src/gallium/drivers/etnaviv/etnaviv_internal.h

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef H_ETNA_INTERNAL
  25 #define H_ETNA_INTERNAL
  26
  27 #include <assert.h>
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #include "hw/state.xml.h"
  32 #include "hw/state_3d.xml.h"
  33
  34 #include <etnaviv_drmif.h>
  35
  36 #define ETNA_NUM_INPUTS (16)
  37 #define ETNA_NUM_VARYINGS 8
  38 #define ETNA_NUM_LOD (14)
  39 #define ETNA_NUM_LAYERS (6)
  40 #define ETNA_MAX_UNIFORMS (256)
  41 #define ETNA_MAX_PIXELPIPES 2
  42
  43 /* All RS operations must have width%16 = 0 */
  44 #define ETNA_RS_WIDTH_MASK (16 - 1)
  45 /* RS tiled operations must have height%4 = 0 */
  46 #define ETNA_RS_HEIGHT_MASK (3)
  47 /* PE render targets must be aligned to 64 bytes */
  48 #define ETNA_PE_ALIGNMENT (64)
  49
  50 /* These demarcate the margin (fixp16) between the computed sizes and the
  51   value sent to the chip. These have been set to the numbers used by the
  52   Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
  53   am not sure whether older hardware was relying on these or they were just a
  54   guess. But if so, these need to be moved to the _specs structure.
  55 */
  56 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
  57 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
  58 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
  59 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
  60
  61 /* GPU chip 3D specs */
  62 struct etna_specs {
  63    /* supports SUPERTILE (64x64) tiling? */
  64    unsigned can_supertile : 1;
  65    /* needs z=(z+w)/2, for older GCxxx */
  66    unsigned vs_need_z_div : 1;
  67    /* supports trigonometric instructions */
  68    unsigned has_sin_cos_sqrt : 1;
  69    /* has SIGN/FLOOR/CEIL instructions */
  70    unsigned has_sign_floor_ceil : 1;
  71    /* can use VS_RANGE, PS_RANGE registers*/
  72    unsigned has_shader_range_registers : 1;
  73    /* has the new sin/cos/log functions */
  74    unsigned has_new_transcendentals : 1;
  75    /* has the new dp2/dpX_norm instructions, among others */
  76    unsigned has_halti2_instructions : 1;
  77    /* supports single-buffer rendering with multiple pixel pipes */
  78    unsigned single_buffer : 1;
  79    /* has unified uniforms memory */
  80    unsigned has_unified_uniforms : 1;
  81    /* can load shader instructions from memory */
  82    unsigned has_icache : 1;
  83    /* ASTC texture support (and has associated states) */
  84    unsigned tex_astc : 1;
  85    /* can use any kind of wrapping mode on npot textures */
  86    unsigned npot_tex_any_wrap;
  87    /* number of bits per TS tile */
  88    unsigned bits_per_tile;
  89    /* clear value for TS (dependent on bits_per_tile) */
  90    uint32_t ts_clear_value;
  91    /* base of vertex texture units */
  92    unsigned vertex_sampler_offset;
  93    /* number of fragment sampler units */
  94    unsigned fragment_sampler_count;
  95    /* number of vertex sampler units */
  96    unsigned vertex_sampler_count;
  97    /* size of vertex shader output buffer */
  98    unsigned vertex_output_buffer_size;
  99    /* maximum number of vertex element configurations */
 100    unsigned vertex_max_elements;
 101    /* size of a cached vertex (?) */
 102    unsigned vertex_cache_size;
 103    /* number of shader cores */
 104    unsigned shader_core_count;
 105    /* number of vertex streams */
 106    unsigned stream_count;
 107    /* vertex shader memory address*/
 108    uint32_t vs_offset;
 109    /* pixel shader memory address*/
 110    uint32_t ps_offset;
 111    /* vertex shader uniforms address*/
 112    uint32_t vs_uniforms_offset;
 113    /* pixel shader uniforms address*/
 114    uint32_t ps_uniforms_offset;
 115    /* vertex/fragment shader max instructions */
 116    uint32_t max_instructions;
 117    /* maximum number of varyings */
 118    unsigned max_varyings;
 119    /* maximum number of registers */
 120    unsigned max_registers;
 121    /* maximum vertex uniforms */
 122    unsigned max_vs_uniforms;
 123    /* maximum pixel uniforms */
 124    unsigned max_ps_uniforms;
 125    /* maximum texture size */
 126    unsigned max_texture_size;
 127    /* maximum texture size */
 128    unsigned max_rendertarget_size;
 129    /* available pixel pipes */
 130    unsigned pixel_pipes;
 131    /* number of constants */
 132    unsigned num_constants;
 133 };
 134
 135 /* Compiled Gallium state. All the different compiled state atoms are woven
 136  * together and uploaded only when it is necessary to synchronize the state,
 137  * for example before rendering. */
 138
 139 /* Compiled pipe_blend_color */
 140 struct compiled_blend_color {
 141    float color[4];
 142    uint32_t PE_ALPHA_BLEND_COLOR;
 143 };
 144
 145 /* Compiled pipe_stencil_ref */
 146 struct compiled_stencil_ref {
 147    uint32_t PE_STENCIL_CONFIG;
 148    uint32_t PE_STENCIL_CONFIG_EXT;
 149 };
 150
 151 /* Compiled pipe_scissor_state */
 152 struct compiled_scissor_state {
 153    uint32_t SE_SCISSOR_LEFT;
 154    uint32_t SE_SCISSOR_TOP;
 155    uint32_t SE_SCISSOR_RIGHT;
 156    uint32_t SE_SCISSOR_BOTTOM;
 157    uint32_t SE_CLIP_RIGHT;
 158    uint32_t SE_CLIP_BOTTOM;
 159 };
 160
 161 /* Compiled pipe_viewport_state */
 162 struct compiled_viewport_state {
 163    uint32_t PA_VIEWPORT_SCALE_X;
 164    uint32_t PA_VIEWPORT_SCALE_Y;
 165    uint32_t PA_VIEWPORT_SCALE_Z;
 166    uint32_t PA_VIEWPORT_OFFSET_X;
 167    uint32_t PA_VIEWPORT_OFFSET_Y;
 168    uint32_t PA_VIEWPORT_OFFSET_Z;
 169    uint32_t SE_SCISSOR_LEFT;
 170    uint32_t SE_SCISSOR_TOP;
 171    uint32_t SE_SCISSOR_RIGHT;
 172    uint32_t SE_SCISSOR_BOTTOM;
 173    uint32_t SE_CLIP_RIGHT;
 174    uint32_t SE_CLIP_BOTTOM;
 175    uint32_t PE_DEPTH_NEAR;
 176    uint32_t PE_DEPTH_FAR;
 177 };
 178
 179 /* Compiled pipe_framebuffer_state */
 180 struct compiled_framebuffer_state {
 181    struct pipe_surface *cbuf, *zsbuf; /* keep reference to surfaces */
 182    uint32_t GL_MULTI_SAMPLE_CONFIG;
 183    uint32_t PE_COLOR_FORMAT;
 184    uint32_t PE_DEPTH_CONFIG;
 185    struct etna_reloc PE_DEPTH_ADDR;
 186    struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
 187    uint32_t PE_DEPTH_STRIDE;
 188    uint32_t PE_HDEPTH_CONTROL;
 189    uint32_t PE_DEPTH_NORMALIZE;
 190    struct etna_reloc PE_COLOR_ADDR;
 191    struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
 192    uint32_t PE_COLOR_STRIDE;
 193    uint32_t SE_SCISSOR_LEFT;
 194    uint32_t SE_SCISSOR_TOP;
 195    uint32_t SE_SCISSOR_RIGHT;
 196    uint32_t SE_SCISSOR_BOTTOM;
 197    uint32_t SE_CLIP_RIGHT;
 198    uint32_t SE_CLIP_BOTTOM;
 199    uint32_t RA_MULTISAMPLE_UNK00E04;
 200    uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
 201    uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
 202    uint32_t TS_MEM_CONFIG;
 203    uint32_t TS_DEPTH_CLEAR_VALUE;
 204    struct etna_reloc TS_DEPTH_STATUS_BASE;
 205    struct etna_reloc TS_DEPTH_SURFACE_BASE;
 206    uint32_t TS_COLOR_CLEAR_VALUE;
 207    struct etna_reloc TS_COLOR_STATUS_BASE;
 208    struct etna_reloc TS_COLOR_SURFACE_BASE;
 209    uint32_t PE_LOGIC_OP;
 210    bool msaa_mode; /* adds input (and possible temp) to PS */
 211 };
 212
 213 /* Compiled context->create_vertex_elements_state */
 214 struct compiled_vertex_elements_state {
 215    unsigned num_elements;
 216    uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
 217 };
 218
 219 /* Compiled context->set_vertex_buffer result */
 220 struct compiled_set_vertex_buffer {
 221    uint32_t FE_VERTEX_STREAM_CONTROL;
 222    struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
 223 };
 224
 225 /* Compiled linked VS+PS shader state */
 226 struct compiled_shader_state {
 227    uint32_t RA_CONTROL;
 228    uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
 229    uint32_t PA_CONFIG;
 230    uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
 231    uint32_t VS_END_PC;
 232    uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
 233    uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
 234    uint32_t VS_INPUT_COUNT;
 235    uint32_t VS_TEMP_REGISTER_CONTROL;
 236    uint32_t VS_OUTPUT[4];
 237    uint32_t VS_INPUT[4];
 238    uint32_t VS_LOAD_BALANCING;
 239    uint32_t VS_START_PC;
 240    uint32_t PS_END_PC;
 241    uint32_t PS_OUTPUT_REG;
 242    uint32_t PS_INPUT_COUNT;
 243    uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
 244    uint32_t PS_TEMP_REGISTER_CONTROL;
 245    uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
 246    uint32_t PS_CONTROL;
 247    uint32_t PS_START_PC;
 248    uint32_t GL_VARYING_TOTAL_COMPONENTS;
 249    uint32_t GL_VARYING_NUM_COMPONENTS;
 250    uint32_t GL_VARYING_COMPONENT_USE[2];
 251    unsigned vs_inst_mem_size;
 252    unsigned vs_uniforms_size;
 253    unsigned ps_inst_mem_size;
 254    unsigned ps_uniforms_size;
 255    uint32_t *VS_INST_MEM;
 256    uint32_t VS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
 257    uint32_t *PS_INST_MEM;
 258    uint32_t PS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
 259    struct etna_reloc PS_INST_ADDR;
 260    struct etna_reloc VS_INST_ADDR;
 261 };
 262
 263 /* state of some 3d and common registers relevant to etna driver */
 264 struct etna_3d_state {
 265    unsigned vs_uniforms_size;
 266    unsigned ps_uniforms_size;
 267
 268    uint32_t /*01008*/ PS_INPUT_COUNT;
 269    uint32_t /*0100C*/ PS_TEMP_REGISTER_CONTROL;
 270    uint32_t /*03818*/ GL_MULTI_SAMPLE_CONFIG;
 271    uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN];
 272    uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN];
 273 };
 274
 275 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
 276  * field_size must be a power of two, and <= 32. */
 277 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
 278    uint32_t name[(num) * (field_size) / 32]
 279
 280 static inline void
 281 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
 282                   size_t index, uint32_t value)
 283 {
 284    size_t shift = (index * field_size) % 32;
 285    size_t offset = (index * field_size) / 32;
 286
 287    assert(index < array_size * 32 / field_size);
 288    assert(value < 1 << field_size);
 289
 290    array[offset] |= value << shift;
 291 }
 292
 293 #define etna_bitarray_set(array, field_size, index, value) \
 294    etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
 295
 296 #endif