src/gallium/drivers/etnaviv/etnaviv_internal.h

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef H_ETNA_INTERNAL
  25 #define H_ETNA_INTERNAL
  26
  27 #include <assert.h>
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 #include "hw/state.xml.h"
  32 #include "hw/state_3d.xml.h"
  33
  34 #include <etnaviv_drmif.h>
  35
  36 #define ETNA_NUM_INPUTS (16)
  37 #define ETNA_NUM_VARYINGS 8
  38 #define ETNA_NUM_LOD (14)
  39 #define ETNA_NUM_LAYERS (6)
  40 #define ETNA_MAX_UNIFORMS (256)
  41 #define ETNA_MAX_PIXELPIPES 2
  42
  43 /* All RS operations must have width%16 = 0 */
  44 #define ETNA_RS_WIDTH_MASK (16 - 1)
  45 /* RS tiled operations must have height%4 = 0 */
  46 #define ETNA_RS_HEIGHT_MASK (3)
  47 /* PE render targets must be aligned to 64 bytes */
  48 #define ETNA_PE_ALIGNMENT (64)
  49
  50 /* GPU chip 3D specs */
  51 struct etna_specs {
  52    /* supports SUPERTILE (64x64) tiling? */
  53    unsigned can_supertile : 1;
  54    /* needs z=(z+w)/2, for older GCxxx */
  55    unsigned vs_need_z_div : 1;
  56    /* supports trigonometric instructions */
  57    unsigned has_sin_cos_sqrt : 1;
  58    /* has SIGN/FLOOR/CEIL instructions */
  59    unsigned has_sign_floor_ceil : 1;
  60    /* can use VS_RANGE, PS_RANGE registers*/
  61    unsigned has_shader_range_registers : 1;
  62    /* can use any kind of wrapping mode on npot textures */
  63    unsigned npot_tex_any_wrap;
  64    /* number of bits per TS tile */
  65    unsigned bits_per_tile;
  66    /* clear value for TS (dependent on bits_per_tile) */
  67    uint32_t ts_clear_value;
  68    /* base of vertex texture units */
  69    unsigned vertex_sampler_offset;
  70    /* number of fragment sampler units */
  71    unsigned fragment_sampler_count;
  72    /* number of vertex sampler units */
  73    unsigned vertex_sampler_count;
  74    /* size of vertex shader output buffer */
  75    unsigned vertex_output_buffer_size;
  76    /* maximum number of vertex element configurations */
  77    unsigned vertex_max_elements;
  78    /* size of a cached vertex (?) */
  79    unsigned vertex_cache_size;
  80    /* number of shader cores */
  81    unsigned shader_core_count;
  82    /* number of vertex streams */
  83    unsigned stream_count;
  84    /* vertex shader memory address*/
  85    uint32_t vs_offset;
  86    /* pixel shader memory address*/
  87    uint32_t ps_offset;
  88    /* vertex/fragment shader max instructions */
  89    uint32_t max_instructions;
  90    /* maximum number of varyings */
  91    unsigned max_varyings;
  92    /* maximum number of registers */
  93    unsigned max_registers;
  94    /* maximum vertex uniforms */
  95    unsigned max_vs_uniforms;
  96    /* maximum pixel uniforms */
  97    unsigned max_ps_uniforms;
  98    /* maximum texture size */
  99    unsigned max_texture_size;
 100    /* maximum texture size */
 101    unsigned max_rendertarget_size;
 102    /* available pixel pipes */
 103    unsigned pixel_pipes;
 104    /* number of constants */
 105    unsigned num_constants;
 106 };
 107
 108 /* Compiled Gallium state. All the different compiled state atoms are woven
 109  * together and uploaded only when it is necessary to synchronize the state,
 110  * for example before rendering. */
 111
 112 /* Compiled pipe_blend_color */
 113 struct compiled_blend_color {
 114    uint32_t PE_ALPHA_BLEND_COLOR;
 115 };
 116
 117 /* Compiled pipe_stencil_ref */
 118 struct compiled_stencil_ref {
 119    uint32_t PE_STENCIL_CONFIG;
 120    uint32_t PE_STENCIL_CONFIG_EXT;
 121 };
 122
 123 /* Compiled pipe_scissor_state */
 124 struct compiled_scissor_state {
 125    uint32_t SE_SCISSOR_LEFT;
 126    uint32_t SE_SCISSOR_TOP;
 127    uint32_t SE_SCISSOR_RIGHT;
 128    uint32_t SE_SCISSOR_BOTTOM;
 129 };
 130
 131 /* Compiled pipe_viewport_state */
 132 struct compiled_viewport_state {
 133    uint32_t PA_VIEWPORT_SCALE_X;
 134    uint32_t PA_VIEWPORT_SCALE_Y;
 135    uint32_t PA_VIEWPORT_SCALE_Z;
 136    uint32_t PA_VIEWPORT_OFFSET_X;
 137    uint32_t PA_VIEWPORT_OFFSET_Y;
 138    uint32_t PA_VIEWPORT_OFFSET_Z;
 139    uint32_t SE_SCISSOR_LEFT;
 140    uint32_t SE_SCISSOR_TOP;
 141    uint32_t SE_SCISSOR_RIGHT;
 142    uint32_t SE_SCISSOR_BOTTOM;
 143    uint32_t PE_DEPTH_NEAR;
 144    uint32_t PE_DEPTH_FAR;
 145 };
 146
 147 /* Compiled pipe_framebuffer_state */
 148 struct compiled_framebuffer_state {
 149    struct pipe_surface *cbuf, *zsbuf; /* keep reference to surfaces */
 150    uint32_t GL_MULTI_SAMPLE_CONFIG;
 151    uint32_t PE_COLOR_FORMAT;
 152    uint32_t PE_DEPTH_CONFIG;
 153    struct etna_reloc PE_DEPTH_ADDR;
 154    struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
 155    uint32_t PE_DEPTH_STRIDE;
 156    uint32_t PE_HDEPTH_CONTROL;
 157    uint32_t PE_DEPTH_NORMALIZE;
 158    struct etna_reloc PE_COLOR_ADDR;
 159    struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
 160    uint32_t PE_COLOR_STRIDE;
 161    uint32_t SE_SCISSOR_LEFT;
 162    uint32_t SE_SCISSOR_TOP;
 163    uint32_t SE_SCISSOR_RIGHT;
 164    uint32_t SE_SCISSOR_BOTTOM;
 165    uint32_t RA_MULTISAMPLE_UNK00E04;
 166    uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
 167    uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
 168    uint32_t TS_MEM_CONFIG;
 169    uint32_t TS_DEPTH_CLEAR_VALUE;
 170    struct etna_reloc TS_DEPTH_STATUS_BASE;
 171    struct etna_reloc TS_DEPTH_SURFACE_BASE;
 172    uint32_t TS_COLOR_CLEAR_VALUE;
 173    struct etna_reloc TS_COLOR_STATUS_BASE;
 174    struct etna_reloc TS_COLOR_SURFACE_BASE;
 175    bool msaa_mode; /* adds input (and possible temp) to PS */
 176 };
 177
 178 /* Compiled context->create_vertex_elements_state */
 179 struct compiled_vertex_elements_state {
 180    unsigned num_elements;
 181    uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
 182 };
 183
 184 /* Compiled context->set_vertex_buffer result */
 185 struct compiled_set_vertex_buffer {
 186    uint32_t FE_VERTEX_STREAM_CONTROL;
 187    struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
 188 };
 189
 190 /* Compiled linked VS+PS shader state */
 191 struct compiled_shader_state {
 192    uint32_t RA_CONTROL;
 193    uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
 194    uint32_t PA_CONFIG;
 195    uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
 196    uint32_t VS_END_PC;
 197    uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
 198    uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
 199    uint32_t VS_INPUT_COUNT;
 200    uint32_t VS_TEMP_REGISTER_CONTROL;
 201    uint32_t VS_OUTPUT[4];
 202    uint32_t VS_INPUT[4];
 203    uint32_t VS_LOAD_BALANCING;
 204    uint32_t VS_START_PC;
 205    uint32_t PS_END_PC;
 206    uint32_t PS_OUTPUT_REG;
 207    uint32_t PS_INPUT_COUNT;
 208    uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
 209    uint32_t PS_TEMP_REGISTER_CONTROL;
 210    uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
 211    uint32_t PS_CONTROL;
 212    uint32_t PS_START_PC;
 213    uint32_t GL_VARYING_TOTAL_COMPONENTS;
 214    uint32_t GL_VARYING_NUM_COMPONENTS;
 215    uint32_t GL_VARYING_COMPONENT_USE[2];
 216    unsigned vs_inst_mem_size;
 217    unsigned vs_uniforms_size;
 218    unsigned ps_inst_mem_size;
 219    unsigned ps_uniforms_size;
 220    uint32_t *VS_INST_MEM;
 221    uint32_t VS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
 222    uint32_t *PS_INST_MEM;
 223    uint32_t PS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
 224 };
 225
 226 /* state of some 3d and common registers relevant to etna driver */
 227 struct etna_3d_state {
 228    unsigned vs_uniforms_size;
 229    unsigned ps_uniforms_size;
 230
 231    uint32_t /*01008*/ PS_INPUT_COUNT;
 232    uint32_t /*0100C*/ PS_TEMP_REGISTER_CONTROL;
 233    uint32_t /*03818*/ GL_MULTI_SAMPLE_CONFIG;
 234    uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN];
 235    uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN];
 236 };
 237
 238 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
 239  * field_size must be a power of two, and <= 32. */
 240 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
 241    uint32_t name[(num) * (field_size) / 32]
 242
 243 static inline void
 244 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
 245                   size_t index, uint32_t value)
 246 {
 247    size_t shift = (index * field_size) % 32;
 248    size_t offset = (index * field_size) / 32;
 249
 250    assert(index < array_size * 32 / field_size);
 251    assert(value < 1 << field_size);
 252
 253    array[offset] |= value << shift;
 254 }
 255
 256 #define etna_bitarray_set(array, field_size, index, value) \
 257    etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
 258
 259 #endif