src/gallium/drivers/etnaviv/etnaviv_nir.c

   1 /*
   2  * Copyright (c) 2019 Zodiac Inflight Innovations
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Jonathan Marek <jonathan@marek.ca>
  25  */
  26
  27 #include "etnaviv_nir.h"
  28
  29 /* io related lowering
  30  * run after lower_int_to_float because it adds i2f/f2i ops
  31  */
  32 void
  33 etna_lower_io(nir_shader *shader, struct etna_shader_variant *v)
  34 {
  35    nir_foreach_function(function, shader) {
  36       nir_builder b;
  37       nir_builder_init(&b, function->impl);
  38
  39       nir_foreach_block(block, function->impl) {
  40          nir_foreach_instr_safe(instr, block) {
  41             if (instr->type == nir_instr_type_intrinsic) {
  42                nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
  43
  44                switch (intr->intrinsic) {
  45                case nir_intrinsic_load_front_face: {
  46                   /* HW front_face is 0.0/1.0, not 0/~0u for bool
  47                    * lower with a comparison with 0
  48                    */
  49                   intr->dest.ssa.bit_size = 32;
  50
  51                   b.cursor = nir_after_instr(instr);
  52
  53                   nir_ssa_def *ssa = nir_ine(&b, &intr->dest.ssa, nir_imm_int(&b, 0));
  54                   if (v->key.front_ccw)
  55                      nir_instr_as_alu(ssa->parent_instr)->op = nir_op_ieq;
  56
  57                   nir_ssa_def_rewrite_uses_after(&intr->dest.ssa,
  58                                                  nir_src_for_ssa(ssa),
  59                                                  ssa->parent_instr);
  60                } break;
  61                case nir_intrinsic_store_deref: {
  62                   nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
  63                   if (shader->info.stage != MESA_SHADER_FRAGMENT || !v->key.frag_rb_swap)
  64                      break;
  65
  66                   assert(deref->deref_type == nir_deref_type_var);
  67
  68                   if (deref->var->data.location != FRAG_RESULT_COLOR &&
  69                       deref->var->data.location != FRAG_RESULT_DATA0)
  70                       break;
  71
  72                   b.cursor = nir_before_instr(instr);
  73
  74                   nir_ssa_def *ssa = nir_mov(&b, intr->src[1].ssa);
  75                   nir_alu_instr *alu = nir_instr_as_alu(ssa->parent_instr);
  76                   alu->src[0].swizzle[0] = 2;
  77                   alu->src[0].swizzle[2] = 0;
  78                   nir_instr_rewrite_src(instr, &intr->src[1], nir_src_for_ssa(ssa));
  79                } break;
  80                case nir_intrinsic_load_uniform: {
  81                   /* convert indirect load_uniform to load_ubo when possible
  82                    * this is required on HALTI5+ because address register is not implemented
  83                    * address register loads also arent done optimally
  84                    */
  85                   if (v->shader->specs->halti < 2 || nir_src_is_const(intr->src[0]))
  86                      break;
  87
  88                   nir_intrinsic_instr *load_ubo =
  89                      nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ubo);
  90                   load_ubo->num_components = intr->num_components;
  91                   nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
  92                                     load_ubo->num_components, 32, NULL);
  93
  94                   b.cursor = nir_before_instr(instr);
  95                   load_ubo->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
  96                   load_ubo->src[1] = nir_src_for_ssa(nir_iadd(&b,
  97                      nir_imul(&b, intr->src[0].ssa, nir_imm_int(&b, 16)),
  98                      nir_imm_int(&b, nir_intrinsic_base(intr) * 16)));
  99                   nir_builder_instr_insert(&b, &load_ubo->instr);
 100                   nir_ssa_def_rewrite_uses(&intr->dest.ssa,
 101                                              nir_src_for_ssa(&load_ubo->dest.ssa));
 102                   nir_instr_remove(&intr->instr);
 103                } break;
 104                case nir_intrinsic_load_ubo: {
 105                   nir_const_value *idx = nir_src_as_const_value(intr->src[0]);
 106                   assert(idx);
 107                   /* offset index by 1, index 0 is used for converted load_uniform */
 108                   b.cursor = nir_before_instr(instr);
 109                   nir_instr_rewrite_src(instr, &intr->src[0],
 110                                         nir_src_for_ssa(nir_imm_int(&b, idx[0].u32 + 1)));
 111                } break;
 112                case nir_intrinsic_load_vertex_id:
 113                case nir_intrinsic_load_instance_id:
 114                   /* detect use of vertex_id/instance_id */
 115                   v->vs_id_in_reg = v->infile.num_reg;
 116                   break;
 117                default:
 118                   break;
 119                }
 120             }
 121
 122             if (instr->type != nir_instr_type_tex)
 123                continue;
 124
 125             nir_tex_instr *tex = nir_instr_as_tex(instr);
 126             nir_src *coord = NULL;
 127             nir_src *lod_bias = NULL;
 128             unsigned lod_bias_idx;
 129
 130             assert(tex->sampler_index == tex->texture_index);
 131
 132             for (unsigned i = 0; i < tex->num_srcs; i++) {
 133                switch (tex->src[i].src_type) {
 134                case nir_tex_src_coord:
 135                   coord = &tex->src[i].src;
 136                   break;
 137                case nir_tex_src_bias:
 138                case nir_tex_src_lod:
 139                   assert(!lod_bias);
 140                   lod_bias = &tex->src[i].src;
 141                   lod_bias_idx = i;
 142                   break;
 143                case nir_tex_src_comparator:
 144                   break;
 145                default:
 146                   assert(0);
 147                   break;
 148                }
 149             }
 150
 151             if (tex->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
 152                /* use a dummy load_uniform here to represent texcoord scale */
 153                b.cursor = nir_before_instr(instr);
 154                nir_intrinsic_instr *load =
 155                   nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_uniform);
 156                nir_intrinsic_set_base(load, ~tex->sampler_index);
 157                load->num_components = 2;
 158                load->src[0] = nir_src_for_ssa(nir_imm_float(&b, 0.0f));
 159                nir_ssa_dest_init(&load->instr, &load->dest, 2, 32, NULL);
 160                nir_intrinsic_set_type(load, nir_type_float);
 161
 162                nir_builder_instr_insert(&b, &load->instr);
 163
 164                nir_ssa_def *new_coord = nir_fmul(&b, coord->ssa, &load->dest.ssa);
 165                nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(new_coord));
 166             }
 167
 168             /* pre HALTI5 needs texture sources in a single source */
 169
 170             if (!lod_bias || v->shader->specs->halti >= 5)
 171                continue;
 172
 173             assert(coord && lod_bias && tex->coord_components < 4);
 174
 175             nir_alu_instr *vec = nir_alu_instr_create(shader, nir_op_vec4);
 176             for (unsigned i = 0; i < tex->coord_components; i++) {
 177                vec->src[i].src = nir_src_for_ssa(coord->ssa);
 178                vec->src[i].swizzle[0] = i;
 179             }
 180             for (unsigned i = tex->coord_components; i < 4; i++)
 181                vec->src[i].src = nir_src_for_ssa(lod_bias->ssa);
 182
 183             vec->dest.write_mask = 0xf;
 184             nir_ssa_dest_init(&vec->instr, &vec->dest.dest, 4, 32, NULL);
 185
 186             nir_tex_instr_remove_src(tex, lod_bias_idx);
 187             nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(&vec->dest.dest.ssa));
 188             tex->coord_components = 4;
 189
 190             nir_instr_insert_before(&tex->instr, &vec->instr);
 191          }
 192       }
 193    }
 194 }