src/gallium/drivers/etnaviv/etnaviv_rs.c

   1 /*
   2  * Copyright (c) 2012-2017 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_rs.h"
  28
  29 #include "etnaviv_clear_blit.h"
  30 #include "etnaviv_context.h"
  31 #include "etnaviv_emit.h"
  32 #include "etnaviv_format.h"
  33 #include "etnaviv_resource.h"
  34 #include "etnaviv_screen.h"
  35 #include "etnaviv_surface.h"
  36 #include "etnaviv_tiling.h"
  37 #include "etnaviv_translate.h"
  38 #include "etnaviv_util.h"
  39
  40 #include "pipe/p_defines.h"
  41 #include "pipe/p_state.h"
  42 #include "util/u_blitter.h"
  43 #include "util/u_inlines.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_surface.h"
  46
  47 #include "hw/common.xml.h"
  48 #include "hw/state.xml.h"
  49 #include "hw/state_3d.xml.h"
  50
  51 #include <assert.h>
  52
  53 void
  54 etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
  55                       const struct rs_state *rs)
  56 {
  57    memset(cs, 0, sizeof(*cs));
  58
  59    /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
  60    unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2);
  61    unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2);
  62
  63    /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
  64    int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
  65    int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
  66
  67    /* Vivante RS needs widths to be a multiple of 16 or bad things
  68     * happen, such as scribbing over memory, or the GPU hanging,
  69     * even for non-tiled formats.  As this is serious, use abort().
  70     */
  71    if (rs->width & ETNA_RS_WIDTH_MASK)
  72       abort();
  73
  74    /* TODO could just pre-generate command buffer, would simply submit to one memcpy */
  75    cs->RS_CONFIG = VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) |
  76                    COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) |
  77                    COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) |
  78                    COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) |
  79                    VIVS_RS_CONFIG_DEST_FORMAT(rs->dest_format) |
  80                    COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) |
  81                    COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) |
  82                    COND(rs->flip, VIVS_RS_CONFIG_FLIP);
  83
  84    cs->RS_SOURCE_STRIDE = (rs->source_stride << source_stride_shift) |
  85                           COND(rs->source_tiling & 2, VIVS_RS_SOURCE_STRIDE_TILING) |
  86                           COND(source_multi, VIVS_RS_SOURCE_STRIDE_MULTI);
  87
  88    /* Initially all pipes are set to the base address of the source and
  89     * destination buffer respectively. This will be overridden below as
  90     * necessary for the multi-pipe, multi-tiled case.
  91     */
  92    for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
  93       cs->source[pipe].bo = rs->source;
  94       cs->source[pipe].offset = rs->source_offset;
  95       cs->source[pipe].flags = ETNA_RELOC_READ;
  96
  97       cs->dest[pipe].bo = rs->dest;
  98       cs->dest[pipe].offset = rs->dest_offset;
  99       cs->dest[pipe].flags = ETNA_RELOC_WRITE;
 100
 101       cs->RS_PIPE_OFFSET[pipe] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
 102    }
 103
 104    cs->RS_DEST_STRIDE = (rs->dest_stride << dest_stride_shift) |
 105                         COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) |
 106                         COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI);
 107
 108
 109    if (source_multi)
 110       cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
 111
 112    if (dest_multi)
 113       cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
 114
 115    cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
 116                         VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
 117
 118    /* use dual pipe mode when required */
 119    if (!ctx->specs.single_buffer && ctx->specs.pixel_pipes == 2 && !(rs->height & 7)) {
 120       cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
 121                               VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
 122       cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2);
 123    }
 124
 125    cs->RS_DITHER[0] = rs->dither[0];
 126    cs->RS_DITHER[1] = rs->dither[1];
 127    cs->RS_CLEAR_CONTROL = VIVS_RS_CLEAR_CONTROL_BITS(rs->clear_bits) | rs->clear_mode;
 128    cs->RS_FILL_VALUE[0] = rs->clear_value[0];
 129    cs->RS_FILL_VALUE[1] = rs->clear_value[1];
 130    cs->RS_FILL_VALUE[2] = rs->clear_value[2];
 131    cs->RS_FILL_VALUE[3] = rs->clear_value[3];
 132    cs->RS_EXTRA_CONFIG = VIVS_RS_EXTRA_CONFIG_AA(rs->aa) |
 133                          VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode);
 134
 135    /* If source the same as destination, and the hardware supports this,
 136     * do an in-place resolve to fill in unrendered tiles.
 137     */
 138    if (ctx->specs.single_buffer && rs->source == rs->dest &&
 139          rs->source_offset == rs->dest_offset &&
 140          rs->source_format == rs->dest_format &&
 141          rs->source_tiling == rs->dest_tiling &&
 142          (rs->source_tiling & ETNA_LAYOUT_BIT_SUPER) &&
 143          rs->source_stride == rs->dest_stride &&
 144          !rs->downsample_x && !rs->downsample_y &&
 145          !rs->swap_rb && !rs->flip &&
 146          !rs->clear_mode && rs->source_padded_width &&
 147          !rs->source_ts_compressed) {
 148       /* Total number of tiles (same as for autodisable) */
 149       cs->RS_KICKER_INPLACE = rs->tile_count;
 150    }
 151    cs->source_ts_valid = rs->source_ts_valid;
 152 }
 153
 154 /* modify the clear bits value in the compiled RS state */
 155 static void
 156 etna_modify_rs_clearbits(struct compiled_rs_state *cs, uint32_t clear_bits)
 157 {
 158    cs->RS_CLEAR_CONTROL &= ~VIVS_RS_CLEAR_CONTROL_BITS__MASK;
 159    cs->RS_CLEAR_CONTROL |= VIVS_RS_CLEAR_CONTROL_BITS(clear_bits);
 160 }
 161
 162 #define EMIT_STATE(state_name, src_value) \
 163    etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
 164
 165 #define EMIT_STATE_FIXP(state_name, src_value) \
 166    etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
 167
 168 #define EMIT_STATE_RELOC(state_name, src_value) \
 169    etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
 170
 171 /* submit RS state, without any processing and no dependence on context
 172  * except TS if this is a source-to-destination blit. */
 173 static void
 174 etna_submit_rs_state(struct etna_context *ctx,
 175                      const struct compiled_rs_state *cs)
 176 {
 177    struct etna_screen *screen = etna_screen(ctx->base.screen);
 178    struct etna_cmd_stream *stream = ctx->stream;
 179    struct etna_coalesce coalesce;
 180
 181    if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
 182       /* Inplace resolve is no-op if TS is not configured */
 183       return;
 184
 185    ctx->stats.rs_operations++;
 186
 187    if (cs->RS_KICKER_INPLACE) {
 188       etna_cmd_stream_reserve(stream, 6);
 189       etna_coalesce_start(stream, &coalesce);
 190       /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
 191       /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
 192       /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE);
 193       etna_coalesce_end(stream, &coalesce);
 194    } else if (screen->specs.pixel_pipes == 1) {
 195       etna_cmd_stream_reserve(stream, 22);
 196       etna_coalesce_start(stream, &coalesce);
 197       /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
 198       /* 2   */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]);
 199       /* 3   */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
 200       /* 4   */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]);
 201       /* 5   */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
 202       /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
 203       /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
 204       /*10   */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
 205       /*11 - pad */
 206       /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
 207       /*14   */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
 208       /*15   */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
 209       /*16   */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
 210       /*17   */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
 211       /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
 212       /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
 213       etna_coalesce_end(stream, &coalesce);
 214    } else if (screen->specs.pixel_pipes == 2) {
 215       etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */
 216       etna_coalesce_start(stream, &coalesce);
 217       /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
 218       /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
 219       /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
 220       /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs->source[0]);
 221       if (cs->RS_SOURCE_STRIDE & VIVS_RS_SOURCE_STRIDE_MULTI) {
 222          /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs->source[1]);
 223          /*9 - pad */
 224       }
 225       /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs->dest[0]);
 226       if (cs->RS_DEST_STRIDE & VIVS_RS_DEST_STRIDE_MULTI) {
 227          /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs->dest[1]);
 228          /*13 - pad */
 229       }
 230       /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs->RS_PIPE_OFFSET[0]);
 231       /*16   */ EMIT_STATE(RS_PIPE_OFFSET(1), cs->RS_PIPE_OFFSET[1]);
 232       /*17 - pad */
 233       /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
 234       /*20/21*/ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
 235       /*22   */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
 236       /*23 - pad */
 237       /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
 238       /*26   */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
 239       /*27   */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
 240       /*28   */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
 241       /*29   */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
 242       /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
 243       /*32/33*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
 244       etna_coalesce_end(stream, &coalesce);
 245    } else {
 246       abort();
 247    }
 248 }
 249
 250 /* Generate clear command for a surface (non-fast clear case) */
 251 void
 252 etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf,
 253                           uint32_t clear_value)
 254 {
 255    struct etna_resource *dst = etna_resource(surf->base.texture);
 256    uint32_t format;
 257
 258    switch (util_format_get_blocksizebits(surf->base.format)) {
 259    case 16:
 260       format = RS_FORMAT_A4R4G4B4;
 261       break;
 262    case 32:
 263       format = RS_FORMAT_A8R8G8B8;
 264       break;
 265    case 64:
 266       assert(ctx->specs.halti >= 2);
 267       format = RS_FORMAT_64BPP_CLEAR;
 268       break;
 269    default:
 270       unreachable("bpp not supported for clear by RS");
 271       break;
 272    }
 273
 274    /* use tiled clear if width is multiple of 16 */
 275    bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
 276                       (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
 277
 278    etna_compile_rs_state( ctx, &surf->clear_command, &(struct rs_state) {
 279       .source_format = format,
 280       .dest_format = format,
 281       .dest = dst->bo,
 282       .dest_offset = surf->surf.offset,
 283       .dest_stride = surf->surf.stride,
 284       .dest_padded_height = surf->surf.padded_height,
 285       .dest_tiling = tiled_clear ? dst->layout : ETNA_LAYOUT_LINEAR,
 286       .dither = {0xffffffff, 0xffffffff},
 287       .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
 288       .height = surf->surf.padded_height,
 289       .clear_value = {clear_value},
 290       .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
 291       .clear_bits = 0xffff
 292    });
 293 }
 294
 295 static void
 296 etna_blit_clear_color_rs(struct pipe_context *pctx, struct pipe_surface *dst,
 297                       const union pipe_color_union *color)
 298 {
 299    struct etna_context *ctx = etna_context(pctx);
 300    struct etna_surface *surf = etna_surface(dst);
 301    uint32_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color->f);
 302
 303    if (surf->surf.ts_size) { /* TS: use precompiled clear command */
 304       ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
 305
 306       if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
 307          /* Set number of color tiles to be filled */
 308          etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
 309                         surf->surf.padded_width * surf->surf.padded_height / 16);
 310          ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE;
 311       }
 312
 313       surf->level->ts_valid = true;
 314       ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
 315    } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
 316       /* If clear color changed, re-generate stored command */
 317       etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
 318    }
 319
 320    etna_submit_rs_state(ctx, &surf->clear_command);
 321
 322    surf->level->clear_value = new_clear_value;
 323    resource_written(ctx, surf->base.texture);
 324    etna_resource(surf->base.texture)->seqno++;
 325 }
 326
 327 static void
 328 etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst,
 329                    unsigned buffers, double depth, unsigned stencil)
 330 {
 331    struct etna_context *ctx = etna_context(pctx);
 332    struct etna_surface *surf = etna_surface(dst);
 333    uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
 334    uint32_t new_clear_bits = 0, clear_bits_depth, clear_bits_stencil;
 335
 336    /* Get the channels to clear */
 337    switch (surf->base.format) {
 338    case PIPE_FORMAT_Z16_UNORM:
 339       clear_bits_depth = 0xffff;
 340       clear_bits_stencil = 0;
 341       break;
 342    case PIPE_FORMAT_X8Z24_UNORM:
 343    case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 344       clear_bits_depth = 0xeeee;
 345       clear_bits_stencil = 0x1111;
 346       break;
 347    default:
 348       clear_bits_depth = clear_bits_stencil = 0xffff;
 349       break;
 350    }
 351
 352    if (buffers & PIPE_CLEAR_DEPTH)
 353       new_clear_bits |= clear_bits_depth;
 354    if (buffers & PIPE_CLEAR_STENCIL)
 355       new_clear_bits |= clear_bits_stencil;
 356    /* FIXME: when tile status is enabled, this becomes more complex as
 357     * we may separately clear the depth from the stencil.  In this case,
 358     * we want to resolve the surface, and avoid using the tile status.
 359     * We may be better off recording the pending clear operation,
 360     * delaying the actual clear to the first use.  This way, we can merge
 361     * consecutive clears together. */
 362    if (surf->surf.ts_size) { /* TS: use precompiled clear command */
 363       /* Set new clear depth value */
 364       ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
 365       if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
 366          /* Set number of depth tiles to be filled */
 367          etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT,
 368                         surf->surf.padded_width * surf->surf.padded_height / 16);
 369          ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE;
 370       }
 371
 372       surf->level->ts_valid = true;
 373       ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
 374    } else {
 375       if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
 376          /* If clear depth value changed, re-generate stored command */
 377          etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
 378       }
 379       /* Update the channels to be cleared */
 380       etna_modify_rs_clearbits(&surf->clear_command, new_clear_bits);
 381    }
 382
 383    etna_submit_rs_state(ctx, &surf->clear_command);
 384
 385    surf->level->clear_value = new_clear_value;
 386    resource_written(ctx, surf->base.texture);
 387    etna_resource(surf->base.texture)->seqno++;
 388 }
 389
 390 static void
 391 etna_clear_rs(struct pipe_context *pctx, unsigned buffers,
 392            const union pipe_color_union *color, double depth, unsigned stencil)
 393 {
 394    struct etna_context *ctx = etna_context(pctx);
 395
 396    /* Flush color and depth cache before clearing anything.
 397     * This is especially important when coming from another surface, as
 398     * otherwise it may clear part of the old surface instead. */
 399    etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
 400    etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 401
 402    /* Preparation: Flush the TS if needed. This must be done after flushing
 403     * color and depth, otherwise it can result in crashes */
 404    bool need_ts_flush = false;
 405    if ((buffers & PIPE_CLEAR_COLOR) && ctx->framebuffer_s.nr_cbufs) {
 406       struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 407       if (surf->surf.ts_size)
 408          need_ts_flush = true;
 409    }
 410    if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL) {
 411       struct etna_surface *surf = etna_surface(ctx->framebuffer_s.zsbuf);
 412
 413       if (surf->surf.ts_size)
 414          need_ts_flush = true;
 415    }
 416
 417    if (need_ts_flush)
 418       etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
 419
 420    /* No need to set up the TS here as RS clear operations (in contrast to
 421     * resolve and copy) do not require the TS state.
 422     */
 423    if (buffers & PIPE_CLEAR_COLOR) {
 424       for (int idx = 0; idx < ctx->framebuffer_s.nr_cbufs; ++idx) {
 425          etna_blit_clear_color_rs(pctx, ctx->framebuffer_s.cbufs[idx],
 426                                &color[idx]);
 427       }
 428    }
 429
 430    /* Flush the color and depth caches before each RS clear operation
 431     * This fixes a hang on GC600. */
 432    if (buffers & PIPE_CLEAR_DEPTHSTENCIL && buffers & PIPE_CLEAR_COLOR)
 433       etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
 434                      VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
 435
 436    if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL)
 437       etna_blit_clear_zs_rs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
 438
 439    etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 440 }
 441
 442 static bool
 443 etna_manual_blit(struct etna_resource *dst, struct etna_resource_level *dst_lev,
 444                  unsigned int dst_offset, struct etna_resource *src,
 445                  struct etna_resource_level *src_lev, unsigned int src_offset,
 446                  const struct pipe_blit_info *blit_info)
 447 {
 448    void *smap, *srow, *dmap, *drow;
 449    size_t tile_size;
 450
 451    assert(src->layout == ETNA_LAYOUT_TILED);
 452    assert(dst->layout == ETNA_LAYOUT_TILED);
 453    assert(src->base.nr_samples == 0);
 454    assert(dst->base.nr_samples == 0);
 455
 456    tile_size = util_format_get_blocksize(blit_info->src.format) * 4 * 4;
 457
 458    smap = etna_bo_map(src->bo);
 459    if (!smap)
 460       return false;
 461
 462    dmap = etna_bo_map(dst->bo);
 463    if (!dmap)
 464       return false;
 465
 466    srow = smap + src_offset;
 467    drow = dmap + dst_offset;
 468
 469    etna_bo_cpu_prep(src->bo, DRM_ETNA_PREP_READ);
 470    etna_bo_cpu_prep(dst->bo, DRM_ETNA_PREP_WRITE);
 471
 472    for (int y = 0; y < blit_info->src.box.height; y += 4) {
 473       memcpy(drow, srow, tile_size * blit_info->src.box.width);
 474       srow += src_lev->stride * 4;
 475       drow += dst_lev->stride * 4;
 476    }
 477
 478    etna_bo_cpu_fini(dst->bo);
 479    etna_bo_cpu_fini(src->bo);
 480
 481    return true;
 482 }
 483
 484 static inline size_t
 485 etna_compute_tileoffset(const struct pipe_box *box, enum pipe_format format,
 486                         size_t stride, enum etna_surface_layout layout)
 487 {
 488    size_t offset;
 489    unsigned int x = box->x, y = box->y;
 490    unsigned int blocksize = util_format_get_blocksize(format);
 491
 492    switch (layout) {
 493    case ETNA_LAYOUT_LINEAR:
 494       offset = y * stride + x * blocksize;
 495       break;
 496    case ETNA_LAYOUT_MULTI_TILED:
 497       y >>= 1;
 498       /* fall-through */
 499    case ETNA_LAYOUT_TILED:
 500       assert(!(x & 0x03) && !(y & 0x03));
 501       offset = (y & ~0x03) * stride + blocksize * ((x & ~0x03) << 2);
 502       break;
 503    case ETNA_LAYOUT_MULTI_SUPERTILED:
 504       y >>= 1;
 505       /* fall-through */
 506    case ETNA_LAYOUT_SUPER_TILED:
 507       assert(!(x & 0x3f) && !(y & 0x3f));
 508       offset = (y & ~0x3f) * stride + blocksize * ((x & ~0x3f) << 6);
 509       break;
 510    default:
 511       unreachable("invalid resource layout");
 512    }
 513
 514    return offset;
 515 }
 516
 517 static inline void
 518 etna_get_rs_alignment_mask(const struct etna_context *ctx,
 519                            const enum etna_surface_layout layout,
 520                            unsigned int *width_mask, unsigned int *height_mask)
 521 {
 522    unsigned int h_align, w_align;
 523
 524    if (layout & ETNA_LAYOUT_BIT_SUPER) {
 525       w_align = 64;
 526       h_align = 64 * ctx->specs.pixel_pipes;
 527    } else {
 528       w_align = ETNA_RS_WIDTH_MASK + 1;
 529       h_align = ETNA_RS_HEIGHT_MASK + 1;
 530    }
 531
 532    *width_mask = w_align - 1;
 533    *height_mask = h_align -1;
 534 }
 535
 536 static bool
 537 etna_try_rs_blit(struct pipe_context *pctx,
 538                  const struct pipe_blit_info *blit_info)
 539 {
 540    struct etna_context *ctx = etna_context(pctx);
 541    struct etna_resource *src = etna_resource(blit_info->src.resource);
 542    struct etna_resource *dst = etna_resource(blit_info->dst.resource);
 543    struct compiled_rs_state copy_to_screen;
 544    int msaa_xscale = 1, msaa_yscale = 1;
 545
 546    /* Ensure that the level is valid */
 547    assert(blit_info->src.level <= src->base.last_level);
 548    assert(blit_info->dst.level <= dst->base.last_level);
 549
 550    if (!translate_samples_to_xyscale(src->base.nr_samples, &msaa_xscale, &msaa_yscale, NULL))
 551       return false;
 552
 553    /* The width/height are in pixels; they do not change as a result of
 554     * multi-sampling. So, when blitting from a 4x multisampled surface
 555     * to a non-multisampled surface, the width and height will be
 556     * identical. As we do not support scaling, reject different sizes. */
 557    if (blit_info->dst.box.width != blit_info->src.box.width ||
 558        blit_info->dst.box.height != blit_info->src.box.height) {
 559       DBG("scaling requested: source %dx%d destination %dx%d",
 560           blit_info->src.box.width, blit_info->src.box.height,
 561           blit_info->dst.box.width, blit_info->dst.box.height);
 562       return false;
 563    }
 564
 565    /* No masks - RS can't copy specific channels */
 566    unsigned mask = util_format_get_mask(blit_info->dst.format);
 567    if ((blit_info->mask & mask) != mask) {
 568       DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info->mask, mask);
 569       return false;
 570    }
 571
 572    unsigned src_format = blit_info->src.format;
 573    unsigned dst_format = blit_info->dst.format;
 574
 575    /* for a copy with same dst/src format, we can use a different format */
 576    if (translate_rs_format(src_format) == ETNA_NO_MATCH &&
 577        src_format == dst_format) {
 578       src_format = dst_format = etna_compatible_rs_format(src_format);
 579    }
 580
 581    if (translate_rs_format(src_format) == ETNA_NO_MATCH ||
 582        translate_rs_format(dst_format) == ETNA_NO_MATCH ||
 583        blit_info->scissor_enable ||
 584        blit_info->dst.box.depth != blit_info->src.box.depth ||
 585        blit_info->dst.box.depth != 1) {
 586       return false;
 587    }
 588
 589    unsigned w_mask, h_mask;
 590
 591    etna_get_rs_alignment_mask(ctx, src->layout, &w_mask, &h_mask);
 592    if ((blit_info->src.box.x & w_mask) || (blit_info->src.box.y & h_mask))
 593       return false;
 594
 595    etna_get_rs_alignment_mask(ctx, dst->layout, &w_mask, &h_mask);
 596    if ((blit_info->dst.box.x & w_mask) || (blit_info->dst.box.y & h_mask))
 597       return false;
 598
 599    struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
 600    struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
 601
 602    /* we may be given coordinates up to the padded width to avoid
 603     * any alignment issues with different tiling formats */
 604    assert((blit_info->src.box.x + blit_info->src.box.width) * msaa_xscale <= src_lev->padded_width);
 605    assert((blit_info->src.box.y + blit_info->src.box.height) * msaa_yscale <= src_lev->padded_height);
 606    assert(blit_info->dst.box.x + blit_info->dst.box.width <= dst_lev->padded_width);
 607    assert(blit_info->dst.box.y + blit_info->dst.box.height <= dst_lev->padded_height);
 608
 609    unsigned src_offset = src_lev->offset +
 610                          blit_info->src.box.z * src_lev->layer_stride +
 611                          etna_compute_tileoffset(&blit_info->src.box,
 612                                                  blit_info->src.format,
 613                                                  src_lev->stride,
 614                                                  src->layout);
 615    unsigned dst_offset = dst_lev->offset +
 616                          blit_info->dst.box.z * dst_lev->layer_stride +
 617                          etna_compute_tileoffset(&blit_info->dst.box,
 618                                                  blit_info->dst.format,
 619                                                  dst_lev->stride,
 620                                                  dst->layout);
 621
 622    if (src_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
 623        dst_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
 624        src_lev->padded_height <= ETNA_RS_HEIGHT_MASK ||
 625        dst_lev->padded_height <= ETNA_RS_HEIGHT_MASK)
 626       goto manual;
 627
 628    /* If the width is not aligned to the RS width, but is within our
 629     * padding, adjust the width to suite the RS width restriction.
 630     * Note: the RS width/height are converted to source samples here. */
 631    unsigned int width = blit_info->src.box.width * msaa_xscale;
 632    unsigned int height = blit_info->src.box.height * msaa_yscale;
 633    unsigned int w_align = ETNA_RS_WIDTH_MASK + 1;
 634    unsigned int h_align = ETNA_RS_HEIGHT_MASK + 1;
 635
 636    if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
 637       width = align(width, w_align);
 638
 639    if (height & (h_align - 1) && height >= src_lev->height * msaa_yscale && height >= dst_lev->height)
 640       height = align(height, h_align);
 641
 642    /* The padded dimensions are in samples */
 643    if (width > src_lev->padded_width ||
 644        width > dst_lev->padded_width * msaa_xscale ||
 645        height > src_lev->padded_height ||
 646        height > dst_lev->padded_height * msaa_yscale ||
 647        width & (w_align - 1) || height & (h_align - 1))
 648       goto manual;
 649
 650    /* Always flush color and depth cache together before resolving. This works
 651     * around artifacts that appear in some cases when scanning out a texture
 652     * directly after it has been rendered to, such as rendering an animated web
 653     * page in a QtWebEngine based WebView on GC2000. The artifacts look like
 654     * the texture sampler samples zeroes instead of texture data in a small,
 655     * irregular triangle in the lower right of each browser tile quad. Other
 656     * attempts to avoid these artifacts, including a pipeline stall before the
 657     * color flush or a TS cache flush afterwards, or flushing multiple times,
 658     * with stalls before and after each flush, have shown no effect. */
 659    if (src->base.bind & PIPE_BIND_RENDER_TARGET ||
 660        src->base.bind & PIPE_BIND_DEPTH_STENCIL) {
 661       etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
 662                      VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
 663       etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 664
 665       if (src_lev->ts_size && src_lev->ts_valid)
 666          etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
 667    }
 668
 669    /* Set up color TS to source surface before blit, if needed */
 670    bool source_ts_valid = false;
 671    if (src_lev->ts_size && src_lev->ts_valid) {
 672       struct etna_reloc reloc;
 673       unsigned ts_offset =
 674          src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
 675       uint32_t ts_mem_config = 0;
 676
 677       if (src_lev->ts_compress_fmt >= 0) {
 678          ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 679                           VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(src_lev->ts_compress_fmt);
 680       }
 681
 682       etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG,
 683                      VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config);
 684
 685       memset(&reloc, 0, sizeof(struct etna_reloc));
 686       reloc.bo = src->ts_bo;
 687       reloc.offset = ts_offset;
 688       reloc.flags = ETNA_RELOC_READ;
 689       etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_STATUS_BASE, &reloc);
 690
 691       memset(&reloc, 0, sizeof(struct etna_reloc));
 692       reloc.bo = src->bo;
 693       reloc.offset = src_lev->offset +
 694                      blit_info->src.box.z * src_lev->layer_stride;
 695       reloc.flags = ETNA_RELOC_READ;
 696       etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_SURFACE_BASE, &reloc);
 697
 698       etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE, src_lev->clear_value);
 699
 700       source_ts_valid = true;
 701    } else {
 702       etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, 0);
 703    }
 704    ctx->dirty |= ETNA_DIRTY_TS;
 705
 706    /* Kick off RS here */
 707    etna_compile_rs_state(ctx, &copy_to_screen, &(struct rs_state) {
 708       .source_format = translate_rs_format(src_format),
 709       .source_tiling = src->layout,
 710       .source = src->bo,
 711       .source_offset = src_offset,
 712       .source_stride = src_lev->stride,
 713       .source_padded_width = src_lev->padded_width,
 714       .source_padded_height = src_lev->padded_height,
 715       .source_ts_valid = source_ts_valid,
 716       .source_ts_compressed = src_lev->ts_compress_fmt >= 0,
 717       .dest_format = translate_rs_format(dst_format),
 718       .dest_tiling = dst->layout,
 719       .dest = dst->bo,
 720       .dest_offset = dst_offset,
 721       .dest_stride = dst_lev->stride,
 722       .dest_padded_height = dst_lev->padded_height,
 723       .downsample_x = msaa_xscale > 1,
 724       .downsample_y = msaa_yscale > 1,
 725       .swap_rb = translate_rb_src_dst_swap(src->base.format, dst->base.format),
 726       .dither = {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
 727       .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
 728       .width = width,
 729       .height = height,
 730       .tile_count = src_lev->layer_stride / 64
 731    });
 732
 733    etna_submit_rs_state(ctx, &copy_to_screen);
 734    resource_read(ctx, &src->base);
 735    resource_written(ctx, &dst->base);
 736    dst->seqno++;
 737    dst_lev->ts_valid = false;
 738    ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
 739
 740    return true;
 741
 742 manual:
 743    if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) {
 744       if ((src->status & ETNA_PENDING_WRITE) ||
 745           (dst->status & ETNA_PENDING_WRITE))
 746          pctx->flush(pctx, NULL, 0);
 747       return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info);
 748    }
 749
 750    return false;
 751 }
 752
 753 static void
 754 etna_blit_rs(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
 755 {
 756    /* This is a more extended version of resource_copy_region */
 757    /* TODO Some cases can be handled by RS; if not, fall back to rendering or
 758     * even CPU copy block of pixels from info->src to info->dst
 759     * (resource, level, box, format);
 760     * function is used for scaling, flipping in x and y direction (negative
 761     * width/height), format conversion, mask and filter and even a scissor rectangle
 762     *
 763     * What can the RS do for us:
 764     *   convert between tiling formats (layouts)
 765     *   downsample 2x in x and y
 766     *   convert between a limited number of pixel formats
 767     *
 768     * For the rest, fall back to util_blitter
 769     * XXX this goes wrong when source surface is supertiled. */
 770    struct etna_context *ctx = etna_context(pctx);
 771    struct pipe_blit_info info = *blit_info;
 772
 773    if (info.src.resource->nr_samples > 1 &&
 774        info.dst.resource->nr_samples <= 1 &&
 775        !util_format_is_depth_or_stencil(info.src.resource->format) &&
 776        !util_format_is_pure_integer(info.src.resource->format)) {
 777       DBG("color resolve unimplemented");
 778       return;
 779    }
 780
 781    if (etna_try_rs_blit(pctx, blit_info))
 782       return;
 783
 784    if (util_try_blit_via_copy_region(pctx, blit_info))
 785       return;
 786
 787    if (info.mask & PIPE_MASK_S) {
 788       DBG("cannot blit stencil, skipping");
 789       info.mask &= ~PIPE_MASK_S;
 790    }
 791
 792    if (!util_blitter_is_blit_supported(ctx->blitter, &info)) {
 793       DBG("blit unsupported %s -> %s",
 794           util_format_short_name(info.src.resource->format),
 795           util_format_short_name(info.dst.resource->format));
 796       return;
 797    }
 798
 799    etna_blit_save_state(ctx);
 800    util_blitter_blit(ctx->blitter, &info);
 801 }
 802
 803 void
 804 etna_clear_blit_rs_init(struct pipe_context *pctx)
 805 {
 806    DBG("etnaviv: Using RS blit engine");
 807    pctx->clear = etna_clear_rs;
 808    pctx->blit = etna_blit_rs;
 809 }