2 * Copyright (c) 2012-2017 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_rs.h"
29 #include "etnaviv_clear_blit.h"
30 #include "etnaviv_context.h"
31 #include "etnaviv_emit.h"
32 #include "etnaviv_format.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_screen.h"
35 #include "etnaviv_surface.h"
36 #include "etnaviv_tiling.h"
37 #include "etnaviv_translate.h"
38 #include "etnaviv_util.h"
40 #include "pipe/p_defines.h"
41 #include "pipe/p_state.h"
42 #include "util/u_blitter.h"
43 #include "util/u_inlines.h"
44 #include "util/u_memory.h"
45 #include "util/u_surface.h"
47 #include "hw/common.xml.h"
48 #include "hw/state.xml.h"
49 #include "hw/state_3d.xml.h"
54 etna_compile_rs_state(struct etna_context
*ctx
, struct compiled_rs_state
*cs
,
55 const struct rs_state
*rs
)
57 memset(cs
, 0, sizeof(*cs
));
59 /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
60 unsigned source_stride_shift
= COND(rs
->source_tiling
!= ETNA_LAYOUT_LINEAR
, 2);
61 unsigned dest_stride_shift
= COND(rs
->dest_tiling
!= ETNA_LAYOUT_LINEAR
, 2);
63 /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
64 int source_multi
= COND(rs
->source_tiling
& ETNA_LAYOUT_BIT_MULTI
, 1);
65 int dest_multi
= COND(rs
->dest_tiling
& ETNA_LAYOUT_BIT_MULTI
, 1);
67 /* Vivante RS needs widths to be a multiple of 16 or bad things
68 * happen, such as scribbing over memory, or the GPU hanging,
69 * even for non-tiled formats. As this is serious, use abort().
71 if (rs
->width
& ETNA_RS_WIDTH_MASK
)
74 /* TODO could just pre-generate command buffer, would simply submit to one memcpy */
75 cs
->RS_CONFIG
= VIVS_RS_CONFIG_SOURCE_FORMAT(rs
->source_format
) |
76 COND(rs
->downsample_x
, VIVS_RS_CONFIG_DOWNSAMPLE_X
) |
77 COND(rs
->downsample_y
, VIVS_RS_CONFIG_DOWNSAMPLE_Y
) |
78 COND(rs
->source_tiling
& 1, VIVS_RS_CONFIG_SOURCE_TILED
) |
79 VIVS_RS_CONFIG_DEST_FORMAT(rs
->dest_format
) |
80 COND(rs
->dest_tiling
& 1, VIVS_RS_CONFIG_DEST_TILED
) |
81 COND(rs
->swap_rb
, VIVS_RS_CONFIG_SWAP_RB
) |
82 COND(rs
->flip
, VIVS_RS_CONFIG_FLIP
);
84 cs
->RS_SOURCE_STRIDE
= (rs
->source_stride
<< source_stride_shift
) |
85 COND(rs
->source_tiling
& 2, VIVS_RS_SOURCE_STRIDE_TILING
) |
86 COND(source_multi
, VIVS_RS_SOURCE_STRIDE_MULTI
);
88 /* Initially all pipes are set to the base address of the source and
89 * destination buffer respectively. This will be overridden below as
90 * necessary for the multi-pipe, multi-tiled case.
92 for (unsigned pipe
= 0; pipe
< ctx
->specs
.pixel_pipes
; ++pipe
) {
93 cs
->source
[pipe
].bo
= rs
->source
;
94 cs
->source
[pipe
].offset
= rs
->source_offset
;
95 cs
->source
[pipe
].flags
= ETNA_RELOC_READ
;
97 cs
->dest
[pipe
].bo
= rs
->dest
;
98 cs
->dest
[pipe
].offset
= rs
->dest_offset
;
99 cs
->dest
[pipe
].flags
= ETNA_RELOC_WRITE
;
101 cs
->RS_PIPE_OFFSET
[pipe
] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
104 cs
->RS_DEST_STRIDE
= (rs
->dest_stride
<< dest_stride_shift
) |
105 COND(rs
->dest_tiling
& 2, VIVS_RS_DEST_STRIDE_TILING
) |
106 COND(dest_multi
, VIVS_RS_DEST_STRIDE_MULTI
);
108 if (ctx
->specs
.pixel_pipes
== 1 || ctx
->specs
.single_buffer
) {
109 cs
->RS_WINDOW_SIZE
= VIVS_RS_WINDOW_SIZE_WIDTH(rs
->width
) |
110 VIVS_RS_WINDOW_SIZE_HEIGHT(rs
->height
);
111 } else if (ctx
->specs
.pixel_pipes
== 2) {
112 assert((rs
->height
& 7) == 0); /* GPU hangs happen if height not 8-aligned */
115 cs
->source
[1].offset
= rs
->source_offset
+ rs
->source_stride
* rs
->source_padded_height
/ 2;
118 cs
->dest
[1].offset
= rs
->dest_offset
+ rs
->dest_stride
* rs
->dest_padded_height
/ 2;
120 cs
->RS_WINDOW_SIZE
= VIVS_RS_WINDOW_SIZE_WIDTH(rs
->width
) |
121 VIVS_RS_WINDOW_SIZE_HEIGHT(rs
->height
/ 2);
122 cs
->RS_PIPE_OFFSET
[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs
->height
/ 2);
127 cs
->RS_DITHER
[0] = rs
->dither
[0];
128 cs
->RS_DITHER
[1] = rs
->dither
[1];
129 cs
->RS_CLEAR_CONTROL
= VIVS_RS_CLEAR_CONTROL_BITS(rs
->clear_bits
) | rs
->clear_mode
;
130 cs
->RS_FILL_VALUE
[0] = rs
->clear_value
[0];
131 cs
->RS_FILL_VALUE
[1] = rs
->clear_value
[1];
132 cs
->RS_FILL_VALUE
[2] = rs
->clear_value
[2];
133 cs
->RS_FILL_VALUE
[3] = rs
->clear_value
[3];
134 cs
->RS_EXTRA_CONFIG
= VIVS_RS_EXTRA_CONFIG_AA(rs
->aa
) |
135 VIVS_RS_EXTRA_CONFIG_ENDIAN(rs
->endian_mode
);
137 /* If source the same as destination, and the hardware supports this,
138 * do an in-place resolve to fill in unrendered tiles.
140 if (ctx
->specs
.single_buffer
&& rs
->source
== rs
->dest
&&
141 rs
->source_offset
== rs
->dest_offset
&&
142 rs
->source_format
== rs
->dest_format
&&
143 rs
->source_tiling
== rs
->dest_tiling
&&
144 (rs
->source_tiling
& ETNA_LAYOUT_BIT_SUPER
) &&
145 rs
->source_stride
== rs
->dest_stride
&&
146 !rs
->downsample_x
&& !rs
->downsample_y
&&
147 !rs
->swap_rb
&& !rs
->flip
&&
148 !rs
->clear_mode
&& rs
->source_padded_width
) {
149 /* Total number of tiles (same as for autodisable) */
150 cs
->RS_KICKER_INPLACE
= rs
->tile_count
;
152 cs
->source_ts_valid
= rs
->source_ts_valid
;
155 /* modify the clear bits value in the compiled RS state */
157 etna_modify_rs_clearbits(struct compiled_rs_state
*cs
, uint32_t clear_bits
)
159 cs
->RS_CLEAR_CONTROL
&= ~VIVS_RS_CLEAR_CONTROL_BITS__MASK
;
160 cs
->RS_CLEAR_CONTROL
|= VIVS_RS_CLEAR_CONTROL_BITS(clear_bits
);
163 #define EMIT_STATE(state_name, src_value) \
164 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
166 #define EMIT_STATE_FIXP(state_name, src_value) \
167 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
169 #define EMIT_STATE_RELOC(state_name, src_value) \
170 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
172 /* submit RS state, without any processing and no dependence on context
173 * except TS if this is a source-to-destination blit. */
175 etna_submit_rs_state(struct etna_context
*ctx
,
176 const struct compiled_rs_state
*cs
)
178 struct etna_screen
*screen
= etna_screen(ctx
->base
.screen
);
179 struct etna_cmd_stream
*stream
= ctx
->stream
;
180 struct etna_coalesce coalesce
;
182 if (cs
->RS_KICKER_INPLACE
&& !cs
->source_ts_valid
)
183 /* Inplace resolve is no-op if TS is not configured */
186 ctx
->stats
.rs_operations
++;
188 if (cs
->RS_KICKER_INPLACE
) {
189 etna_cmd_stream_reserve(stream
, 6);
190 etna_coalesce_start(stream
, &coalesce
);
191 /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG
, cs
->RS_EXTRA_CONFIG
);
192 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE
, cs
->RS_SOURCE_STRIDE
);
193 /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE
, cs
->RS_KICKER_INPLACE
);
194 etna_coalesce_end(stream
, &coalesce
);
195 } else if (screen
->specs
.pixel_pipes
== 1) {
196 etna_cmd_stream_reserve(stream
, 22);
197 etna_coalesce_start(stream
, &coalesce
);
198 /* 0/1 */ EMIT_STATE(RS_CONFIG
, cs
->RS_CONFIG
);
199 /* 2 */ EMIT_STATE_RELOC(RS_SOURCE_ADDR
, &cs
->source
[0]);
200 /* 3 */ EMIT_STATE(RS_SOURCE_STRIDE
, cs
->RS_SOURCE_STRIDE
);
201 /* 4 */ EMIT_STATE_RELOC(RS_DEST_ADDR
, &cs
->dest
[0]);
202 /* 5 */ EMIT_STATE(RS_DEST_STRIDE
, cs
->RS_DEST_STRIDE
);
203 /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE
, cs
->RS_WINDOW_SIZE
);
204 /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs
->RS_DITHER
[0]);
205 /*10 */ EMIT_STATE(RS_DITHER(1), cs
->RS_DITHER
[1]);
207 /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL
, cs
->RS_CLEAR_CONTROL
);
208 /*14 */ EMIT_STATE(RS_FILL_VALUE(0), cs
->RS_FILL_VALUE
[0]);
209 /*15 */ EMIT_STATE(RS_FILL_VALUE(1), cs
->RS_FILL_VALUE
[1]);
210 /*16 */ EMIT_STATE(RS_FILL_VALUE(2), cs
->RS_FILL_VALUE
[2]);
211 /*17 */ EMIT_STATE(RS_FILL_VALUE(3), cs
->RS_FILL_VALUE
[3]);
212 /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG
, cs
->RS_EXTRA_CONFIG
);
213 /*20/21*/ EMIT_STATE(RS_KICKER
, 0xbeebbeeb);
214 etna_coalesce_end(stream
, &coalesce
);
215 } else if (screen
->specs
.pixel_pipes
== 2) {
216 etna_cmd_stream_reserve(stream
, 34); /* worst case - both pipes multi=1 */
217 etna_coalesce_start(stream
, &coalesce
);
218 /* 0/1 */ EMIT_STATE(RS_CONFIG
, cs
->RS_CONFIG
);
219 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE
, cs
->RS_SOURCE_STRIDE
);
220 /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE
, cs
->RS_DEST_STRIDE
);
221 /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs
->source
[0]);
222 if (cs
->RS_SOURCE_STRIDE
& VIVS_RS_SOURCE_STRIDE_MULTI
) {
223 /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs
->source
[1]);
226 /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs
->dest
[0]);
227 if (cs
->RS_DEST_STRIDE
& VIVS_RS_DEST_STRIDE_MULTI
) {
228 /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs
->dest
[1]);
231 /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs
->RS_PIPE_OFFSET
[0]);
232 /*16 */ EMIT_STATE(RS_PIPE_OFFSET(1), cs
->RS_PIPE_OFFSET
[1]);
234 /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE
, cs
->RS_WINDOW_SIZE
);
235 /*20/21*/ EMIT_STATE(RS_DITHER(0), cs
->RS_DITHER
[0]);
236 /*22 */ EMIT_STATE(RS_DITHER(1), cs
->RS_DITHER
[1]);
238 /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL
, cs
->RS_CLEAR_CONTROL
);
239 /*26 */ EMIT_STATE(RS_FILL_VALUE(0), cs
->RS_FILL_VALUE
[0]);
240 /*27 */ EMIT_STATE(RS_FILL_VALUE(1), cs
->RS_FILL_VALUE
[1]);
241 /*28 */ EMIT_STATE(RS_FILL_VALUE(2), cs
->RS_FILL_VALUE
[2]);
242 /*29 */ EMIT_STATE(RS_FILL_VALUE(3), cs
->RS_FILL_VALUE
[3]);
243 /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG
, cs
->RS_EXTRA_CONFIG
);
244 /*32/33*/ EMIT_STATE(RS_KICKER
, 0xbeebbeeb);
245 etna_coalesce_end(stream
, &coalesce
);
251 /* Generate clear command for a surface (non-fast clear case) */
253 etna_rs_gen_clear_surface(struct etna_context
*ctx
, struct etna_surface
*surf
,
254 uint32_t clear_value
)
256 struct etna_resource
*dst
= etna_resource(surf
->base
.texture
);
257 uint32_t format
= translate_rs_format(surf
->base
.format
);
259 if (format
== ETNA_NO_MATCH
) {
260 BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", util_format_name(surf
->base
.format
));
261 format
= RS_FORMAT_A8R8G8B8
;
265 /* use tiled clear if width is multiple of 16 */
266 bool tiled_clear
= (surf
->surf
.padded_width
& ETNA_RS_WIDTH_MASK
) == 0 &&
267 (surf
->surf
.padded_height
& ETNA_RS_HEIGHT_MASK
) == 0;
269 etna_compile_rs_state( ctx
, &surf
->clear_command
, &(struct rs_state
) {
270 .source_format
= format
,
271 .dest_format
= format
,
273 .dest_offset
= surf
->surf
.offset
,
274 .dest_stride
= surf
->surf
.stride
,
275 .dest_padded_height
= surf
->surf
.padded_height
,
276 .dest_tiling
= tiled_clear
? dst
->layout
: ETNA_LAYOUT_LINEAR
,
277 .dither
= {0xffffffff, 0xffffffff},
278 .width
= surf
->surf
.padded_width
, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
279 .height
= surf
->surf
.padded_height
,
280 .clear_value
= {clear_value
},
281 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1
,
287 etna_blit_clear_color_rs(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
288 const union pipe_color_union
*color
)
290 struct etna_context
*ctx
= etna_context(pctx
);
291 struct etna_surface
*surf
= etna_surface(dst
);
292 uint32_t new_clear_value
= etna_clear_blit_pack_rgba(surf
->base
.format
, color
->f
);
294 if (surf
->surf
.ts_size
) { /* TS: use precompiled clear command */
295 ctx
->framebuffer
.TS_COLOR_CLEAR_VALUE
= new_clear_value
;
297 if (VIV_FEATURE(ctx
->screen
, chipMinorFeatures1
, AUTO_DISABLE
)) {
298 /* Set number of color tiles to be filled */
299 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_AUTO_DISABLE_COUNT
,
300 surf
->surf
.padded_width
* surf
->surf
.padded_height
/ 16);
301 ctx
->framebuffer
.TS_MEM_CONFIG
|= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE
;
304 surf
->level
->ts_valid
= true;
305 ctx
->dirty
|= ETNA_DIRTY_TS
| ETNA_DIRTY_DERIVE_TS
;
306 } else if (unlikely(new_clear_value
!= surf
->level
->clear_value
)) { /* Queue normal RS clear for non-TS surfaces */
307 /* If clear color changed, re-generate stored command */
308 etna_rs_gen_clear_surface(ctx
, surf
, new_clear_value
);
311 etna_submit_rs_state(ctx
, &surf
->clear_command
);
313 surf
->level
->clear_value
= new_clear_value
;
314 resource_written(ctx
, surf
->base
.texture
);
315 etna_resource(surf
->base
.texture
)->seqno
++;
319 etna_blit_clear_zs_rs(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
320 unsigned buffers
, double depth
, unsigned stencil
)
322 struct etna_context
*ctx
= etna_context(pctx
);
323 struct etna_surface
*surf
= etna_surface(dst
);
324 uint32_t new_clear_value
= translate_clear_depth_stencil(surf
->base
.format
, depth
, stencil
);
325 uint32_t new_clear_bits
= 0, clear_bits_depth
, clear_bits_stencil
;
327 /* Get the channels to clear */
328 switch (surf
->base
.format
) {
329 case PIPE_FORMAT_Z16_UNORM
:
330 clear_bits_depth
= 0xffff;
331 clear_bits_stencil
= 0;
333 case PIPE_FORMAT_X8Z24_UNORM
:
334 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
335 clear_bits_depth
= 0xeeee;
336 clear_bits_stencil
= 0x1111;
339 clear_bits_depth
= clear_bits_stencil
= 0xffff;
343 if (buffers
& PIPE_CLEAR_DEPTH
)
344 new_clear_bits
|= clear_bits_depth
;
345 if (buffers
& PIPE_CLEAR_STENCIL
)
346 new_clear_bits
|= clear_bits_stencil
;
347 /* FIXME: when tile status is enabled, this becomes more complex as
348 * we may separately clear the depth from the stencil. In this case,
349 * we want to resolve the surface, and avoid using the tile status.
350 * We may be better off recording the pending clear operation,
351 * delaying the actual clear to the first use. This way, we can merge
352 * consecutive clears together. */
353 if (surf
->surf
.ts_size
) { /* TS: use precompiled clear command */
354 /* Set new clear depth value */
355 ctx
->framebuffer
.TS_DEPTH_CLEAR_VALUE
= new_clear_value
;
356 if (VIV_FEATURE(ctx
->screen
, chipMinorFeatures1
, AUTO_DISABLE
)) {
357 /* Set number of depth tiles to be filled */
358 etna_set_state(ctx
->stream
, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT
,
359 surf
->surf
.padded_width
* surf
->surf
.padded_height
/ 16);
360 ctx
->framebuffer
.TS_MEM_CONFIG
|= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE
;
363 surf
->level
->ts_valid
= true;
364 ctx
->dirty
|= ETNA_DIRTY_TS
| ETNA_DIRTY_DERIVE_TS
;
366 if (unlikely(new_clear_value
!= surf
->level
->clear_value
)) { /* Queue normal RS clear for non-TS surfaces */
367 /* If clear depth value changed, re-generate stored command */
368 etna_rs_gen_clear_surface(ctx
, surf
, new_clear_value
);
370 /* Update the channels to be cleared */
371 etna_modify_rs_clearbits(&surf
->clear_command
, new_clear_bits
);
374 etna_submit_rs_state(ctx
, &surf
->clear_command
);
376 surf
->level
->clear_value
= new_clear_value
;
377 resource_written(ctx
, surf
->base
.texture
);
378 etna_resource(surf
->base
.texture
)->seqno
++;
382 etna_clear_rs(struct pipe_context
*pctx
, unsigned buffers
,
383 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
385 struct etna_context
*ctx
= etna_context(pctx
);
387 /* Flush color and depth cache before clearing anything.
388 * This is especially important when coming from another surface, as
389 * otherwise it may clear part of the old surface instead. */
390 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
391 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
393 /* Preparation: Flush the TS if needed. This must be done after flushing
394 * color and depth, otherwise it can result in crashes */
395 bool need_ts_flush
= false;
396 if ((buffers
& PIPE_CLEAR_COLOR
) && ctx
->framebuffer_s
.nr_cbufs
) {
397 struct etna_surface
*surf
= etna_surface(ctx
->framebuffer_s
.cbufs
[0]);
398 if (surf
->surf
.ts_size
)
399 need_ts_flush
= true;
401 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
) {
402 struct etna_surface
*surf
= etna_surface(ctx
->framebuffer_s
.zsbuf
);
404 if (surf
->surf
.ts_size
)
405 need_ts_flush
= true;
409 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, VIVS_TS_FLUSH_CACHE_FLUSH
);
411 /* No need to set up the TS here as RS clear operations (in contrast to
412 * resolve and copy) do not require the TS state.
414 if (buffers
& PIPE_CLEAR_COLOR
) {
415 for (int idx
= 0; idx
< ctx
->framebuffer_s
.nr_cbufs
; ++idx
) {
416 etna_blit_clear_color_rs(pctx
, ctx
->framebuffer_s
.cbufs
[idx
],
421 /* Flush the color and depth caches before each RS clear operation
422 * This fixes a hang on GC600. */
423 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
&& buffers
& PIPE_CLEAR_COLOR
)
424 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
,
425 VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
427 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
)
428 etna_blit_clear_zs_rs(pctx
, ctx
->framebuffer_s
.zsbuf
, buffers
, depth
, stencil
);
430 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
434 etna_manual_blit(struct etna_resource
*dst
, struct etna_resource_level
*dst_lev
,
435 unsigned int dst_offset
, struct etna_resource
*src
,
436 struct etna_resource_level
*src_lev
, unsigned int src_offset
,
437 const struct pipe_blit_info
*blit_info
)
439 void *smap
, *srow
, *dmap
, *drow
;
442 assert(src
->layout
== ETNA_LAYOUT_TILED
);
443 assert(dst
->layout
== ETNA_LAYOUT_TILED
);
444 assert(src
->base
.nr_samples
== 0);
445 assert(dst
->base
.nr_samples
== 0);
447 tile_size
= util_format_get_blocksize(blit_info
->src
.format
) * 4 * 4;
449 smap
= etna_bo_map(src
->bo
);
453 dmap
= etna_bo_map(dst
->bo
);
457 srow
= smap
+ src_offset
;
458 drow
= dmap
+ dst_offset
;
460 etna_bo_cpu_prep(src
->bo
, DRM_ETNA_PREP_READ
);
461 etna_bo_cpu_prep(dst
->bo
, DRM_ETNA_PREP_WRITE
);
463 for (int y
= 0; y
< blit_info
->src
.box
.height
; y
+= 4) {
464 memcpy(drow
, srow
, tile_size
* blit_info
->src
.box
.width
);
465 srow
+= src_lev
->stride
* 4;
466 drow
+= dst_lev
->stride
* 4;
469 etna_bo_cpu_fini(dst
->bo
);
470 etna_bo_cpu_fini(src
->bo
);
476 etna_compute_tileoffset(const struct pipe_box
*box
, enum pipe_format format
,
477 size_t stride
, enum etna_surface_layout layout
)
480 unsigned int x
= box
->x
, y
= box
->y
;
481 unsigned int blocksize
= util_format_get_blocksize(format
);
484 case ETNA_LAYOUT_LINEAR
:
485 offset
= y
* stride
+ x
* blocksize
;
487 case ETNA_LAYOUT_MULTI_TILED
:
490 case ETNA_LAYOUT_TILED
:
491 assert(!(x
& 0x03) && !(y
& 0x03));
492 offset
= (y
& ~0x03) * stride
+ blocksize
* ((x
& ~0x03) << 2);
494 case ETNA_LAYOUT_MULTI_SUPERTILED
:
497 case ETNA_LAYOUT_SUPER_TILED
:
498 assert(!(x
& 0x3f) && !(y
& 0x3f));
499 offset
= (y
& ~0x3f) * stride
+ blocksize
* ((x
& ~0x3f) << 6);
502 unreachable("invalid resource layout");
509 etna_get_rs_alignment_mask(const struct etna_context
*ctx
,
510 const enum etna_surface_layout layout
,
511 unsigned int *width_mask
, unsigned int *height_mask
)
513 unsigned int h_align
, w_align
;
515 if (layout
& ETNA_LAYOUT_BIT_SUPER
) {
516 w_align
= h_align
= 64;
518 w_align
= ETNA_RS_WIDTH_MASK
+ 1;
519 h_align
= ETNA_RS_HEIGHT_MASK
+ 1;
522 h_align
*= ctx
->screen
->specs
.pixel_pipes
;
524 *width_mask
= w_align
- 1;
525 *height_mask
= h_align
-1;
529 etna_try_rs_blit(struct pipe_context
*pctx
,
530 const struct pipe_blit_info
*blit_info
)
532 struct etna_context
*ctx
= etna_context(pctx
);
533 struct etna_resource
*src
= etna_resource(blit_info
->src
.resource
);
534 struct etna_resource
*dst
= etna_resource(blit_info
->dst
.resource
);
535 struct compiled_rs_state copy_to_screen
;
536 uint32_t ts_mem_config
= 0;
537 int msaa_xscale
= 1, msaa_yscale
= 1;
539 /* Ensure that the level is valid */
540 assert(blit_info
->src
.level
<= src
->base
.last_level
);
541 assert(blit_info
->dst
.level
<= dst
->base
.last_level
);
543 if (!translate_samples_to_xyscale(src
->base
.nr_samples
, &msaa_xscale
, &msaa_yscale
, NULL
))
546 /* The width/height are in pixels; they do not change as a result of
547 * multi-sampling. So, when blitting from a 4x multisampled surface
548 * to a non-multisampled surface, the width and height will be
549 * identical. As we do not support scaling, reject different sizes. */
550 if (blit_info
->dst
.box
.width
!= blit_info
->src
.box
.width
||
551 blit_info
->dst
.box
.height
!= blit_info
->src
.box
.height
) {
552 DBG("scaling requested: source %dx%d destination %dx%d",
553 blit_info
->src
.box
.width
, blit_info
->src
.box
.height
,
554 blit_info
->dst
.box
.width
, blit_info
->dst
.box
.height
);
558 /* No masks - RS can't copy specific channels */
559 unsigned mask
= util_format_get_mask(blit_info
->dst
.format
);
560 if ((blit_info
->mask
& mask
) != mask
) {
561 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info
->mask
, mask
);
565 unsigned src_format
= etna_compatible_rs_format(blit_info
->src
.format
);
566 unsigned dst_format
= etna_compatible_rs_format(blit_info
->dst
.format
);
567 if (translate_rs_format(src_format
) == ETNA_NO_MATCH
||
568 translate_rs_format(dst_format
) == ETNA_NO_MATCH
||
569 blit_info
->scissor_enable
||
570 blit_info
->dst
.box
.depth
!= blit_info
->src
.box
.depth
||
571 blit_info
->dst
.box
.depth
!= 1) {
575 unsigned w_mask
, h_mask
;
577 etna_get_rs_alignment_mask(ctx
, src
->layout
, &w_mask
, &h_mask
);
578 if ((blit_info
->src
.box
.x
& w_mask
) || (blit_info
->src
.box
.y
& h_mask
))
581 etna_get_rs_alignment_mask(ctx
, dst
->layout
, &w_mask
, &h_mask
);
582 if ((blit_info
->dst
.box
.x
& w_mask
) || (blit_info
->dst
.box
.y
& h_mask
))
585 /* Ensure that the Z coordinate is sane */
586 if (dst
->base
.target
!= PIPE_TEXTURE_CUBE
)
587 assert(blit_info
->dst
.box
.z
== 0);
588 if (src
->base
.target
!= PIPE_TEXTURE_CUBE
)
589 assert(blit_info
->src
.box
.z
== 0);
591 assert(blit_info
->src
.box
.z
< src
->base
.array_size
);
592 assert(blit_info
->dst
.box
.z
< dst
->base
.array_size
);
594 struct etna_resource_level
*src_lev
= &src
->levels
[blit_info
->src
.level
];
595 struct etna_resource_level
*dst_lev
= &dst
->levels
[blit_info
->dst
.level
];
597 /* we may be given coordinates up to the padded width to avoid
598 * any alignment issues with different tiling formats */
599 assert((blit_info
->src
.box
.x
+ blit_info
->src
.box
.width
) * msaa_xscale
<= src_lev
->padded_width
);
600 assert((blit_info
->src
.box
.y
+ blit_info
->src
.box
.height
) * msaa_yscale
<= src_lev
->padded_height
);
601 assert(blit_info
->dst
.box
.x
+ blit_info
->dst
.box
.width
<= dst_lev
->padded_width
);
602 assert(blit_info
->dst
.box
.y
+ blit_info
->dst
.box
.height
<= dst_lev
->padded_height
);
604 unsigned src_offset
= src_lev
->offset
+
605 blit_info
->src
.box
.z
* src_lev
->layer_stride
+
606 etna_compute_tileoffset(&blit_info
->src
.box
,
607 blit_info
->src
.format
,
610 unsigned dst_offset
= dst_lev
->offset
+
611 blit_info
->dst
.box
.z
* dst_lev
->layer_stride
+
612 etna_compute_tileoffset(&blit_info
->dst
.box
,
613 blit_info
->dst
.format
,
617 if (src_lev
->padded_width
<= ETNA_RS_WIDTH_MASK
||
618 dst_lev
->padded_width
<= ETNA_RS_WIDTH_MASK
||
619 src_lev
->padded_height
<= ETNA_RS_HEIGHT_MASK
||
620 dst_lev
->padded_height
<= ETNA_RS_HEIGHT_MASK
)
623 /* If the width is not aligned to the RS width, but is within our
624 * padding, adjust the width to suite the RS width restriction.
625 * Note: the RS width/height are converted to source samples here. */
626 unsigned int width
= blit_info
->src
.box
.width
* msaa_xscale
;
627 unsigned int height
= blit_info
->src
.box
.height
* msaa_yscale
;
628 unsigned int w_align
= ETNA_RS_WIDTH_MASK
+ 1;
629 unsigned int h_align
= (ETNA_RS_HEIGHT_MASK
+ 1) * ctx
->specs
.pixel_pipes
;
631 if (width
& (w_align
- 1) && width
>= src_lev
->width
* msaa_xscale
&& width
>= dst_lev
->width
)
632 width
= align(width
, w_align
);
634 if (height
& (h_align
- 1) && height
>= src_lev
->height
* msaa_yscale
&& height
>= dst_lev
->height
)
635 height
= align(height
, h_align
);
637 /* The padded dimensions are in samples */
638 if (width
> src_lev
->padded_width
||
639 width
> dst_lev
->padded_width
* msaa_xscale
||
640 height
> src_lev
->padded_height
||
641 height
> dst_lev
->padded_height
* msaa_yscale
||
642 width
& (w_align
- 1) || height
& (h_align
- 1))
645 if (src
->base
.nr_samples
> 1) {
646 uint32_t msaa_format
= translate_msaa_format(src_format
);
647 assert(msaa_format
!= ETNA_NO_MATCH
);
648 ts_mem_config
|= VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION
| msaa_format
;
651 /* Always flush color and depth cache together before resolving. This works
652 * around artifacts that appear in some cases when scanning out a texture
653 * directly after it has been rendered to, such as rendering an animated web
654 * page in a QtWebEngine based WebView on GC2000. The artifacts look like
655 * the texture sampler samples zeroes instead of texture data in a small,
656 * irregular triangle in the lower right of each browser tile quad. Other
657 * attempts to avoid these artifacts, including a pipeline stall before the
658 * color flush or a TS cache flush afterwards, or flushing multiple times,
659 * with stalls before and after each flush, have shown no effect. */
660 if (src
->base
.bind
& PIPE_BIND_RENDER_TARGET
||
661 src
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
) {
662 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
,
663 VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
664 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
666 if (src
->levels
[blit_info
->src
.level
].ts_size
&&
667 src
->levels
[blit_info
->src
.level
].ts_valid
)
668 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, VIVS_TS_FLUSH_CACHE_FLUSH
);
671 /* Set up color TS to source surface before blit, if needed */
672 bool source_ts_valid
= false;
673 if (src
->levels
[blit_info
->src
.level
].ts_size
&&
674 src
->levels
[blit_info
->src
.level
].ts_valid
) {
675 struct etna_reloc reloc
;
677 src_lev
->ts_offset
+ blit_info
->src
.box
.z
* src_lev
->ts_layer_stride
;
679 etna_set_state(ctx
->stream
, VIVS_TS_MEM_CONFIG
,
680 VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
| ts_mem_config
);
682 memset(&reloc
, 0, sizeof(struct etna_reloc
));
683 reloc
.bo
= src
->ts_bo
;
684 reloc
.offset
= ts_offset
;
685 reloc
.flags
= ETNA_RELOC_READ
;
686 etna_set_state_reloc(ctx
->stream
, VIVS_TS_COLOR_STATUS_BASE
, &reloc
);
688 memset(&reloc
, 0, sizeof(struct etna_reloc
));
690 reloc
.offset
= src_lev
->offset
+
691 blit_info
->src
.box
.z
* src_lev
->layer_stride
;
692 reloc
.flags
= ETNA_RELOC_READ
;
693 etna_set_state_reloc(ctx
->stream
, VIVS_TS_COLOR_SURFACE_BASE
, &reloc
);
695 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_CLEAR_VALUE
,
696 src
->levels
[blit_info
->src
.level
].clear_value
);
698 source_ts_valid
= true;
700 etna_set_state(ctx
->stream
, VIVS_TS_MEM_CONFIG
, ts_mem_config
);
702 ctx
->dirty
|= ETNA_DIRTY_TS
;
704 /* Kick off RS here */
705 etna_compile_rs_state(ctx
, ©_to_screen
, &(struct rs_state
) {
706 .source_format
= translate_rs_format(src_format
),
707 .source_tiling
= src
->layout
,
709 .source_offset
= src_offset
,
710 .source_stride
= src_lev
->stride
,
711 .source_padded_width
= src_lev
->padded_width
,
712 .source_padded_height
= src_lev
->padded_height
,
713 .source_ts_valid
= source_ts_valid
,
714 .dest_format
= translate_rs_format(dst_format
),
715 .dest_tiling
= dst
->layout
,
717 .dest_offset
= dst_offset
,
718 .dest_stride
= dst_lev
->stride
,
719 .dest_padded_height
= dst_lev
->padded_height
,
720 .downsample_x
= msaa_xscale
> 1,
721 .downsample_y
= msaa_yscale
> 1,
722 .swap_rb
= translate_rb_src_dst_swap(src
->base
.format
, dst
->base
.format
),
723 .dither
= {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
724 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_DISABLED
,
727 .tile_count
= src_lev
->layer_stride
/ 64
730 etna_submit_rs_state(ctx
, ©_to_screen
);
731 resource_read(ctx
, &src
->base
);
732 resource_written(ctx
, &dst
->base
);
734 dst
->levels
[blit_info
->dst
.level
].ts_valid
= false;
735 ctx
->dirty
|= ETNA_DIRTY_DERIVE_TS
;
740 if (src
->layout
== ETNA_LAYOUT_TILED
&& dst
->layout
== ETNA_LAYOUT_TILED
) {
741 if ((src
->status
& ETNA_PENDING_WRITE
) ||
742 (dst
->status
& ETNA_PENDING_WRITE
))
743 pctx
->flush(pctx
, NULL
, 0);
744 return etna_manual_blit(dst
, dst_lev
, dst_offset
, src
, src_lev
, src_offset
, blit_info
);
751 etna_blit_rs(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
753 /* This is a more extended version of resource_copy_region */
754 /* TODO Some cases can be handled by RS; if not, fall back to rendering or
755 * even CPU copy block of pixels from info->src to info->dst
756 * (resource, level, box, format);
757 * function is used for scaling, flipping in x and y direction (negative
758 * width/height), format conversion, mask and filter and even a scissor rectangle
760 * What can the RS do for us:
761 * convert between tiling formats (layouts)
762 * downsample 2x in x and y
763 * convert between a limited number of pixel formats
765 * For the rest, fall back to util_blitter
766 * XXX this goes wrong when source surface is supertiled. */
767 struct etna_context
*ctx
= etna_context(pctx
);
768 struct pipe_blit_info info
= *blit_info
;
770 if (info
.src
.resource
->nr_samples
> 1 &&
771 info
.dst
.resource
->nr_samples
<= 1 &&
772 !util_format_is_depth_or_stencil(info
.src
.resource
->format
) &&
773 !util_format_is_pure_integer(info
.src
.resource
->format
)) {
774 DBG("color resolve unimplemented");
778 if (etna_try_rs_blit(pctx
, blit_info
))
781 if (util_try_blit_via_copy_region(pctx
, blit_info
))
784 if (info
.mask
& PIPE_MASK_S
) {
785 DBG("cannot blit stencil, skipping");
786 info
.mask
&= ~PIPE_MASK_S
;
789 if (!util_blitter_is_blit_supported(ctx
->blitter
, &info
)) {
790 DBG("blit unsupported %s -> %s",
791 util_format_short_name(info
.src
.resource
->format
),
792 util_format_short_name(info
.dst
.resource
->format
));
796 etna_blit_save_state(ctx
);
797 util_blitter_blit(ctx
->blitter
, &info
);
801 etna_clear_blit_rs_init(struct pipe_context
*pctx
)
803 DBG("etnaviv: Using RS blit engine");
804 pctx
->clear
= etna_clear_rs
;
805 pctx
->blit
= etna_blit_rs
;