2 * Copyright (c) 2012-2017 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_rs.h"
29 #include "etnaviv_clear_blit.h"
30 #include "etnaviv_context.h"
31 #include "etnaviv_emit.h"
32 #include "etnaviv_format.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_screen.h"
35 #include "etnaviv_surface.h"
36 #include "etnaviv_tiling.h"
37 #include "etnaviv_translate.h"
38 #include "etnaviv_util.h"
40 #include "pipe/p_defines.h"
41 #include "pipe/p_state.h"
42 #include "util/u_blitter.h"
43 #include "util/u_inlines.h"
44 #include "util/u_memory.h"
45 #include "util/u_surface.h"
47 #include "hw/common.xml.h"
48 #include "hw/state.xml.h"
49 #include "hw/state_3d.xml.h"
53 /* return a RS "compatible" format for use when copying */
55 etna_compatible_rs_format(enum pipe_format fmt
)
57 /* YUYV and UYVY are blocksize 4, but 2 bytes per pixel */
58 if (fmt
== PIPE_FORMAT_YUYV
|| fmt
== PIPE_FORMAT_UYVY
)
59 return RS_FORMAT_A4R4G4B4
;
61 switch (util_format_get_blocksize(fmt
)) {
62 case 2: return RS_FORMAT_A4R4G4B4
;
63 case 4: return RS_FORMAT_A8R8G8B8
;
64 default: return ETNA_NO_MATCH
;
69 etna_compile_rs_state(struct etna_context
*ctx
, struct compiled_rs_state
*cs
,
70 const struct rs_state
*rs
)
72 memset(cs
, 0, sizeof(*cs
));
74 /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
75 unsigned source_stride_shift
= COND(rs
->source_tiling
!= ETNA_LAYOUT_LINEAR
, 2);
76 unsigned dest_stride_shift
= COND(rs
->dest_tiling
!= ETNA_LAYOUT_LINEAR
, 2);
78 /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
79 int source_multi
= COND(rs
->source_tiling
& ETNA_LAYOUT_BIT_MULTI
, 1);
80 int dest_multi
= COND(rs
->dest_tiling
& ETNA_LAYOUT_BIT_MULTI
, 1);
82 /* Vivante RS needs widths to be a multiple of 16 or bad things
83 * happen, such as scribbing over memory, or the GPU hanging,
84 * even for non-tiled formats. As this is serious, use abort().
86 if (rs
->width
& ETNA_RS_WIDTH_MASK
)
89 /* TODO could just pre-generate command buffer, would simply submit to one memcpy */
90 cs
->RS_CONFIG
= VIVS_RS_CONFIG_SOURCE_FORMAT(rs
->source_format
) |
91 COND(rs
->downsample_x
, VIVS_RS_CONFIG_DOWNSAMPLE_X
) |
92 COND(rs
->downsample_y
, VIVS_RS_CONFIG_DOWNSAMPLE_Y
) |
93 COND(rs
->source_tiling
& 1, VIVS_RS_CONFIG_SOURCE_TILED
) |
94 VIVS_RS_CONFIG_DEST_FORMAT(rs
->dest_format
) |
95 COND(rs
->dest_tiling
& 1, VIVS_RS_CONFIG_DEST_TILED
) |
96 COND(rs
->swap_rb
, VIVS_RS_CONFIG_SWAP_RB
) |
97 COND(rs
->flip
, VIVS_RS_CONFIG_FLIP
);
99 cs
->RS_SOURCE_STRIDE
= (rs
->source_stride
<< source_stride_shift
) |
100 COND(rs
->source_tiling
& 2, VIVS_RS_SOURCE_STRIDE_TILING
) |
101 COND(source_multi
, VIVS_RS_SOURCE_STRIDE_MULTI
);
103 /* Initially all pipes are set to the base address of the source and
104 * destination buffer respectively. This will be overridden below as
105 * necessary for the multi-pipe, multi-tiled case.
107 for (unsigned pipe
= 0; pipe
< ctx
->specs
.pixel_pipes
; ++pipe
) {
108 cs
->source
[pipe
].bo
= rs
->source
;
109 cs
->source
[pipe
].offset
= rs
->source_offset
;
110 cs
->source
[pipe
].flags
= ETNA_RELOC_READ
;
112 cs
->dest
[pipe
].bo
= rs
->dest
;
113 cs
->dest
[pipe
].offset
= rs
->dest_offset
;
114 cs
->dest
[pipe
].flags
= ETNA_RELOC_WRITE
;
116 cs
->RS_PIPE_OFFSET
[pipe
] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
119 cs
->RS_DEST_STRIDE
= (rs
->dest_stride
<< dest_stride_shift
) |
120 COND(rs
->dest_tiling
& 2, VIVS_RS_DEST_STRIDE_TILING
) |
121 COND(dest_multi
, VIVS_RS_DEST_STRIDE_MULTI
);
125 cs
->source
[1].offset
= rs
->source_offset
+ rs
->source_stride
* rs
->source_padded_height
/ 2;
128 cs
->dest
[1].offset
= rs
->dest_offset
+ rs
->dest_stride
* rs
->dest_padded_height
/ 2;
130 cs
->RS_WINDOW_SIZE
= VIVS_RS_WINDOW_SIZE_WIDTH(rs
->width
) |
131 VIVS_RS_WINDOW_SIZE_HEIGHT(rs
->height
);
133 /* use dual pipe mode when required */
134 if (!ctx
->specs
.single_buffer
&& ctx
->specs
.pixel_pipes
== 2 && !(rs
->height
& 7)) {
135 cs
->RS_WINDOW_SIZE
= VIVS_RS_WINDOW_SIZE_WIDTH(rs
->width
) |
136 VIVS_RS_WINDOW_SIZE_HEIGHT(rs
->height
/ 2);
137 cs
->RS_PIPE_OFFSET
[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs
->height
/ 2);
140 cs
->RS_DITHER
[0] = rs
->dither
[0];
141 cs
->RS_DITHER
[1] = rs
->dither
[1];
142 cs
->RS_CLEAR_CONTROL
= VIVS_RS_CLEAR_CONTROL_BITS(rs
->clear_bits
) | rs
->clear_mode
;
143 cs
->RS_FILL_VALUE
[0] = rs
->clear_value
[0];
144 cs
->RS_FILL_VALUE
[1] = rs
->clear_value
[1];
145 cs
->RS_FILL_VALUE
[2] = rs
->clear_value
[2];
146 cs
->RS_FILL_VALUE
[3] = rs
->clear_value
[3];
147 cs
->RS_EXTRA_CONFIG
= VIVS_RS_EXTRA_CONFIG_AA(rs
->aa
) |
148 VIVS_RS_EXTRA_CONFIG_ENDIAN(rs
->endian_mode
);
150 /* If source the same as destination, and the hardware supports this,
151 * do an in-place resolve to fill in unrendered tiles.
153 if (ctx
->specs
.single_buffer
&& rs
->source
== rs
->dest
&&
154 rs
->source_offset
== rs
->dest_offset
&&
155 rs
->source_format
== rs
->dest_format
&&
156 rs
->source_tiling
== rs
->dest_tiling
&&
157 (rs
->source_tiling
& ETNA_LAYOUT_BIT_SUPER
) &&
158 rs
->source_stride
== rs
->dest_stride
&&
159 !rs
->downsample_x
&& !rs
->downsample_y
&&
160 !rs
->swap_rb
&& !rs
->flip
&&
161 !rs
->clear_mode
&& rs
->source_padded_width
&&
162 !rs
->source_ts_compressed
) {
163 /* Total number of tiles (same as for autodisable) */
164 cs
->RS_KICKER_INPLACE
= rs
->tile_count
;
166 cs
->source_ts_valid
= rs
->source_ts_valid
;
169 /* modify the clear bits value in the compiled RS state */
171 etna_modify_rs_clearbits(struct compiled_rs_state
*cs
, uint32_t clear_bits
)
173 cs
->RS_CLEAR_CONTROL
&= ~VIVS_RS_CLEAR_CONTROL_BITS__MASK
;
174 cs
->RS_CLEAR_CONTROL
|= VIVS_RS_CLEAR_CONTROL_BITS(clear_bits
);
177 #define EMIT_STATE(state_name, src_value) \
178 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
180 #define EMIT_STATE_FIXP(state_name, src_value) \
181 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
183 #define EMIT_STATE_RELOC(state_name, src_value) \
184 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
186 /* submit RS state, without any processing and no dependence on context
187 * except TS if this is a source-to-destination blit. */
189 etna_submit_rs_state(struct etna_context
*ctx
,
190 const struct compiled_rs_state
*cs
)
192 struct etna_screen
*screen
= etna_screen(ctx
->base
.screen
);
193 struct etna_cmd_stream
*stream
= ctx
->stream
;
194 struct etna_coalesce coalesce
;
196 if (cs
->RS_KICKER_INPLACE
&& !cs
->source_ts_valid
)
197 /* Inplace resolve is no-op if TS is not configured */
200 ctx
->stats
.rs_operations
++;
202 if (cs
->RS_KICKER_INPLACE
) {
203 etna_cmd_stream_reserve(stream
, 6);
204 etna_coalesce_start(stream
, &coalesce
);
205 /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG
, cs
->RS_EXTRA_CONFIG
);
206 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE
, cs
->RS_SOURCE_STRIDE
);
207 /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE
, cs
->RS_KICKER_INPLACE
);
208 etna_coalesce_end(stream
, &coalesce
);
209 } else if (screen
->specs
.pixel_pipes
== 1) {
210 etna_cmd_stream_reserve(stream
, 22);
211 etna_coalesce_start(stream
, &coalesce
);
212 /* 0/1 */ EMIT_STATE(RS_CONFIG
, cs
->RS_CONFIG
);
213 /* 2 */ EMIT_STATE_RELOC(RS_SOURCE_ADDR
, &cs
->source
[0]);
214 /* 3 */ EMIT_STATE(RS_SOURCE_STRIDE
, cs
->RS_SOURCE_STRIDE
);
215 /* 4 */ EMIT_STATE_RELOC(RS_DEST_ADDR
, &cs
->dest
[0]);
216 /* 5 */ EMIT_STATE(RS_DEST_STRIDE
, cs
->RS_DEST_STRIDE
);
217 /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE
, cs
->RS_WINDOW_SIZE
);
218 /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs
->RS_DITHER
[0]);
219 /*10 */ EMIT_STATE(RS_DITHER(1), cs
->RS_DITHER
[1]);
221 /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL
, cs
->RS_CLEAR_CONTROL
);
222 /*14 */ EMIT_STATE(RS_FILL_VALUE(0), cs
->RS_FILL_VALUE
[0]);
223 /*15 */ EMIT_STATE(RS_FILL_VALUE(1), cs
->RS_FILL_VALUE
[1]);
224 /*16 */ EMIT_STATE(RS_FILL_VALUE(2), cs
->RS_FILL_VALUE
[2]);
225 /*17 */ EMIT_STATE(RS_FILL_VALUE(3), cs
->RS_FILL_VALUE
[3]);
226 /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG
, cs
->RS_EXTRA_CONFIG
);
227 /*20/21*/ EMIT_STATE(RS_KICKER
, 0xbeebbeeb);
228 etna_coalesce_end(stream
, &coalesce
);
229 } else if (screen
->specs
.pixel_pipes
== 2) {
230 etna_cmd_stream_reserve(stream
, 34); /* worst case - both pipes multi=1 */
231 etna_coalesce_start(stream
, &coalesce
);
232 /* 0/1 */ EMIT_STATE(RS_CONFIG
, cs
->RS_CONFIG
);
233 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE
, cs
->RS_SOURCE_STRIDE
);
234 /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE
, cs
->RS_DEST_STRIDE
);
235 /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs
->source
[0]);
236 if (cs
->RS_SOURCE_STRIDE
& VIVS_RS_SOURCE_STRIDE_MULTI
) {
237 /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs
->source
[1]);
240 /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs
->dest
[0]);
241 if (cs
->RS_DEST_STRIDE
& VIVS_RS_DEST_STRIDE_MULTI
) {
242 /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs
->dest
[1]);
245 /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs
->RS_PIPE_OFFSET
[0]);
246 /*16 */ EMIT_STATE(RS_PIPE_OFFSET(1), cs
->RS_PIPE_OFFSET
[1]);
248 /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE
, cs
->RS_WINDOW_SIZE
);
249 /*20/21*/ EMIT_STATE(RS_DITHER(0), cs
->RS_DITHER
[0]);
250 /*22 */ EMIT_STATE(RS_DITHER(1), cs
->RS_DITHER
[1]);
252 /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL
, cs
->RS_CLEAR_CONTROL
);
253 /*26 */ EMIT_STATE(RS_FILL_VALUE(0), cs
->RS_FILL_VALUE
[0]);
254 /*27 */ EMIT_STATE(RS_FILL_VALUE(1), cs
->RS_FILL_VALUE
[1]);
255 /*28 */ EMIT_STATE(RS_FILL_VALUE(2), cs
->RS_FILL_VALUE
[2]);
256 /*29 */ EMIT_STATE(RS_FILL_VALUE(3), cs
->RS_FILL_VALUE
[3]);
257 /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG
, cs
->RS_EXTRA_CONFIG
);
258 /*32/33*/ EMIT_STATE(RS_KICKER
, 0xbeebbeeb);
259 etna_coalesce_end(stream
, &coalesce
);
265 /* Generate clear command for a surface (non-fast clear case) */
267 etna_rs_gen_clear_surface(struct etna_context
*ctx
, struct etna_surface
*surf
,
268 uint64_t clear_value
)
270 struct etna_resource
*dst
= etna_resource(surf
->base
.texture
);
273 switch (util_format_get_blocksizebits(surf
->base
.format
)) {
275 format
= RS_FORMAT_A4R4G4B4
;
278 format
= RS_FORMAT_A8R8G8B8
;
281 assert(ctx
->specs
.halti
>= 2);
282 format
= RS_FORMAT_64BPP_CLEAR
;
285 unreachable("bpp not supported for clear by RS");
289 /* use tiled clear if width is multiple of 16 */
290 bool tiled_clear
= (surf
->surf
.padded_width
& ETNA_RS_WIDTH_MASK
) == 0 &&
291 (surf
->surf
.padded_height
& ETNA_RS_HEIGHT_MASK
) == 0;
293 etna_compile_rs_state( ctx
, &surf
->clear_command
, &(struct rs_state
) {
294 .source_format
= format
,
295 .dest_format
= format
,
297 .dest_offset
= surf
->surf
.offset
,
298 .dest_stride
= surf
->surf
.stride
,
299 .dest_padded_height
= surf
->surf
.padded_height
,
300 .dest_tiling
= tiled_clear
? dst
->layout
: ETNA_LAYOUT_LINEAR
,
301 .dither
= {0xffffffff, 0xffffffff},
302 .width
= surf
->surf
.padded_width
, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
303 .height
= surf
->surf
.padded_height
,
304 .clear_value
= {clear_value
, clear_value
>> 32, clear_value
, clear_value
>> 32},
305 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1
,
311 etna_blit_clear_color_rs(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
312 const union pipe_color_union
*color
)
314 struct etna_context
*ctx
= etna_context(pctx
);
315 struct etna_surface
*surf
= etna_surface(dst
);
316 uint64_t new_clear_value
= etna_clear_blit_pack_rgba(surf
->base
.format
, color
);
318 if (surf
->surf
.ts_size
) { /* TS: use precompiled clear command */
319 ctx
->framebuffer
.TS_COLOR_CLEAR_VALUE
= new_clear_value
;
320 ctx
->framebuffer
.TS_COLOR_CLEAR_VALUE_EXT
= new_clear_value
>> 32;
322 if (VIV_FEATURE(ctx
->screen
, chipMinorFeatures1
, AUTO_DISABLE
)) {
323 /* Set number of color tiles to be filled */
324 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_AUTO_DISABLE_COUNT
,
325 surf
->surf
.padded_width
* surf
->surf
.padded_height
/ 16);
326 ctx
->framebuffer
.TS_MEM_CONFIG
|= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE
;
329 surf
->level
->ts_valid
= true;
330 ctx
->dirty
|= ETNA_DIRTY_TS
| ETNA_DIRTY_DERIVE_TS
;
331 } else if (unlikely(new_clear_value
!= surf
->level
->clear_value
)) { /* Queue normal RS clear for non-TS surfaces */
332 /* If clear color changed, re-generate stored command */
333 etna_rs_gen_clear_surface(ctx
, surf
, new_clear_value
);
336 etna_submit_rs_state(ctx
, &surf
->clear_command
);
338 surf
->level
->clear_value
= new_clear_value
;
339 resource_written(ctx
, surf
->base
.texture
);
340 etna_resource(surf
->base
.texture
)->seqno
++;
344 etna_blit_clear_zs_rs(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
345 unsigned buffers
, double depth
, unsigned stencil
)
347 struct etna_context
*ctx
= etna_context(pctx
);
348 struct etna_surface
*surf
= etna_surface(dst
);
349 uint32_t new_clear_value
= translate_clear_depth_stencil(surf
->base
.format
, depth
, stencil
);
350 uint32_t new_clear_bits
= 0, clear_bits_depth
, clear_bits_stencil
;
352 /* Get the channels to clear */
353 switch (surf
->base
.format
) {
354 case PIPE_FORMAT_Z16_UNORM
:
355 clear_bits_depth
= 0xffff;
356 clear_bits_stencil
= 0;
358 case PIPE_FORMAT_X8Z24_UNORM
:
359 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
360 clear_bits_depth
= 0xeeee;
361 clear_bits_stencil
= 0x1111;
364 clear_bits_depth
= clear_bits_stencil
= 0xffff;
368 if (buffers
& PIPE_CLEAR_DEPTH
)
369 new_clear_bits
|= clear_bits_depth
;
370 if (buffers
& PIPE_CLEAR_STENCIL
)
371 new_clear_bits
|= clear_bits_stencil
;
372 /* FIXME: when tile status is enabled, this becomes more complex as
373 * we may separately clear the depth from the stencil. In this case,
374 * we want to resolve the surface, and avoid using the tile status.
375 * We may be better off recording the pending clear operation,
376 * delaying the actual clear to the first use. This way, we can merge
377 * consecutive clears together. */
378 if (surf
->surf
.ts_size
) { /* TS: use precompiled clear command */
379 /* Set new clear depth value */
380 ctx
->framebuffer
.TS_DEPTH_CLEAR_VALUE
= new_clear_value
;
381 if (VIV_FEATURE(ctx
->screen
, chipMinorFeatures1
, AUTO_DISABLE
)) {
382 /* Set number of depth tiles to be filled */
383 etna_set_state(ctx
->stream
, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT
,
384 surf
->surf
.padded_width
* surf
->surf
.padded_height
/ 16);
385 ctx
->framebuffer
.TS_MEM_CONFIG
|= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE
;
388 surf
->level
->ts_valid
= true;
389 ctx
->dirty
|= ETNA_DIRTY_TS
| ETNA_DIRTY_DERIVE_TS
;
391 if (unlikely(new_clear_value
!= surf
->level
->clear_value
)) { /* Queue normal RS clear for non-TS surfaces */
392 /* If clear depth value changed, re-generate stored command */
393 etna_rs_gen_clear_surface(ctx
, surf
, new_clear_value
);
395 /* Update the channels to be cleared */
396 etna_modify_rs_clearbits(&surf
->clear_command
, new_clear_bits
);
399 etna_submit_rs_state(ctx
, &surf
->clear_command
);
401 surf
->level
->clear_value
= new_clear_value
;
402 resource_written(ctx
, surf
->base
.texture
);
403 etna_resource(surf
->base
.texture
)->seqno
++;
407 etna_clear_rs(struct pipe_context
*pctx
, unsigned buffers
,
408 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
410 struct etna_context
*ctx
= etna_context(pctx
);
411 mtx_lock(&ctx
->lock
);
413 /* Flush color and depth cache before clearing anything.
414 * This is especially important when coming from another surface, as
415 * otherwise it may clear part of the old surface instead. */
416 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
417 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
419 /* Preparation: Flush the TS if needed. This must be done after flushing
420 * color and depth, otherwise it can result in crashes */
421 bool need_ts_flush
= false;
422 if ((buffers
& PIPE_CLEAR_COLOR
) && ctx
->framebuffer_s
.nr_cbufs
) {
423 struct etna_surface
*surf
= etna_surface(ctx
->framebuffer_s
.cbufs
[0]);
424 if (surf
->surf
.ts_size
)
425 need_ts_flush
= true;
427 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
) {
428 struct etna_surface
*surf
= etna_surface(ctx
->framebuffer_s
.zsbuf
);
430 if (surf
->surf
.ts_size
)
431 need_ts_flush
= true;
435 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, VIVS_TS_FLUSH_CACHE_FLUSH
);
437 /* No need to set up the TS here as RS clear operations (in contrast to
438 * resolve and copy) do not require the TS state.
440 if (buffers
& PIPE_CLEAR_COLOR
) {
441 for (int idx
= 0; idx
< ctx
->framebuffer_s
.nr_cbufs
; ++idx
) {
442 etna_blit_clear_color_rs(pctx
, ctx
->framebuffer_s
.cbufs
[idx
],
447 /* Flush the color and depth caches before each RS clear operation
448 * This fixes a hang on GC600. */
449 if (buffers
& PIPE_CLEAR_DEPTHSTENCIL
&& buffers
& PIPE_CLEAR_COLOR
)
450 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
,
451 VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
453 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
)
454 etna_blit_clear_zs_rs(pctx
, ctx
->framebuffer_s
.zsbuf
, buffers
, depth
, stencil
);
456 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
457 mtx_unlock(&ctx
->lock
);
461 etna_manual_blit(struct etna_resource
*dst
, struct etna_resource_level
*dst_lev
,
462 unsigned int dst_offset
, struct etna_resource
*src
,
463 struct etna_resource_level
*src_lev
, unsigned int src_offset
,
464 const struct pipe_blit_info
*blit_info
)
466 void *smap
, *srow
, *dmap
, *drow
;
469 assert(src
->layout
== ETNA_LAYOUT_TILED
);
470 assert(dst
->layout
== ETNA_LAYOUT_TILED
);
471 assert(src
->base
.nr_samples
== 0);
472 assert(dst
->base
.nr_samples
== 0);
474 tile_size
= util_format_get_blocksize(blit_info
->src
.format
) * 4 * 4;
476 smap
= etna_bo_map(src
->bo
);
480 dmap
= etna_bo_map(dst
->bo
);
484 srow
= smap
+ src_offset
;
485 drow
= dmap
+ dst_offset
;
487 etna_bo_cpu_prep(src
->bo
, DRM_ETNA_PREP_READ
);
488 etna_bo_cpu_prep(dst
->bo
, DRM_ETNA_PREP_WRITE
);
490 for (int y
= 0; y
< blit_info
->src
.box
.height
; y
+= 4) {
491 memcpy(drow
, srow
, tile_size
* blit_info
->src
.box
.width
);
492 srow
+= src_lev
->stride
* 4;
493 drow
+= dst_lev
->stride
* 4;
496 etna_bo_cpu_fini(dst
->bo
);
497 etna_bo_cpu_fini(src
->bo
);
503 etna_compute_tileoffset(const struct pipe_box
*box
, enum pipe_format format
,
504 size_t stride
, enum etna_surface_layout layout
)
507 unsigned int x
= box
->x
, y
= box
->y
;
508 unsigned int blocksize
= util_format_get_blocksize(format
);
511 case ETNA_LAYOUT_LINEAR
:
512 offset
= y
* stride
+ x
* blocksize
;
514 case ETNA_LAYOUT_MULTI_TILED
:
517 case ETNA_LAYOUT_TILED
:
518 assert(!(x
& 0x03) && !(y
& 0x03));
519 offset
= (y
& ~0x03) * stride
+ blocksize
* ((x
& ~0x03) << 2);
521 case ETNA_LAYOUT_MULTI_SUPERTILED
:
524 case ETNA_LAYOUT_SUPER_TILED
:
525 assert(!(x
& 0x3f) && !(y
& 0x3f));
526 offset
= (y
& ~0x3f) * stride
+ blocksize
* ((x
& ~0x3f) << 6);
529 unreachable("invalid resource layout");
536 etna_get_rs_alignment_mask(const struct etna_context
*ctx
,
537 const enum etna_surface_layout layout
,
538 unsigned int *width_mask
, unsigned int *height_mask
)
540 unsigned int h_align
, w_align
;
542 if (layout
& ETNA_LAYOUT_BIT_SUPER
) {
544 h_align
= 64 * ctx
->specs
.pixel_pipes
;
546 w_align
= ETNA_RS_WIDTH_MASK
+ 1;
547 h_align
= ETNA_RS_HEIGHT_MASK
+ 1;
550 *width_mask
= w_align
- 1;
551 *height_mask
= h_align
-1;
554 static bool msaa_config(const struct pipe_resource
*src
,
555 const struct pipe_resource
*dst
,
559 int src_xscale
= 1, src_yscale
= 1;
560 int dst_xscale
= 1, dst_yscale
= 1;
562 assert(src
->nr_samples
<= 4);
563 assert(dst
->nr_samples
<= 4);
565 translate_samples_to_xyscale(src
->nr_samples
, &src_xscale
, &src_yscale
);
566 translate_samples_to_xyscale(dst
->nr_samples
, &dst_xscale
, &dst_yscale
);
568 /* RS does not support upscaling */
569 if ((src_xscale
< dst_xscale
) || (src_yscale
< dst_yscale
))
572 *msaa_xscale
= src_xscale
- dst_xscale
+ 1;
573 *msaa_yscale
= src_yscale
- dst_yscale
+ 1;
579 etna_try_rs_blit(struct pipe_context
*pctx
,
580 const struct pipe_blit_info
*blit_info
)
582 struct etna_context
*ctx
= etna_context(pctx
);
583 struct etna_resource
*src
= etna_resource(blit_info
->src
.resource
);
584 struct etna_resource
*dst
= etna_resource(blit_info
->dst
.resource
);
585 struct compiled_rs_state copy_to_screen
;
586 int msaa_xscale
= 1, msaa_yscale
= 1;
588 /* Ensure that the level is valid */
589 assert(blit_info
->src
.level
<= src
->base
.last_level
);
590 assert(blit_info
->dst
.level
<= dst
->base
.last_level
);
592 if (!msaa_config(&src
->base
, &dst
->base
, &msaa_xscale
, &msaa_yscale
)) {
593 DBG("upsampling not supported");
597 /* The width/height are in pixels; they do not change as a result of
598 * multi-sampling. So, when blitting from a 4x multisampled surface
599 * to a non-multisampled surface, the width and height will be
600 * identical. As we do not support scaling, reject different sizes. */
601 if (blit_info
->dst
.box
.width
!= blit_info
->src
.box
.width
||
602 blit_info
->dst
.box
.height
!= blit_info
->src
.box
.height
) {
603 DBG("scaling requested: source %dx%d destination %dx%d",
604 blit_info
->src
.box
.width
, blit_info
->src
.box
.height
,
605 blit_info
->dst
.box
.width
, blit_info
->dst
.box
.height
);
609 /* No masks - RS can't copy specific channels */
610 unsigned mask
= util_format_get_mask(blit_info
->dst
.format
);
611 if ((blit_info
->mask
& mask
) != mask
) {
612 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info
->mask
, mask
);
616 /* Only support same format (used tiling/detiling) blits for now.
617 * TODO: figure out which different-format blits are possible and test them
618 * - fail if swizzle needed
619 * - avoid trying to convert between float/int formats?
621 if (blit_info
->src
.format
!= blit_info
->dst
.format
)
624 uint32_t format
= etna_compatible_rs_format(blit_info
->dst
.format
);
625 if (format
== ETNA_NO_MATCH
)
628 if (blit_info
->scissor_enable
||
629 blit_info
->dst
.box
.depth
!= blit_info
->src
.box
.depth
||
630 blit_info
->dst
.box
.depth
!= 1) {
634 unsigned w_mask
, h_mask
;
636 etna_get_rs_alignment_mask(ctx
, src
->layout
, &w_mask
, &h_mask
);
637 if ((blit_info
->src
.box
.x
& w_mask
) || (blit_info
->src
.box
.y
& h_mask
))
640 etna_get_rs_alignment_mask(ctx
, dst
->layout
, &w_mask
, &h_mask
);
641 if ((blit_info
->dst
.box
.x
& w_mask
) || (blit_info
->dst
.box
.y
& h_mask
))
644 struct etna_resource_level
*src_lev
= &src
->levels
[blit_info
->src
.level
];
645 struct etna_resource_level
*dst_lev
= &dst
->levels
[blit_info
->dst
.level
];
647 /* we may be given coordinates up to the padded width to avoid
648 * any alignment issues with different tiling formats */
649 assert((blit_info
->src
.box
.x
+ blit_info
->src
.box
.width
) * msaa_xscale
<= src_lev
->padded_width
);
650 assert((blit_info
->src
.box
.y
+ blit_info
->src
.box
.height
) * msaa_yscale
<= src_lev
->padded_height
);
651 assert(blit_info
->dst
.box
.x
+ blit_info
->dst
.box
.width
<= dst_lev
->padded_width
);
652 assert(blit_info
->dst
.box
.y
+ blit_info
->dst
.box
.height
<= dst_lev
->padded_height
);
654 unsigned src_offset
= src_lev
->offset
+
655 blit_info
->src
.box
.z
* src_lev
->layer_stride
+
656 etna_compute_tileoffset(&blit_info
->src
.box
,
657 blit_info
->src
.format
,
660 unsigned dst_offset
= dst_lev
->offset
+
661 blit_info
->dst
.box
.z
* dst_lev
->layer_stride
+
662 etna_compute_tileoffset(&blit_info
->dst
.box
,
663 blit_info
->dst
.format
,
667 if (src_lev
->padded_width
<= ETNA_RS_WIDTH_MASK
||
668 dst_lev
->padded_width
<= ETNA_RS_WIDTH_MASK
||
669 src_lev
->padded_height
<= ETNA_RS_HEIGHT_MASK
||
670 dst_lev
->padded_height
<= ETNA_RS_HEIGHT_MASK
)
673 /* If the width is not aligned to the RS width, but is within our
674 * padding, adjust the width to suite the RS width restriction.
675 * Note: the RS width/height are converted to source samples here. */
676 unsigned int width
= blit_info
->src
.box
.width
* msaa_xscale
;
677 unsigned int height
= blit_info
->src
.box
.height
* msaa_yscale
;
678 unsigned int w_align
= ETNA_RS_WIDTH_MASK
+ 1;
679 unsigned int h_align
= ETNA_RS_HEIGHT_MASK
+ 1;
681 if (width
& (w_align
- 1) && width
>= src_lev
->width
* msaa_xscale
&& width
>= dst_lev
->width
)
682 width
= align(width
, w_align
);
684 if (height
& (h_align
- 1) && height
>= src_lev
->height
* msaa_yscale
&& height
>= dst_lev
->height
)
685 height
= align(height
, h_align
);
687 /* The padded dimensions are in samples */
688 if (width
> src_lev
->padded_width
||
689 width
> dst_lev
->padded_width
* msaa_xscale
||
690 height
> src_lev
->padded_height
||
691 height
> dst_lev
->padded_height
* msaa_yscale
||
692 width
& (w_align
- 1) || height
& (h_align
- 1))
695 mtx_lock(&ctx
->lock
);
697 /* Always flush color and depth cache together before resolving. This works
698 * around artifacts that appear in some cases when scanning out a texture
699 * directly after it has been rendered to, such as rendering an animated web
700 * page in a QtWebEngine based WebView on GC2000. The artifacts look like
701 * the texture sampler samples zeroes instead of texture data in a small,
702 * irregular triangle in the lower right of each browser tile quad. Other
703 * attempts to avoid these artifacts, including a pipeline stall before the
704 * color flush or a TS cache flush afterwards, or flushing multiple times,
705 * with stalls before and after each flush, have shown no effect. */
706 if (src
->base
.bind
& PIPE_BIND_RENDER_TARGET
||
707 src
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
) {
708 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
,
709 VIVS_GL_FLUSH_CACHE_COLOR
| VIVS_GL_FLUSH_CACHE_DEPTH
);
710 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_PE
);
712 if (src_lev
->ts_size
&& src_lev
->ts_valid
)
713 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, VIVS_TS_FLUSH_CACHE_FLUSH
);
716 /* Set up color TS to source surface before blit, if needed */
717 bool source_ts_valid
= false;
718 if (src_lev
->ts_size
&& src_lev
->ts_valid
) {
719 struct etna_reloc reloc
;
721 src_lev
->ts_offset
+ blit_info
->src
.box
.z
* src_lev
->ts_layer_stride
;
722 uint32_t ts_mem_config
= 0;
724 if (src_lev
->ts_compress_fmt
>= 0) {
725 ts_mem_config
|= VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION
|
726 VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(src_lev
->ts_compress_fmt
);
729 etna_set_state(ctx
->stream
, VIVS_TS_MEM_CONFIG
,
730 VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
| ts_mem_config
);
732 memset(&reloc
, 0, sizeof(struct etna_reloc
));
733 reloc
.bo
= src
->ts_bo
;
734 reloc
.offset
= ts_offset
;
735 reloc
.flags
= ETNA_RELOC_READ
;
736 etna_set_state_reloc(ctx
->stream
, VIVS_TS_COLOR_STATUS_BASE
, &reloc
);
738 memset(&reloc
, 0, sizeof(struct etna_reloc
));
740 reloc
.offset
= src_lev
->offset
+
741 blit_info
->src
.box
.z
* src_lev
->layer_stride
;
742 reloc
.flags
= ETNA_RELOC_READ
;
743 etna_set_state_reloc(ctx
->stream
, VIVS_TS_COLOR_SURFACE_BASE
, &reloc
);
745 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_CLEAR_VALUE
, src_lev
->clear_value
);
746 etna_set_state(ctx
->stream
, VIVS_TS_COLOR_CLEAR_VALUE_EXT
, src_lev
->clear_value
>> 32);
748 source_ts_valid
= true;
750 etna_set_state(ctx
->stream
, VIVS_TS_MEM_CONFIG
, 0);
752 ctx
->dirty
|= ETNA_DIRTY_TS
;
754 /* Kick off RS here */
755 etna_compile_rs_state(ctx
, ©_to_screen
, &(struct rs_state
) {
756 .source_format
= format
,
757 .source_tiling
= src
->layout
,
759 .source_offset
= src_offset
,
760 .source_stride
= src_lev
->stride
,
761 .source_padded_width
= src_lev
->padded_width
,
762 .source_padded_height
= src_lev
->padded_height
,
763 .source_ts_valid
= source_ts_valid
,
764 .source_ts_compressed
= src_lev
->ts_compress_fmt
>= 0,
765 .dest_format
= format
,
766 .dest_tiling
= dst
->layout
,
768 .dest_offset
= dst_offset
,
769 .dest_stride
= dst_lev
->stride
,
770 .dest_padded_height
= dst_lev
->padded_height
,
771 .downsample_x
= msaa_xscale
> 1,
772 .downsample_y
= msaa_yscale
> 1,
773 .swap_rb
= translate_rb_src_dst_swap(src
->base
.format
, dst
->base
.format
),
774 .dither
= {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
775 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_DISABLED
,
778 .tile_count
= src_lev
->layer_stride
/ 64
781 etna_submit_rs_state(ctx
, ©_to_screen
);
782 resource_read(ctx
, &src
->base
);
783 resource_written(ctx
, &dst
->base
);
785 dst_lev
->ts_valid
= false;
786 ctx
->dirty
|= ETNA_DIRTY_DERIVE_TS
;
787 mtx_unlock(&ctx
->lock
);
792 if (src
->layout
== ETNA_LAYOUT_TILED
&& dst
->layout
== ETNA_LAYOUT_TILED
) {
793 if ((src
->status
& ETNA_PENDING_WRITE
) ||
794 (dst
->status
& ETNA_PENDING_WRITE
))
795 pctx
->flush(pctx
, NULL
, 0);
796 return etna_manual_blit(dst
, dst_lev
, dst_offset
, src
, src_lev
, src_offset
, blit_info
);
803 etna_blit_rs(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
805 /* This is a more extended version of resource_copy_region */
806 /* TODO Some cases can be handled by RS; if not, fall back to rendering or
807 * even CPU copy block of pixels from info->src to info->dst
808 * (resource, level, box, format);
809 * function is used for scaling, flipping in x and y direction (negative
810 * width/height), format conversion, mask and filter and even a scissor rectangle
812 * What can the RS do for us:
813 * convert between tiling formats (layouts)
814 * downsample 2x in x and y
815 * convert between a limited number of pixel formats
817 * For the rest, fall back to util_blitter
818 * XXX this goes wrong when source surface is supertiled. */
819 struct etna_context
*ctx
= etna_context(pctx
);
820 struct pipe_blit_info info
= *blit_info
;
822 if (info
.src
.resource
->nr_samples
> 1 &&
823 info
.dst
.resource
->nr_samples
<= 1 &&
824 !util_format_is_depth_or_stencil(info
.src
.resource
->format
) &&
825 !util_format_is_pure_integer(info
.src
.resource
->format
)) {
826 DBG("color resolve unimplemented");
830 if (etna_try_rs_blit(pctx
, blit_info
))
833 if (util_try_blit_via_copy_region(pctx
, blit_info
))
836 if (info
.mask
& PIPE_MASK_S
) {
837 DBG("cannot blit stencil, skipping");
838 info
.mask
&= ~PIPE_MASK_S
;
841 if (!util_blitter_is_blit_supported(ctx
->blitter
, &info
)) {
842 DBG("blit unsupported %s -> %s",
843 util_format_short_name(info
.src
.resource
->format
),
844 util_format_short_name(info
.dst
.resource
->format
));
848 etna_blit_save_state(ctx
);
849 util_blitter_blit(ctx
->blitter
, &info
);
853 etna_clear_blit_rs_init(struct pipe_context
*pctx
)
855 DBG("etnaviv: Using RS blit engine");
856 pctx
->clear
= etna_clear_rs
;
857 pctx
->blit
= etna_blit_rs
;