src/gallium/drivers/etnaviv/etnaviv_rs.c

   1 /*
   2  * Copyright (c) 2012-2017 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_rs.h"
  28
  29 #include "etnaviv_clear_blit.h"
  30 #include "etnaviv_context.h"
  31 #include "etnaviv_emit.h"
  32 #include "etnaviv_format.h"
  33 #include "etnaviv_resource.h"
  34 #include "etnaviv_screen.h"
  35 #include "etnaviv_surface.h"
  36 #include "etnaviv_tiling.h"
  37 #include "etnaviv_translate.h"
  38 #include "etnaviv_util.h"
  39
  40 #include "pipe/p_defines.h"
  41 #include "pipe/p_state.h"
  42 #include "util/u_blitter.h"
  43 #include "util/u_inlines.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_surface.h"
  46
  47 #include "hw/common.xml.h"
  48 #include "hw/state.xml.h"
  49 #include "hw/state_3d.xml.h"
  50
  51 #include <assert.h>
  52
  53 void
  54 etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
  55                       const struct rs_state *rs)
  56 {
  57    memset(cs, 0, sizeof(*cs));
  58
  59    /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
  60    unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2);
  61    unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2);
  62
  63    /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
  64    int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
  65    int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
  66
  67    /* Vivante RS needs widths to be a multiple of 16 or bad things
  68     * happen, such as scribbing over memory, or the GPU hanging,
  69     * even for non-tiled formats.  As this is serious, use abort().
  70     */
  71    if (rs->width & ETNA_RS_WIDTH_MASK)
  72       abort();
  73
  74    /* TODO could just pre-generate command buffer, would simply submit to one memcpy */
  75    cs->RS_CONFIG = VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) |
  76                    COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) |
  77                    COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) |
  78                    COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) |
  79                    VIVS_RS_CONFIG_DEST_FORMAT(rs->dest_format) |
  80                    COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) |
  81                    COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) |
  82                    COND(rs->flip, VIVS_RS_CONFIG_FLIP);
  83
  84    cs->RS_SOURCE_STRIDE = (rs->source_stride << source_stride_shift) |
  85                           COND(rs->source_tiling & 2, VIVS_RS_SOURCE_STRIDE_TILING) |
  86                           COND(source_multi, VIVS_RS_SOURCE_STRIDE_MULTI);
  87
  88    /* Initially all pipes are set to the base address of the source and
  89     * destination buffer respectively. This will be overridden below as
  90     * necessary for the multi-pipe, multi-tiled case.
  91     */
  92    for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
  93       cs->source[pipe].bo = rs->source;
  94       cs->source[pipe].offset = rs->source_offset;
  95       cs->source[pipe].flags = ETNA_RELOC_READ;
  96
  97       cs->dest[pipe].bo = rs->dest;
  98       cs->dest[pipe].offset = rs->dest_offset;
  99       cs->dest[pipe].flags = ETNA_RELOC_WRITE;
 100
 101       cs->RS_PIPE_OFFSET[pipe] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
 102    }
 103
 104    cs->RS_DEST_STRIDE = (rs->dest_stride << dest_stride_shift) |
 105                         COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) |
 106                         COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI);
 107
 108
 109    if (source_multi)
 110       cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
 111
 112    if (dest_multi)
 113       cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
 114
 115    cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
 116                         VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
 117
 118    /* use dual pipe mode when required */
 119    if (!ctx->specs.single_buffer && ctx->specs.pixel_pipes == 2 && !(rs->height & 7)) {
 120       cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
 121                               VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
 122       cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2);
 123    }
 124
 125    cs->RS_DITHER[0] = rs->dither[0];
 126    cs->RS_DITHER[1] = rs->dither[1];
 127    cs->RS_CLEAR_CONTROL = VIVS_RS_CLEAR_CONTROL_BITS(rs->clear_bits) | rs->clear_mode;
 128    cs->RS_FILL_VALUE[0] = rs->clear_value[0];
 129    cs->RS_FILL_VALUE[1] = rs->clear_value[1];
 130    cs->RS_FILL_VALUE[2] = rs->clear_value[2];
 131    cs->RS_FILL_VALUE[3] = rs->clear_value[3];
 132    cs->RS_EXTRA_CONFIG = VIVS_RS_EXTRA_CONFIG_AA(rs->aa) |
 133                          VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode);
 134
 135    /* If source the same as destination, and the hardware supports this,
 136     * do an in-place resolve to fill in unrendered tiles.
 137     */
 138    if (ctx->specs.single_buffer && rs->source == rs->dest &&
 139          rs->source_offset == rs->dest_offset &&
 140          rs->source_format == rs->dest_format &&
 141          rs->source_tiling == rs->dest_tiling &&
 142          (rs->source_tiling & ETNA_LAYOUT_BIT_SUPER) &&
 143          rs->source_stride == rs->dest_stride &&
 144          !rs->downsample_x && !rs->downsample_y &&
 145          !rs->swap_rb && !rs->flip &&
 146          !rs->clear_mode && rs->source_padded_width &&
 147          !rs->source_ts_compressed) {
 148       /* Total number of tiles (same as for autodisable) */
 149       cs->RS_KICKER_INPLACE = rs->tile_count;
 150    }
 151    cs->source_ts_valid = rs->source_ts_valid;
 152 }
 153
 154 /* modify the clear bits value in the compiled RS state */
 155 static void
 156 etna_modify_rs_clearbits(struct compiled_rs_state *cs, uint32_t clear_bits)
 157 {
 158    cs->RS_CLEAR_CONTROL &= ~VIVS_RS_CLEAR_CONTROL_BITS__MASK;
 159    cs->RS_CLEAR_CONTROL |= VIVS_RS_CLEAR_CONTROL_BITS(clear_bits);
 160 }
 161
 162 #define EMIT_STATE(state_name, src_value) \
 163    etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
 164
 165 #define EMIT_STATE_FIXP(state_name, src_value) \
 166    etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
 167
 168 #define EMIT_STATE_RELOC(state_name, src_value) \
 169    etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
 170
 171 /* submit RS state, without any processing and no dependence on context
 172  * except TS if this is a source-to-destination blit. */
 173 static void
 174 etna_submit_rs_state(struct etna_context *ctx,
 175                      const struct compiled_rs_state *cs)
 176 {
 177    struct etna_screen *screen = etna_screen(ctx->base.screen);
 178    struct etna_cmd_stream *stream = ctx->stream;
 179    struct etna_coalesce coalesce;
 180
 181    if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
 182       /* Inplace resolve is no-op if TS is not configured */
 183       return;
 184
 185    ctx->stats.rs_operations++;
 186
 187    if (cs->RS_KICKER_INPLACE) {
 188       etna_cmd_stream_reserve(stream, 6);
 189       etna_coalesce_start(stream, &coalesce);
 190       /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
 191       /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
 192       /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE);
 193       etna_coalesce_end(stream, &coalesce);
 194    } else if (screen->specs.pixel_pipes == 1) {
 195       etna_cmd_stream_reserve(stream, 22);
 196       etna_coalesce_start(stream, &coalesce);
 197       /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
 198       /* 2   */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]);
 199       /* 3   */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
 200       /* 4   */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]);
 201       /* 5   */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
 202       /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
 203       /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
 204       /*10   */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
 205       /*11 - pad */
 206       /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
 207       /*14   */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
 208       /*15   */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
 209       /*16   */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
 210       /*17   */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
 211       /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
 212       /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
 213       etna_coalesce_end(stream, &coalesce);
 214    } else if (screen->specs.pixel_pipes == 2) {
 215       etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */
 216       etna_coalesce_start(stream, &coalesce);
 217       /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
 218       /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
 219       /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
 220       /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs->source[0]);
 221       if (cs->RS_SOURCE_STRIDE & VIVS_RS_SOURCE_STRIDE_MULTI) {
 222          /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs->source[1]);
 223          /*9 - pad */
 224       }
 225       /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs->dest[0]);
 226       if (cs->RS_DEST_STRIDE & VIVS_RS_DEST_STRIDE_MULTI) {
 227          /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs->dest[1]);
 228          /*13 - pad */
 229       }
 230       /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs->RS_PIPE_OFFSET[0]);
 231       /*16   */ EMIT_STATE(RS_PIPE_OFFSET(1), cs->RS_PIPE_OFFSET[1]);
 232       /*17 - pad */
 233       /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
 234       /*20/21*/ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
 235       /*22   */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
 236       /*23 - pad */
 237       /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
 238       /*26   */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
 239       /*27   */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
 240       /*28   */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
 241       /*29   */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
 242       /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
 243       /*32/33*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
 244       etna_coalesce_end(stream, &coalesce);
 245    } else {
 246       abort();
 247    }
 248 }
 249
 250 /* Generate clear command for a surface (non-fast clear case) */
 251 void
 252 etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf,
 253                           uint32_t clear_value)
 254 {
 255    struct etna_resource *dst = etna_resource(surf->base.texture);
 256    uint32_t format;
 257
 258    switch (util_format_get_blocksizebits(surf->base.format)) {
 259    case 16:
 260       format = RS_FORMAT_A4R4G4B4;
 261       break;
 262    case 32:
 263       format = RS_FORMAT_A8R8G8B8;
 264       break;
 265    default:
 266       format = ETNA_NO_MATCH;
 267       break;
 268    }
 269
 270    if (format == ETNA_NO_MATCH) {
 271       BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", util_format_name(surf->base.format));
 272       format = RS_FORMAT_A8R8G8B8;
 273       assert(0);
 274    }
 275
 276    /* use tiled clear if width is multiple of 16 */
 277    bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
 278                       (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
 279
 280    etna_compile_rs_state( ctx, &surf->clear_command, &(struct rs_state) {
 281       .source_format = format,
 282       .dest_format = format,
 283       .dest = dst->bo,
 284       .dest_offset = surf->surf.offset,
 285       .dest_stride = surf->surf.stride,
 286       .dest_padded_height = surf->surf.padded_height,
 287       .dest_tiling = tiled_clear ? dst->layout : ETNA_LAYOUT_LINEAR,
 288       .dither = {0xffffffff, 0xffffffff},
 289       .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
 290       .height = surf->surf.padded_height,
 291       .clear_value = {clear_value},
 292       .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
 293       .clear_bits = 0xffff
 294    });
 295 }
 296
 297 static void
 298 etna_blit_clear_color_rs(struct pipe_context *pctx, struct pipe_surface *dst,
 299                       const union pipe_color_union *color)
 300 {
 301    struct etna_context *ctx = etna_context(pctx);
 302    struct etna_surface *surf = etna_surface(dst);
 303    uint32_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color->f);
 304
 305    if (surf->surf.ts_size) { /* TS: use precompiled clear command */
 306       ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
 307
 308       if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
 309          /* Set number of color tiles to be filled */
 310          etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
 311                         surf->surf.padded_width * surf->surf.padded_height / 16);
 312          ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE;
 313       }
 314
 315       surf->level->ts_valid = true;
 316       ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
 317    } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
 318       /* If clear color changed, re-generate stored command */
 319       etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
 320    }
 321
 322    etna_submit_rs_state(ctx, &surf->clear_command);
 323
 324    surf->level->clear_value = new_clear_value;
 325    resource_written(ctx, surf->base.texture);
 326    etna_resource(surf->base.texture)->seqno++;
 327 }
 328
 329 static void
 330 etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst,
 331                    unsigned buffers, double depth, unsigned stencil)
 332 {
 333    struct etna_context *ctx = etna_context(pctx);
 334    struct etna_surface *surf = etna_surface(dst);
 335    uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
 336    uint32_t new_clear_bits = 0, clear_bits_depth, clear_bits_stencil;
 337
 338    /* Get the channels to clear */
 339    switch (surf->base.format) {
 340    case PIPE_FORMAT_Z16_UNORM:
 341       clear_bits_depth = 0xffff;
 342       clear_bits_stencil = 0;
 343       break;
 344    case PIPE_FORMAT_X8Z24_UNORM:
 345    case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 346       clear_bits_depth = 0xeeee;
 347       clear_bits_stencil = 0x1111;
 348       break;
 349    default:
 350       clear_bits_depth = clear_bits_stencil = 0xffff;
 351       break;
 352    }
 353
 354    if (buffers & PIPE_CLEAR_DEPTH)
 355       new_clear_bits |= clear_bits_depth;
 356    if (buffers & PIPE_CLEAR_STENCIL)
 357       new_clear_bits |= clear_bits_stencil;
 358    /* FIXME: when tile status is enabled, this becomes more complex as
 359     * we may separately clear the depth from the stencil.  In this case,
 360     * we want to resolve the surface, and avoid using the tile status.
 361     * We may be better off recording the pending clear operation,
 362     * delaying the actual clear to the first use.  This way, we can merge
 363     * consecutive clears together. */
 364    if (surf->surf.ts_size) { /* TS: use precompiled clear command */
 365       /* Set new clear depth value */
 366       ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
 367       if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
 368          /* Set number of depth tiles to be filled */
 369          etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT,
 370                         surf->surf.padded_width * surf->surf.padded_height / 16);
 371          ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE;
 372       }
 373
 374       surf->level->ts_valid = true;
 375       ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
 376    } else {
 377       if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
 378          /* If clear depth value changed, re-generate stored command */
 379          etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
 380       }
 381       /* Update the channels to be cleared */
 382       etna_modify_rs_clearbits(&surf->clear_command, new_clear_bits);
 383    }
 384
 385    etna_submit_rs_state(ctx, &surf->clear_command);
 386
 387    surf->level->clear_value = new_clear_value;
 388    resource_written(ctx, surf->base.texture);
 389    etna_resource(surf->base.texture)->seqno++;
 390 }
 391
 392 static void
 393 etna_clear_rs(struct pipe_context *pctx, unsigned buffers,
 394            const union pipe_color_union *color, double depth, unsigned stencil)
 395 {
 396    struct etna_context *ctx = etna_context(pctx);
 397
 398    /* Flush color and depth cache before clearing anything.
 399     * This is especially important when coming from another surface, as
 400     * otherwise it may clear part of the old surface instead. */
 401    etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
 402    etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 403
 404    /* Preparation: Flush the TS if needed. This must be done after flushing
 405     * color and depth, otherwise it can result in crashes */
 406    bool need_ts_flush = false;
 407    if ((buffers & PIPE_CLEAR_COLOR) && ctx->framebuffer_s.nr_cbufs) {
 408       struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 409       if (surf->surf.ts_size)
 410          need_ts_flush = true;
 411    }
 412    if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL) {
 413       struct etna_surface *surf = etna_surface(ctx->framebuffer_s.zsbuf);
 414
 415       if (surf->surf.ts_size)
 416          need_ts_flush = true;
 417    }
 418
 419    if (need_ts_flush)
 420       etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
 421
 422    /* No need to set up the TS here as RS clear operations (in contrast to
 423     * resolve and copy) do not require the TS state.
 424     */
 425    if (buffers & PIPE_CLEAR_COLOR) {
 426       for (int idx = 0; idx < ctx->framebuffer_s.nr_cbufs; ++idx) {
 427          etna_blit_clear_color_rs(pctx, ctx->framebuffer_s.cbufs[idx],
 428                                &color[idx]);
 429       }
 430    }
 431
 432    /* Flush the color and depth caches before each RS clear operation
 433     * This fixes a hang on GC600. */
 434    if (buffers & PIPE_CLEAR_DEPTHSTENCIL && buffers & PIPE_CLEAR_COLOR)
 435       etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
 436                      VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
 437
 438    if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL)
 439       etna_blit_clear_zs_rs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
 440
 441    etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 442 }
 443
 444 static bool
 445 etna_manual_blit(struct etna_resource *dst, struct etna_resource_level *dst_lev,
 446                  unsigned int dst_offset, struct etna_resource *src,
 447                  struct etna_resource_level *src_lev, unsigned int src_offset,
 448                  const struct pipe_blit_info *blit_info)
 449 {
 450    void *smap, *srow, *dmap, *drow;
 451    size_t tile_size;
 452
 453    assert(src->layout == ETNA_LAYOUT_TILED);
 454    assert(dst->layout == ETNA_LAYOUT_TILED);
 455    assert(src->base.nr_samples == 0);
 456    assert(dst->base.nr_samples == 0);
 457
 458    tile_size = util_format_get_blocksize(blit_info->src.format) * 4 * 4;
 459
 460    smap = etna_bo_map(src->bo);
 461    if (!smap)
 462       return false;
 463
 464    dmap = etna_bo_map(dst->bo);
 465    if (!dmap)
 466       return false;
 467
 468    srow = smap + src_offset;
 469    drow = dmap + dst_offset;
 470
 471    etna_bo_cpu_prep(src->bo, DRM_ETNA_PREP_READ);
 472    etna_bo_cpu_prep(dst->bo, DRM_ETNA_PREP_WRITE);
 473
 474    for (int y = 0; y < blit_info->src.box.height; y += 4) {
 475       memcpy(drow, srow, tile_size * blit_info->src.box.width);
 476       srow += src_lev->stride * 4;
 477       drow += dst_lev->stride * 4;
 478    }
 479
 480    etna_bo_cpu_fini(dst->bo);
 481    etna_bo_cpu_fini(src->bo);
 482
 483    return true;
 484 }
 485
 486 static inline size_t
 487 etna_compute_tileoffset(const struct pipe_box *box, enum pipe_format format,
 488                         size_t stride, enum etna_surface_layout layout)
 489 {
 490    size_t offset;
 491    unsigned int x = box->x, y = box->y;
 492    unsigned int blocksize = util_format_get_blocksize(format);
 493
 494    switch (layout) {
 495    case ETNA_LAYOUT_LINEAR:
 496       offset = y * stride + x * blocksize;
 497       break;
 498    case ETNA_LAYOUT_MULTI_TILED:
 499       y >>= 1;
 500       /* fall-through */
 501    case ETNA_LAYOUT_TILED:
 502       assert(!(x & 0x03) && !(y & 0x03));
 503       offset = (y & ~0x03) * stride + blocksize * ((x & ~0x03) << 2);
 504       break;
 505    case ETNA_LAYOUT_MULTI_SUPERTILED:
 506       y >>= 1;
 507       /* fall-through */
 508    case ETNA_LAYOUT_SUPER_TILED:
 509       assert(!(x & 0x3f) && !(y & 0x3f));
 510       offset = (y & ~0x3f) * stride + blocksize * ((x & ~0x3f) << 6);
 511       break;
 512    default:
 513       unreachable("invalid resource layout");
 514    }
 515
 516    return offset;
 517 }
 518
 519 static inline void
 520 etna_get_rs_alignment_mask(const struct etna_context *ctx,
 521                            const enum etna_surface_layout layout,
 522                            unsigned int *width_mask, unsigned int *height_mask)
 523 {
 524    unsigned int h_align, w_align;
 525
 526    if (layout & ETNA_LAYOUT_BIT_SUPER) {
 527       w_align = 64;
 528       h_align = 64 * ctx->specs.pixel_pipes;
 529    } else {
 530       w_align = ETNA_RS_WIDTH_MASK + 1;
 531       h_align = ETNA_RS_HEIGHT_MASK + 1;
 532    }
 533
 534    *width_mask = w_align - 1;
 535    *height_mask = h_align -1;
 536 }
 537
 538 static bool
 539 etna_try_rs_blit(struct pipe_context *pctx,
 540                  const struct pipe_blit_info *blit_info)
 541 {
 542    struct etna_context *ctx = etna_context(pctx);
 543    struct etna_resource *src = etna_resource(blit_info->src.resource);
 544    struct etna_resource *dst = etna_resource(blit_info->dst.resource);
 545    struct compiled_rs_state copy_to_screen;
 546    int msaa_xscale = 1, msaa_yscale = 1;
 547
 548    /* Ensure that the level is valid */
 549    assert(blit_info->src.level <= src->base.last_level);
 550    assert(blit_info->dst.level <= dst->base.last_level);
 551
 552    if (!translate_samples_to_xyscale(src->base.nr_samples, &msaa_xscale, &msaa_yscale, NULL))
 553       return false;
 554
 555    /* The width/height are in pixels; they do not change as a result of
 556     * multi-sampling. So, when blitting from a 4x multisampled surface
 557     * to a non-multisampled surface, the width and height will be
 558     * identical. As we do not support scaling, reject different sizes. */
 559    if (blit_info->dst.box.width != blit_info->src.box.width ||
 560        blit_info->dst.box.height != blit_info->src.box.height) {
 561       DBG("scaling requested: source %dx%d destination %dx%d",
 562           blit_info->src.box.width, blit_info->src.box.height,
 563           blit_info->dst.box.width, blit_info->dst.box.height);
 564       return false;
 565    }
 566
 567    /* No masks - RS can't copy specific channels */
 568    unsigned mask = util_format_get_mask(blit_info->dst.format);
 569    if ((blit_info->mask & mask) != mask) {
 570       DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info->mask, mask);
 571       return false;
 572    }
 573
 574    unsigned src_format = blit_info->src.format;
 575    unsigned dst_format = blit_info->dst.format;
 576
 577    /* for a copy with same dst/src format, we can use a different format */
 578    if (translate_rs_format(src_format) == ETNA_NO_MATCH &&
 579        src_format == dst_format) {
 580       src_format = dst_format = etna_compatible_rs_format(src_format);
 581    }
 582
 583    if (translate_rs_format(src_format) == ETNA_NO_MATCH ||
 584        translate_rs_format(dst_format) == ETNA_NO_MATCH ||
 585        blit_info->scissor_enable ||
 586        blit_info->dst.box.depth != blit_info->src.box.depth ||
 587        blit_info->dst.box.depth != 1) {
 588       return false;
 589    }
 590
 591    unsigned w_mask, h_mask;
 592
 593    etna_get_rs_alignment_mask(ctx, src->layout, &w_mask, &h_mask);
 594    if ((blit_info->src.box.x & w_mask) || (blit_info->src.box.y & h_mask))
 595       return false;
 596
 597    etna_get_rs_alignment_mask(ctx, dst->layout, &w_mask, &h_mask);
 598    if ((blit_info->dst.box.x & w_mask) || (blit_info->dst.box.y & h_mask))
 599       return false;
 600
 601    /* Ensure that the Z coordinate is sane */
 602    if (dst->base.target != PIPE_TEXTURE_CUBE)
 603       assert(blit_info->dst.box.z == 0);
 604    if (src->base.target != PIPE_TEXTURE_CUBE)
 605       assert(blit_info->src.box.z == 0);
 606
 607    assert(blit_info->src.box.z < src->base.array_size);
 608    assert(blit_info->dst.box.z < dst->base.array_size);
 609
 610    struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
 611    struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
 612
 613    /* we may be given coordinates up to the padded width to avoid
 614     * any alignment issues with different tiling formats */
 615    assert((blit_info->src.box.x + blit_info->src.box.width) * msaa_xscale <= src_lev->padded_width);
 616    assert((blit_info->src.box.y + blit_info->src.box.height) * msaa_yscale <= src_lev->padded_height);
 617    assert(blit_info->dst.box.x + blit_info->dst.box.width <= dst_lev->padded_width);
 618    assert(blit_info->dst.box.y + blit_info->dst.box.height <= dst_lev->padded_height);
 619
 620    unsigned src_offset = src_lev->offset +
 621                          blit_info->src.box.z * src_lev->layer_stride +
 622                          etna_compute_tileoffset(&blit_info->src.box,
 623                                                  blit_info->src.format,
 624                                                  src_lev->stride,
 625                                                  src->layout);
 626    unsigned dst_offset = dst_lev->offset +
 627                          blit_info->dst.box.z * dst_lev->layer_stride +
 628                          etna_compute_tileoffset(&blit_info->dst.box,
 629                                                  blit_info->dst.format,
 630                                                  dst_lev->stride,
 631                                                  dst->layout);
 632
 633    if (src_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
 634        dst_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
 635        src_lev->padded_height <= ETNA_RS_HEIGHT_MASK ||
 636        dst_lev->padded_height <= ETNA_RS_HEIGHT_MASK)
 637       goto manual;
 638
 639    /* If the width is not aligned to the RS width, but is within our
 640     * padding, adjust the width to suite the RS width restriction.
 641     * Note: the RS width/height are converted to source samples here. */
 642    unsigned int width = blit_info->src.box.width * msaa_xscale;
 643    unsigned int height = blit_info->src.box.height * msaa_yscale;
 644    unsigned int w_align = ETNA_RS_WIDTH_MASK + 1;
 645    unsigned int h_align = ETNA_RS_HEIGHT_MASK + 1;
 646
 647    if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
 648       width = align(width, w_align);
 649
 650    if (height & (h_align - 1) && height >= src_lev->height * msaa_yscale && height >= dst_lev->height)
 651       height = align(height, h_align);
 652
 653    /* The padded dimensions are in samples */
 654    if (width > src_lev->padded_width ||
 655        width > dst_lev->padded_width * msaa_xscale ||
 656        height > src_lev->padded_height ||
 657        height > dst_lev->padded_height * msaa_yscale ||
 658        width & (w_align - 1) || height & (h_align - 1))
 659       goto manual;
 660
 661    /* Always flush color and depth cache together before resolving. This works
 662     * around artifacts that appear in some cases when scanning out a texture
 663     * directly after it has been rendered to, such as rendering an animated web
 664     * page in a QtWebEngine based WebView on GC2000. The artifacts look like
 665     * the texture sampler samples zeroes instead of texture data in a small,
 666     * irregular triangle in the lower right of each browser tile quad. Other
 667     * attempts to avoid these artifacts, including a pipeline stall before the
 668     * color flush or a TS cache flush afterwards, or flushing multiple times,
 669     * with stalls before and after each flush, have shown no effect. */
 670    if (src->base.bind & PIPE_BIND_RENDER_TARGET ||
 671        src->base.bind & PIPE_BIND_DEPTH_STENCIL) {
 672       etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
 673                      VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
 674       etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 675
 676       if (src_lev->ts_size && src_lev->ts_valid)
 677          etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
 678    }
 679
 680    /* Set up color TS to source surface before blit, if needed */
 681    bool source_ts_valid = false;
 682    if (src_lev->ts_size && src_lev->ts_valid) {
 683       struct etna_reloc reloc;
 684       unsigned ts_offset =
 685          src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
 686       uint32_t ts_mem_config = 0;
 687
 688       if (src_lev->ts_compress_fmt >= 0) {
 689          ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 690                           VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(src_lev->ts_compress_fmt);
 691       }
 692
 693       etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG,
 694                      VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config);
 695
 696       memset(&reloc, 0, sizeof(struct etna_reloc));
 697       reloc.bo = src->ts_bo;
 698       reloc.offset = ts_offset;
 699       reloc.flags = ETNA_RELOC_READ;
 700       etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_STATUS_BASE, &reloc);
 701
 702       memset(&reloc, 0, sizeof(struct etna_reloc));
 703       reloc.bo = src->bo;
 704       reloc.offset = src_lev->offset +
 705                      blit_info->src.box.z * src_lev->layer_stride;
 706       reloc.flags = ETNA_RELOC_READ;
 707       etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_SURFACE_BASE, &reloc);
 708
 709       etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE, src_lev->clear_value);
 710
 711       source_ts_valid = true;
 712    } else {
 713       etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, 0);
 714    }
 715    ctx->dirty |= ETNA_DIRTY_TS;
 716
 717    /* Kick off RS here */
 718    etna_compile_rs_state(ctx, &copy_to_screen, &(struct rs_state) {
 719       .source_format = translate_rs_format(src_format),
 720       .source_tiling = src->layout,
 721       .source = src->bo,
 722       .source_offset = src_offset,
 723       .source_stride = src_lev->stride,
 724       .source_padded_width = src_lev->padded_width,
 725       .source_padded_height = src_lev->padded_height,
 726       .source_ts_valid = source_ts_valid,
 727       .source_ts_compressed = src_lev->ts_compress_fmt >= 0,
 728       .dest_format = translate_rs_format(dst_format),
 729       .dest_tiling = dst->layout,
 730       .dest = dst->bo,
 731       .dest_offset = dst_offset,
 732       .dest_stride = dst_lev->stride,
 733       .dest_padded_height = dst_lev->padded_height,
 734       .downsample_x = msaa_xscale > 1,
 735       .downsample_y = msaa_yscale > 1,
 736       .swap_rb = translate_rb_src_dst_swap(src->base.format, dst->base.format),
 737       .dither = {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
 738       .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
 739       .width = width,
 740       .height = height,
 741       .tile_count = src_lev->layer_stride / 64
 742    });
 743
 744    etna_submit_rs_state(ctx, &copy_to_screen);
 745    resource_read(ctx, &src->base);
 746    resource_written(ctx, &dst->base);
 747    dst->seqno++;
 748    dst_lev->ts_valid = false;
 749    ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
 750
 751    return true;
 752
 753 manual:
 754    if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) {
 755       if ((src->status & ETNA_PENDING_WRITE) ||
 756           (dst->status & ETNA_PENDING_WRITE))
 757          pctx->flush(pctx, NULL, 0);
 758       return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info);
 759    }
 760
 761    return false;
 762 }
 763
 764 static void
 765 etna_blit_rs(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
 766 {
 767    /* This is a more extended version of resource_copy_region */
 768    /* TODO Some cases can be handled by RS; if not, fall back to rendering or
 769     * even CPU copy block of pixels from info->src to info->dst
 770     * (resource, level, box, format);
 771     * function is used for scaling, flipping in x and y direction (negative
 772     * width/height), format conversion, mask and filter and even a scissor rectangle
 773     *
 774     * What can the RS do for us:
 775     *   convert between tiling formats (layouts)
 776     *   downsample 2x in x and y
 777     *   convert between a limited number of pixel formats
 778     *
 779     * For the rest, fall back to util_blitter
 780     * XXX this goes wrong when source surface is supertiled. */
 781    struct etna_context *ctx = etna_context(pctx);
 782    struct pipe_blit_info info = *blit_info;
 783
 784    if (info.src.resource->nr_samples > 1 &&
 785        info.dst.resource->nr_samples <= 1 &&
 786        !util_format_is_depth_or_stencil(info.src.resource->format) &&
 787        !util_format_is_pure_integer(info.src.resource->format)) {
 788       DBG("color resolve unimplemented");
 789       return;
 790    }
 791
 792    if (etna_try_rs_blit(pctx, blit_info))
 793       return;
 794
 795    if (util_try_blit_via_copy_region(pctx, blit_info))
 796       return;
 797
 798    if (info.mask & PIPE_MASK_S) {
 799       DBG("cannot blit stencil, skipping");
 800       info.mask &= ~PIPE_MASK_S;
 801    }
 802
 803    if (!util_blitter_is_blit_supported(ctx->blitter, &info)) {
 804       DBG("blit unsupported %s -> %s",
 805           util_format_short_name(info.src.resource->format),
 806           util_format_short_name(info.dst.resource->format));
 807       return;
 808    }
 809
 810    etna_blit_save_state(ctx);
 811    util_blitter_blit(ctx->blitter, &info);
 812 }
 813
 814 void
 815 etna_clear_blit_rs_init(struct pipe_context *pctx)
 816 {
 817    DBG("etnaviv: Using RS blit engine");
 818    pctx->clear = etna_clear_rs;
 819    pctx->blit = etna_blit_rs;
 820 }