2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
28 #include "etnaviv_screen.h"
30 #include "hw/common.xml.h"
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
41 #include "os/os_time.h"
42 #include "util/u_math.h"
43 #include "util/u_memory.h"
44 #include "util/u_string.h"
46 #include "state_tracker/drm_driver.h"
48 static const struct debug_named_value debug_options
[] = {
49 {"dbg_msgs", ETNA_DBG_MSGS
, "Print debug messages"},
50 {"frame_msgs", ETNA_DBG_FRAME_MSGS
, "Print frame messages"},
51 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS
, "Print resource messages"},
52 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS
, "Print compiler messages"},
53 {"linker_msgs", ETNA_DBG_LINKER_MSGS
, "Print linker messages"},
54 {"dump_shaders", ETNA_DBG_DUMP_SHADERS
, "Dump shaders"},
55 {"no_ts", ETNA_DBG_NO_TS
, "Disable TS"},
56 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE
, "Disable autodisable"},
57 {"no_supertile", ETNA_DBG_NO_SUPERTILE
, "Disable supertiles"},
58 {"no_early_z", ETNA_DBG_NO_EARLY_Z
, "Disable early z"},
59 {"cflush_all", ETNA_DBG_CFLUSH_ALL
, "Flush every cash before state update"},
60 {"msaa2x", ETNA_DBG_MSAA_2X
, "Force 2x msaa"},
61 {"msaa4x", ETNA_DBG_MSAA_4X
, "Force 4x msaa"},
62 {"flush_all", ETNA_DBG_FLUSH_ALL
, "Flush after every rendered primitive"},
63 {"zero", ETNA_DBG_ZERO
, "Zero all resources after allocation"},
64 {"draw_stall", ETNA_DBG_DRAW_STALL
, "Stall FE/PE after each rendered primitive"},
65 {"shaderdb", ETNA_DBG_SHADERDB
, "Enable shaderdb output"},
69 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug
, "ETNA_MESA_DEBUG", debug_options
, 0)
70 int etna_mesa_debug
= 0;
73 etna_screen_destroy(struct pipe_screen
*pscreen
)
75 struct etna_screen
*screen
= etna_screen(pscreen
);
78 etna_pipe_del(screen
->pipe
);
81 etna_gpu_del(screen
->gpu
);
87 etna_device_del(screen
->dev
);
93 etna_screen_get_name(struct pipe_screen
*pscreen
)
95 struct etna_screen
*priv
= etna_screen(pscreen
);
96 static char buffer
[128];
98 util_snprintf(buffer
, sizeof(buffer
), "Vivante GC%x rev %04x", priv
->model
,
105 etna_screen_get_vendor(struct pipe_screen
*pscreen
)
111 etna_screen_get_device_vendor(struct pipe_screen
*pscreen
)
117 etna_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
119 struct etna_screen
*screen
= etna_screen(pscreen
);
122 /* Supported features (boolean caps). */
123 case PIPE_CAP_TWO_SIDED_STENCIL
:
124 case PIPE_CAP_ANISOTROPIC_FILTER
:
125 case PIPE_CAP_POINT_SPRITE
:
126 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
127 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
128 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
129 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
131 case PIPE_CAP_TEXTURE_BARRIER
:
132 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
133 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
134 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
135 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
136 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
137 case PIPE_CAP_TGSI_TEXCOORD
:
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
142 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
144 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
145 return 4; /* XXX could easily be supported */
146 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
149 case PIPE_CAP_NPOT_TEXTURES
:
150 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
151 NON_POWER_OF_TWO); */
153 case PIPE_CAP_PRIMITIVE_RESTART
:
154 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
156 case PIPE_CAP_ENDIANNESS
:
157 return PIPE_ENDIAN_LITTLE
; /* on most Viv hw this is configurable (feature
158 ENDIANNESS_CONFIG) */
160 /* Unsupported features. */
161 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
162 case PIPE_CAP_TEXTURE_SWIZZLE
: /* XXX supported on gc2000 */
163 case PIPE_CAP_COMPUTE
: /* XXX supported on gc2000 */
164 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
: /* only one colorbuffer supported, so mixing makes no sense */
165 case PIPE_CAP_CONDITIONAL_RENDER
: /* no occlusion queries */
166 case PIPE_CAP_TGSI_INSTANCEID
: /* no idea, really */
167 case PIPE_CAP_START_INSTANCE
: /* instancing not supported AFAIK */
168 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
: /* instancing not supported AFAIK */
169 case PIPE_CAP_SHADER_STENCIL_EXPORT
: /* Fragment shader cannot export stencil value */
170 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
: /* no dual-source supported */
171 case PIPE_CAP_TEXTURE_MULTISAMPLE
: /* no texture multisample */
172 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
: /* only mirrored repeat */
173 case PIPE_CAP_INDEP_BLEND_ENABLE
:
174 case PIPE_CAP_INDEP_BLEND_FUNC
:
175 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
176 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
177 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
178 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
179 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
: /* Don't skip strict max uniform limit check */
180 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
181 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
182 case PIPE_CAP_USER_VERTEX_BUFFERS
:
183 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
184 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
185 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
186 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
: /* TODO: test me out with piglit */
187 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
188 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
189 case PIPE_CAP_TEXTURE_GATHER_SM5
:
190 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
191 case PIPE_CAP_FAKE_SW_MSAA
:
192 case PIPE_CAP_TEXTURE_QUERY_LOD
:
193 case PIPE_CAP_SAMPLE_SHADING
:
194 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
195 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
196 case PIPE_CAP_DRAW_INDIRECT
:
197 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
198 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
199 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
200 case PIPE_CAP_CLIP_HALFZ
:
201 case PIPE_CAP_VERTEXID_NOBASE
:
202 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
203 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
204 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
205 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
206 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
207 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
208 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
209 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
210 case PIPE_CAP_TGSI_TXQS
:
211 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
212 case PIPE_CAP_SHAREABLE_SHADERS
:
213 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
214 case PIPE_CAP_CLEAR_TEXTURE
:
215 case PIPE_CAP_DRAW_PARAMETERS
:
216 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
217 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
218 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
219 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
220 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
221 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
222 case PIPE_CAP_INVALIDATE_BUFFER
:
223 case PIPE_CAP_GENERATE_MIPMAP
:
224 case PIPE_CAP_STRING_MARKER
:
225 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
226 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
227 case PIPE_CAP_QUERY_MEMORY_INFO
:
228 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
229 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
230 case PIPE_CAP_CULL_DISTANCE
:
231 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
232 case PIPE_CAP_TGSI_VOTE
:
233 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
234 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
235 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
236 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
237 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
238 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
239 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
240 case PIPE_CAP_NATIVE_FENCE_FD
:
241 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
242 case PIPE_CAP_TGSI_FS_FBFETCH
:
243 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
244 case PIPE_CAP_DOUBLES
:
246 case PIPE_CAP_INT64_DIVMOD
:
247 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
251 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
252 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
253 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
254 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
257 /* Geometry shader output, unsupported. */
258 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
259 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
260 case PIPE_CAP_MAX_VERTEX_STREAMS
:
263 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
267 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
268 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
270 int log2_max_tex_size
= util_last_bit(screen
->specs
.max_texture_size
);
271 assert(log2_max_tex_size
> 0);
272 return log2_max_tex_size
;
274 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
: /* 3D textures not supported - fake it */
276 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
278 case PIPE_CAP_CUBE_MAP_ARRAY
:
280 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
281 case PIPE_CAP_MIN_TEXEL_OFFSET
:
283 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
284 case PIPE_CAP_MAX_TEXEL_OFFSET
:
286 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
288 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
291 /* Render targets. */
292 case PIPE_CAP_MAX_RENDER_TARGETS
:
295 /* Viewports and scissors. */
296 case PIPE_CAP_MAX_VIEWPORTS
:
300 case PIPE_CAP_QUERY_TIME_ELAPSED
:
301 case PIPE_CAP_OCCLUSION_QUERY
:
303 case PIPE_CAP_QUERY_TIMESTAMP
:
305 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
309 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
312 case PIPE_CAP_PCI_GROUP
:
313 case PIPE_CAP_PCI_BUS
:
314 case PIPE_CAP_PCI_DEVICE
:
315 case PIPE_CAP_PCI_FUNCTION
:
317 case PIPE_CAP_VENDOR_ID
:
318 case PIPE_CAP_DEVICE_ID
:
320 case PIPE_CAP_ACCELERATED
:
322 case PIPE_CAP_VIDEO_MEMORY
:
328 debug_printf("unknown param %d", param
);
333 etna_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
336 case PIPE_CAPF_MAX_LINE_WIDTH
:
337 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
338 case PIPE_CAPF_MAX_POINT_WIDTH
:
339 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
341 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
343 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
345 case PIPE_CAPF_GUARD_BAND_LEFT
:
346 case PIPE_CAPF_GUARD_BAND_TOP
:
347 case PIPE_CAPF_GUARD_BAND_RIGHT
:
348 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
352 debug_printf("unknown paramf %d", param
);
357 etna_screen_get_shader_param(struct pipe_screen
*pscreen
,
358 enum pipe_shader_type shader
,
359 enum pipe_shader_cap param
)
361 struct etna_screen
*screen
= etna_screen(pscreen
);
364 case PIPE_SHADER_FRAGMENT
:
365 case PIPE_SHADER_VERTEX
:
367 case PIPE_SHADER_COMPUTE
:
368 case PIPE_SHADER_GEOMETRY
:
369 case PIPE_SHADER_TESS_CTRL
:
370 case PIPE_SHADER_TESS_EVAL
:
373 DBG("unknown shader type %d", shader
);
378 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
379 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
380 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
381 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
382 return ETNA_MAX_TOKENS
;
383 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
384 return ETNA_MAX_DEPTH
; /* XXX */
385 case PIPE_SHADER_CAP_MAX_INPUTS
:
386 /* Maximum number of inputs for the vertex shader is the number
387 * of vertex elements - each element defines one vertex shader
388 * input register. For the fragment shader, this is the number
390 return shader
== PIPE_SHADER_FRAGMENT
? screen
->specs
.max_varyings
391 : screen
->specs
.vertex_max_elements
;
392 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
393 return 16; /* see VIVS_VS_OUTPUT */
394 case PIPE_SHADER_CAP_MAX_TEMPS
:
395 return 64; /* Max native temporaries. */
396 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
398 case PIPE_SHADER_CAP_MAX_PREDS
:
399 return 0; /* nothing uses this */
400 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
402 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
403 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
404 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
405 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
407 case PIPE_SHADER_CAP_SUBROUTINES
:
409 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
410 return VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
411 case PIPE_SHADER_CAP_INTEGERS
:
413 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
414 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
415 return shader
== PIPE_SHADER_FRAGMENT
416 ? screen
->specs
.fragment_sampler_count
417 : screen
->specs
.vertex_sampler_count
;
418 case PIPE_SHADER_CAP_PREFERRED_IR
:
419 return PIPE_SHADER_IR_TGSI
;
420 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
422 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
423 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
424 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
425 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
427 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
429 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
431 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
432 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
433 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
437 debug_printf("unknown shader param %d", param
);
442 etna_screen_get_timestamp(struct pipe_screen
*pscreen
)
444 return os_time_get_nano();
448 gpu_supports_texure_format(struct etna_screen
*screen
, uint32_t fmt
)
450 if (fmt
== TEXTURE_FORMAT_ETC1
)
451 return VIV_FEATURE(screen
, chipFeatures
, ETC1_TEXTURE_COMPRESSION
);
453 if (fmt
>= TEXTURE_FORMAT_DXT1
&& fmt
<= TEXTURE_FORMAT_DXT4_DXT5
)
454 return VIV_FEATURE(screen
, chipFeatures
, DXT_TEXTURE_COMPRESSION
);
460 etna_screen_is_format_supported(struct pipe_screen
*pscreen
,
461 enum pipe_format format
,
462 enum pipe_texture_target target
,
463 unsigned sample_count
, unsigned usage
)
465 struct etna_screen
*screen
= etna_screen(pscreen
);
466 unsigned allowed
= 0;
468 if (target
!= PIPE_BUFFER
&&
469 target
!= PIPE_TEXTURE_1D
&&
470 target
!= PIPE_TEXTURE_2D
&&
471 target
!= PIPE_TEXTURE_3D
&&
472 target
!= PIPE_TEXTURE_CUBE
&&
473 target
!= PIPE_TEXTURE_RECT
)
476 if (usage
& PIPE_BIND_RENDER_TARGET
) {
477 /* If render target, must be RS-supported format that is not rb swapped.
478 * Exposing rb swapped (or other swizzled) formats for rendering would
479 * involve swizzing in the pixel shader.
481 if (translate_rs_format(format
) != ETNA_NO_MATCH
&& !translate_rs_format_rb_swap(format
)) {
482 /* Validate MSAA; number of samples must be allowed, and render target
483 * must have MSAA'able format. */
484 if (sample_count
> 1) {
485 if (translate_samples_to_xyscale(sample_count
, NULL
, NULL
, NULL
) &&
486 translate_msaa_format(format
) != ETNA_NO_MATCH
) {
487 allowed
|= PIPE_BIND_RENDER_TARGET
;
490 allowed
|= PIPE_BIND_RENDER_TARGET
;
495 if (usage
& PIPE_BIND_DEPTH_STENCIL
) {
496 if (translate_depth_format(format
) != ETNA_NO_MATCH
)
497 allowed
|= PIPE_BIND_DEPTH_STENCIL
;
500 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
501 uint32_t fmt
= translate_texture_format(format
);
503 if (!gpu_supports_texure_format(screen
, fmt
))
506 if (sample_count
< 2 && fmt
!= ETNA_NO_MATCH
)
507 allowed
|= PIPE_BIND_SAMPLER_VIEW
;
510 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
511 if (translate_vertex_format_type(format
) != ETNA_NO_MATCH
)
512 allowed
|= PIPE_BIND_VERTEX_BUFFER
;
515 if (usage
& PIPE_BIND_INDEX_BUFFER
) {
516 /* must be supported index format */
517 if (format
== PIPE_FORMAT_I8_UINT
|| format
== PIPE_FORMAT_I16_UINT
||
518 (format
== PIPE_FORMAT_I32_UINT
&&
519 VIV_FEATURE(screen
, chipFeatures
, 32_BIT_INDICES
))) {
520 allowed
|= PIPE_BIND_INDEX_BUFFER
;
526 usage
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
);
528 if (usage
!= allowed
) {
529 DBG("not supported: format=%s, target=%d, sample_count=%d, "
530 "usage=%x, allowed=%x",
531 util_format_name(format
), target
, sample_count
, usage
, allowed
);
534 return usage
== allowed
;
538 etna_get_specs(struct etna_screen
*screen
)
541 uint32_t instruction_count
;
543 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_INSTRUCTION_COUNT
, &val
)) {
544 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
547 instruction_count
= val
;
549 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE
,
551 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
554 screen
->specs
.vertex_output_buffer_size
= val
;
556 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_CACHE_SIZE
, &val
)) {
557 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
560 screen
->specs
.vertex_cache_size
= val
;
562 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_SHADER_CORE_COUNT
, &val
)) {
563 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
566 screen
->specs
.shader_core_count
= val
;
568 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_STREAM_COUNT
, &val
)) {
569 DBG("could not get ETNA_GPU_STREAM_COUNT");
572 screen
->specs
.stream_count
= val
;
574 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REGISTER_MAX
, &val
)) {
575 DBG("could not get ETNA_GPU_REGISTER_MAX");
578 screen
->specs
.max_registers
= val
;
580 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_PIXEL_PIPES
, &val
)) {
581 DBG("could not get ETNA_GPU_PIXEL_PIPES");
584 screen
->specs
.pixel_pipes
= val
;
586 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_NUM_CONSTANTS
, &val
)) {
587 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
591 fprintf(stderr
, "Warning: zero num constants (update kernel?)\n");
594 screen
->specs
.num_constants
= val
;
596 screen
->specs
.can_supertile
=
597 VIV_FEATURE(screen
, chipMinorFeatures0
, SUPER_TILED
);
598 screen
->specs
.bits_per_tile
=
599 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 2 : 4;
600 screen
->specs
.ts_clear_value
=
601 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 0x55555555
604 /* vertex and fragment samplers live in one address space */
605 screen
->specs
.vertex_sampler_offset
= 8;
606 screen
->specs
.fragment_sampler_count
= 8;
607 screen
->specs
.vertex_sampler_count
= 4;
608 screen
->specs
.vs_need_z_div
=
609 screen
->model
< 0x1000 && screen
->model
!= 0x880;
610 screen
->specs
.has_sin_cos_sqrt
=
611 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
612 screen
->specs
.has_sign_floor_ceil
=
613 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SIGN_FLOOR_CEIL
);
614 screen
->specs
.has_shader_range_registers
=
615 screen
->model
>= 0x1000 || screen
->model
== 0x880;
616 screen
->specs
.npot_tex_any_wrap
=
617 VIV_FEATURE(screen
, chipMinorFeatures1
, NON_POWER_OF_TWO
);
618 screen
->specs
.has_new_sin_cos
=
619 VIV_FEATURE(screen
, chipMinorFeatures3
, HAS_FAST_TRANSCENDENTALS
);
621 if (VIV_FEATURE(screen
, chipMinorFeatures3
, INSTRUCTION_CACHE
)) {
622 /* GC3000 - this core is capable of loading shaders from
623 * memory. It can also run shaders from registers, as a fallback, but
624 * "max_instructions" does not have the correct value. It has place for
625 * 2*256 instructions just like GC2000, but the offsets are slightly
628 screen
->specs
.vs_offset
= 0xC000;
629 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
630 * this mirror for writing PS instructions, probably safest to do the
633 screen
->specs
.ps_offset
= 0x8000 + 0x1000;
634 screen
->specs
.max_instructions
= 256;
636 if (instruction_count
> 256) { /* unified instruction memory? */
637 screen
->specs
.vs_offset
= 0xC000;
638 screen
->specs
.ps_offset
= 0xD000; /* like vivante driver */
639 screen
->specs
.max_instructions
= 256;
641 screen
->specs
.vs_offset
= 0x4000;
642 screen
->specs
.ps_offset
= 0x6000;
643 screen
->specs
.max_instructions
= instruction_count
/ 2;
647 if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
)) {
648 screen
->specs
.max_varyings
= 12;
649 screen
->specs
.vertex_max_elements
= 16;
651 screen
->specs
.max_varyings
= 8;
652 /* Etna_viv documentation seems confused over the correct value
653 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
654 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
655 screen
->specs
.vertex_max_elements
= 10;
658 /* Etna_viv documentation does not indicate where varyings above 8 are
659 * stored. Moreover, if we are passed more than 8 varyings, we will
660 * walk off the end of some arrays. Limit the maximum number of varyings. */
661 if (screen
->specs
.max_varyings
> ETNA_NUM_VARYINGS
)
662 screen
->specs
.max_varyings
= ETNA_NUM_VARYINGS
;
664 /* from QueryShaderCaps in kernel driver */
665 if (screen
->model
< chipModel_GC4000
) {
666 screen
->specs
.max_vs_uniforms
= 168;
667 screen
->specs
.max_ps_uniforms
= 64;
669 screen
->specs
.max_vs_uniforms
= 256;
670 screen
->specs
.max_ps_uniforms
= 256;
673 screen
->specs
.max_texture_size
=
674 VIV_FEATURE(screen
, chipMinorFeatures0
, TEXTURE_8K
) ? 8192 : 2048;
675 screen
->specs
.max_rendertarget_size
=
676 VIV_FEATURE(screen
, chipMinorFeatures0
, RENDERTARGET_8K
) ? 8192 : 2048;
685 etna_screen_bo_get_handle(struct pipe_screen
*pscreen
, struct etna_bo
*bo
,
686 unsigned stride
, struct winsys_handle
*whandle
)
688 whandle
->stride
= stride
;
690 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
691 return etna_bo_get_name(bo
, &whandle
->handle
) == 0;
692 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_KMS
) {
693 whandle
->handle
= etna_bo_handle(bo
);
695 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
696 whandle
->handle
= etna_bo_dmabuf(bo
);
704 etna_screen_bo_from_handle(struct pipe_screen
*pscreen
,
705 struct winsys_handle
*whandle
, unsigned *out_stride
)
707 struct etna_screen
*screen
= etna_screen(pscreen
);
710 if (whandle
->type
== DRM_API_HANDLE_TYPE_SHARED
) {
711 bo
= etna_bo_from_name(screen
->dev
, whandle
->handle
);
712 } else if (whandle
->type
== DRM_API_HANDLE_TYPE_FD
) {
713 bo
= etna_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
715 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
720 DBG("ref name 0x%08x failed", whandle
->handle
);
724 *out_stride
= whandle
->stride
;
730 etna_screen_create(struct etna_device
*dev
, struct etna_gpu
*gpu
,
731 struct renderonly
*ro
)
733 struct etna_screen
*screen
= CALLOC_STRUCT(etna_screen
);
734 struct pipe_screen
*pscreen
;
740 pscreen
= &screen
->base
;
743 screen
->ro
= renderonly_dup(ro
);
746 DBG("could not create renderonly object");
750 etna_mesa_debug
= debug_get_option_etna_mesa_debug();
752 /* FIXME: Disable tile status for stability at the moment */
753 etna_mesa_debug
|= ETNA_DBG_NO_TS
;
755 screen
->pipe
= etna_pipe_new(gpu
, ETNA_PIPE_3D
);
757 DBG("could not create 3d pipe");
761 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_MODEL
, &val
)) {
762 DBG("could not get ETNA_GPU_MODEL");
767 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REVISION
, &val
)) {
768 DBG("could not get ETNA_GPU_REVISION");
771 screen
->revision
= val
;
773 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_0
, &val
)) {
774 DBG("could not get ETNA_GPU_FEATURES_0");
777 screen
->features
[0] = val
;
779 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_1
, &val
)) {
780 DBG("could not get ETNA_GPU_FEATURES_1");
783 screen
->features
[1] = val
;
785 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_2
, &val
)) {
786 DBG("could not get ETNA_GPU_FEATURES_2");
789 screen
->features
[2] = val
;
791 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_3
, &val
)) {
792 DBG("could not get ETNA_GPU_FEATURES_3");
795 screen
->features
[3] = val
;
797 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_4
, &val
)) {
798 DBG("could not get ETNA_GPU_FEATURES_4");
801 screen
->features
[4] = val
;
803 if (!etna_get_specs(screen
))
806 pscreen
->destroy
= etna_screen_destroy
;
807 pscreen
->get_param
= etna_screen_get_param
;
808 pscreen
->get_paramf
= etna_screen_get_paramf
;
809 pscreen
->get_shader_param
= etna_screen_get_shader_param
;
811 pscreen
->get_name
= etna_screen_get_name
;
812 pscreen
->get_vendor
= etna_screen_get_vendor
;
813 pscreen
->get_device_vendor
= etna_screen_get_device_vendor
;
815 pscreen
->get_timestamp
= etna_screen_get_timestamp
;
816 pscreen
->context_create
= etna_context_create
;
817 pscreen
->is_format_supported
= etna_screen_is_format_supported
;
819 etna_fence_screen_init(pscreen
);
820 etna_query_screen_init(pscreen
);
821 etna_resource_screen_init(pscreen
);
823 slab_create_parent(&screen
->transfer_pool
, sizeof(struct etna_transfer
), 16);
828 etna_screen_destroy(pscreen
);