src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/hash_table.h"
  42 #include "util/os_time.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_screen.h"
  46 #include "util/u_string.h"
  47
  48 #include "state_tracker/drm_driver.h"
  49
  50 #include "drm-uapi/drm_fourcc.h"
  51
  52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  53 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  54 #define ETNA_DRM_VERSION_PERFMON       ETNA_DRM_VERSION(1, 2)
  55
  56 static const struct debug_named_value debug_options[] = {
  57    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  58    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  59    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  60    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  61    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  62    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  63    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  64    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  65    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  66    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  67    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
  68    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  69    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  70    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  71    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  72    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  73    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  74    {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
  75    {"nir",            ETNA_DBG_NIR, "use new NIR compiler"},
  76    DEBUG_NAMED_VALUE_END
  77 };
  78
  79 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  80 int etna_mesa_debug = 0;
  81
  82 static void
  83 etna_screen_destroy(struct pipe_screen *pscreen)
  84 {
  85    struct etna_screen *screen = etna_screen(pscreen);
  86
  87    _mesa_set_destroy(screen->used_resources, NULL);
  88    mtx_destroy(&screen->lock);
  89
  90    if (screen->perfmon)
  91       etna_perfmon_del(screen->perfmon);
  92
  93    if (screen->pipe)
  94       etna_pipe_del(screen->pipe);
  95
  96    if (screen->gpu)
  97       etna_gpu_del(screen->gpu);
  98
  99    if (screen->ro)
 100       FREE(screen->ro);
 101
 102    if (screen->dev)
 103       etna_device_del(screen->dev);
 104
 105    FREE(screen);
 106 }
 107
 108 static const char *
 109 etna_screen_get_name(struct pipe_screen *pscreen)
 110 {
 111    struct etna_screen *priv = etna_screen(pscreen);
 112    static char buffer[128];
 113
 114    snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 115             priv->revision);
 116
 117    return buffer;
 118 }
 119
 120 static const char *
 121 etna_screen_get_vendor(struct pipe_screen *pscreen)
 122 {
 123    return "etnaviv";
 124 }
 125
 126 static const char *
 127 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 128 {
 129    return "Vivante";
 130 }
 131
 132 static int
 133 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 134 {
 135    struct etna_screen *screen = etna_screen(pscreen);
 136
 137    switch (param) {
 138    /* Supported features (boolean caps). */
 139    case PIPE_CAP_ANISOTROPIC_FILTER:
 140    case PIPE_CAP_POINT_SPRITE:
 141    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 142    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 143    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 144    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 145    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 146    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 147    case PIPE_CAP_TEXTURE_BARRIER:
 148    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 149    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 150    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 151    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 152    case PIPE_CAP_TGSI_TEXCOORD:
 153    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 154    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 155       return 1;
 156    case PIPE_CAP_NATIVE_FENCE_FD:
 157       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 158    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 159    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: /* note: not integer */
 160       return DBG_ENABLED(ETNA_DBG_NIR);
 161    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 162       return 0;
 163
 164    /* Memory */
 165    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 166       return 256;
 167    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 168       return 4; /* XXX could easily be supported */
 169
 170    case PIPE_CAP_NPOT_TEXTURES:
 171       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 172                       NON_POWER_OF_TWO); */
 173
 174    case PIPE_CAP_TEXTURE_SWIZZLE:
 175    case PIPE_CAP_PRIMITIVE_RESTART:
 176       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 177
 178    /* Unsupported features. */
 179    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 180    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 181    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 182       return 0;
 183
 184    /* Stream output. */
 185    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 186    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 187       return 0;
 188
 189    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 190       return 128;
 191    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 192       return 255;
 193
 194    /* Texturing. */
 195    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 196    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */
 197       return screen->specs.max_texture_size;
 198    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 199    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 200    {
 201       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 202       assert(log2_max_tex_size > 0);
 203       return log2_max_tex_size;
 204    }
 205
 206    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 207    case PIPE_CAP_MIN_TEXEL_OFFSET:
 208       return -8;
 209    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 210    case PIPE_CAP_MAX_TEXEL_OFFSET:
 211       return 7;
 212    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 213       return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
 214
 215    /* Timer queries. */
 216    case PIPE_CAP_OCCLUSION_QUERY:
 217       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 218    case PIPE_CAP_QUERY_TIMESTAMP:
 219       return 1;
 220
 221    /* Preferences */
 222    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 223       return 0;
 224
 225    case PIPE_CAP_MAX_VARYINGS:
 226       return screen->specs.max_varyings;
 227
 228    case PIPE_CAP_PCI_GROUP:
 229    case PIPE_CAP_PCI_BUS:
 230    case PIPE_CAP_PCI_DEVICE:
 231    case PIPE_CAP_PCI_FUNCTION:
 232       return 0;
 233    case PIPE_CAP_ACCELERATED:
 234       return 1;
 235    case PIPE_CAP_VIDEO_MEMORY:
 236       return 0;
 237    case PIPE_CAP_UMA:
 238       return 1;
 239    default:
 240       return u_pipe_screen_get_param_defaults(pscreen, param);
 241    }
 242 }
 243
 244 static float
 245 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 246 {
 247    struct etna_screen *screen = etna_screen(pscreen);
 248
 249    switch (param) {
 250    case PIPE_CAPF_MAX_LINE_WIDTH:
 251    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 252    case PIPE_CAPF_MAX_POINT_WIDTH:
 253    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 254       return 8192.0f;
 255    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 256       return 16.0f;
 257    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 258       return util_last_bit(screen->specs.max_texture_size);
 259    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 260    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 261    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 262       return 0.0f;
 263    }
 264
 265    debug_printf("unknown paramf %d", param);
 266    return 0;
 267 }
 268
 269 static int
 270 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 271                              enum pipe_shader_type shader,
 272                              enum pipe_shader_cap param)
 273 {
 274    struct etna_screen *screen = etna_screen(pscreen);
 275
 276    switch (shader) {
 277    case PIPE_SHADER_FRAGMENT:
 278    case PIPE_SHADER_VERTEX:
 279       break;
 280    case PIPE_SHADER_COMPUTE:
 281    case PIPE_SHADER_GEOMETRY:
 282    case PIPE_SHADER_TESS_CTRL:
 283    case PIPE_SHADER_TESS_EVAL:
 284       return 0;
 285    default:
 286       DBG("unknown shader type %d", shader);
 287       return 0;
 288    }
 289
 290    switch (param) {
 291    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 292    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 293    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 294    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 295       return ETNA_MAX_TOKENS;
 296    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 297       return ETNA_MAX_DEPTH; /* XXX */
 298    case PIPE_SHADER_CAP_MAX_INPUTS:
 299       /* Maximum number of inputs for the vertex shader is the number
 300        * of vertex elements - each element defines one vertex shader
 301        * input register.  For the fragment shader, this is the number
 302        * of varyings. */
 303       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 304                                             : screen->specs.vertex_max_elements;
 305    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 306       return 16; /* see VIVS_VS_OUTPUT */
 307    case PIPE_SHADER_CAP_MAX_TEMPS:
 308       return 64; /* Max native temporaries. */
 309    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 310       return 1;
 311    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 312       return 1;
 313    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 314    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 315    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 316    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 317       return 1;
 318    case PIPE_SHADER_CAP_SUBROUTINES:
 319       return 0;
 320    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 321       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 322    case PIPE_SHADER_CAP_INTEGERS:
 323    case PIPE_SHADER_CAP_INT64_ATOMICS:
 324    case PIPE_SHADER_CAP_FP16:
 325       return 0;
 326    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 327    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 328       return shader == PIPE_SHADER_FRAGMENT
 329                 ? screen->specs.fragment_sampler_count
 330                 : screen->specs.vertex_sampler_count;
 331    case PIPE_SHADER_CAP_PREFERRED_IR:
 332       return DBG_ENABLED(ETNA_DBG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 333    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 334       return 4096;
 335    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 336    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 337    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 338    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 339    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 340       return false;
 341    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 342       return 0;
 343    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 344       return 32;
 345    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 346    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 347    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 348    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 349    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 350    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 351    case PIPE_SHADER_CAP_SCALAR_ISA:
 352       return 0;
 353    }
 354
 355    debug_printf("unknown shader param %d", param);
 356    return 0;
 357 }
 358
 359 static uint64_t
 360 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 361 {
 362    return os_time_get_nano();
 363 }
 364
 365 static bool
 366 gpu_supports_texture_target(struct etna_screen *screen,
 367                             enum pipe_texture_target target)
 368 {
 369    if (target == PIPE_TEXTURE_CUBE_ARRAY)
 370       return false;
 371
 372    /* pre-halti has no array/3D */
 373    if (screen->specs.halti < 0 &&
 374        (target == PIPE_TEXTURE_1D_ARRAY ||
 375         target == PIPE_TEXTURE_2D_ARRAY ||
 376         target == PIPE_TEXTURE_3D))
 377       return false;
 378
 379    return true;
 380 }
 381
 382 static bool
 383 gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
 384                             enum pipe_format format)
 385 {
 386    bool supported = true;
 387
 388    if (fmt == TEXTURE_FORMAT_ETC1)
 389       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 390
 391    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 392       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 393
 394    if (util_format_is_srgb(format))
 395       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 396
 397    if (fmt & EXT_FORMAT)
 398       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 399
 400    if (fmt & ASTC_FORMAT) {
 401       supported = screen->specs.tex_astc;
 402    }
 403
 404    if (!supported)
 405       return false;
 406
 407    if (texture_format_needs_swiz(format))
 408       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 409
 410    return true;
 411 }
 412
 413 static bool
 414 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 415                                 enum pipe_format format,
 416                                 enum pipe_texture_target target,
 417                                 unsigned sample_count,
 418                                 unsigned storage_sample_count,
 419                                 unsigned usage)
 420 {
 421    struct etna_screen *screen = etna_screen(pscreen);
 422    unsigned allowed = 0;
 423
 424    if (!gpu_supports_texture_target(screen, target))
 425       return false;
 426
 427    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 428       return false;
 429
 430    if (usage & PIPE_BIND_RENDER_TARGET) {
 431       /* if render target, must be RS-supported format */
 432       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 433          /* Validate MSAA; number of samples must be allowed, and render target
 434           * must have MSAA'able format. */
 435          if (sample_count > 1) {
 436             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 437                 translate_ts_format(format) != ETNA_NO_MATCH) {
 438                allowed |= PIPE_BIND_RENDER_TARGET;
 439             }
 440          } else {
 441             allowed |= PIPE_BIND_RENDER_TARGET;
 442          }
 443       }
 444    }
 445
 446    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 447       if (translate_depth_format(format) != ETNA_NO_MATCH)
 448          allowed |= PIPE_BIND_DEPTH_STENCIL;
 449    }
 450
 451    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 452       uint32_t fmt = translate_texture_format(format);
 453
 454       if (!gpu_supports_texture_format(screen, fmt, format))
 455          fmt = ETNA_NO_MATCH;
 456
 457       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 458          allowed |= PIPE_BIND_SAMPLER_VIEW;
 459    }
 460
 461    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 462       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 463          allowed |= PIPE_BIND_VERTEX_BUFFER;
 464    }
 465
 466    if (usage & PIPE_BIND_INDEX_BUFFER) {
 467       /* must be supported index format */
 468       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 469           (format == PIPE_FORMAT_I32_UINT &&
 470            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 471          allowed |= PIPE_BIND_INDEX_BUFFER;
 472       }
 473    }
 474
 475    /* Always allowed */
 476    allowed |=
 477       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 478
 479    if (usage != allowed) {
 480       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 481           "usage=%x, allowed=%x",
 482           util_format_name(format), target, sample_count, usage, allowed);
 483    }
 484
 485    return usage == allowed;
 486 }
 487
 488 const uint64_t supported_modifiers[] = {
 489    DRM_FORMAT_MOD_LINEAR,
 490    DRM_FORMAT_MOD_VIVANTE_TILED,
 491    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 492    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 493    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 494 };
 495
 496 static void
 497 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 498                                    enum pipe_format format, int max,
 499                                    uint64_t *modifiers,
 500                                    unsigned int *external_only, int *count)
 501 {
 502    struct etna_screen *screen = etna_screen(pscreen);
 503    int i, num_modifiers = 0;
 504
 505    if (max > ARRAY_SIZE(supported_modifiers))
 506       max = ARRAY_SIZE(supported_modifiers);
 507
 508    if (!max) {
 509       modifiers = NULL;
 510       max = ARRAY_SIZE(supported_modifiers);
 511    }
 512
 513    for (i = 0; num_modifiers < max; i++) {
 514       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 515       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 516           i >= 3)
 517          break;
 518
 519       if (modifiers)
 520          modifiers[num_modifiers] = supported_modifiers[i];
 521       if (external_only)
 522          external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
 523       num_modifiers++;
 524    }
 525
 526    *count = num_modifiers;
 527 }
 528
 529 static void
 530 etna_determine_uniform_limits(struct etna_screen *screen)
 531 {
 532    /* from QueryShaderCaps in kernel driver */
 533    if (screen->model < chipModel_GC4000) {
 534       screen->specs.max_vs_uniforms = 168;
 535       screen->specs.max_ps_uniforms = 64;
 536    } else {
 537       screen->specs.max_vs_uniforms = 256;
 538       screen->specs.max_ps_uniforms = 256;
 539    }
 540 }
 541
 542 static bool
 543 etna_get_specs(struct etna_screen *screen)
 544 {
 545    uint64_t val;
 546    uint32_t instruction_count;
 547
 548    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 549       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 550       goto fail;
 551    }
 552    instruction_count = val;
 553
 554    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 555                           &val)) {
 556       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 557       goto fail;
 558    }
 559    screen->specs.vertex_output_buffer_size = val;
 560
 561    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 562       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 563       goto fail;
 564    }
 565    screen->specs.vertex_cache_size = val;
 566
 567    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 568       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 569       goto fail;
 570    }
 571    screen->specs.shader_core_count = val;
 572
 573    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 574       DBG("could not get ETNA_GPU_STREAM_COUNT");
 575       goto fail;
 576    }
 577    screen->specs.stream_count = val;
 578
 579    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 580       DBG("could not get ETNA_GPU_REGISTER_MAX");
 581       goto fail;
 582    }
 583    screen->specs.max_registers = val;
 584
 585    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 586       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 587       goto fail;
 588    }
 589    screen->specs.pixel_pipes = val;
 590
 591    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 592       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 593       goto fail;
 594    }
 595    if (val == 0) {
 596       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 597       val = 168;
 598    }
 599    screen->specs.num_constants = val;
 600
 601    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 602     * description of the differences. */
 603    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 604       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 605    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 606       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 607    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 608       screen->specs.halti = 3; /* None? */
 609    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 610       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 611    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 612       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 613    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 614       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 615    else
 616       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 617    if (screen->specs.halti >= 0)
 618       DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
 619    else
 620       DBG("etnaviv: GPU arch: pre-HALTI");
 621
 622    screen->specs.can_supertile =
 623       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 624    screen->specs.bits_per_tile =
 625       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 626    screen->specs.ts_clear_value =
 627       VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE)  ? 0xffffffff :
 628       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 :
 629                                                              0x11111111;
 630
 631
 632    /* vertex and fragment samplers live in one address space */
 633    screen->specs.vertex_sampler_offset = 8;
 634    screen->specs.fragment_sampler_count = 8;
 635    screen->specs.vertex_sampler_count = 4;
 636    screen->specs.vs_need_z_div =
 637       screen->model < 0x1000 && screen->model != 0x880;
 638    screen->specs.has_sin_cos_sqrt =
 639       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 640    screen->specs.has_sign_floor_ceil =
 641       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 642    screen->specs.has_shader_range_registers =
 643       screen->model >= 0x1000 || screen->model == 0x880;
 644    screen->specs.npot_tex_any_wrap =
 645       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 646    screen->specs.has_new_transcendentals =
 647       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 648    screen->specs.has_halti2_instructions =
 649       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 650    screen->specs.v4_compression =
 651       VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
 652
 653    if (screen->specs.halti >= 5) {
 654       /* GC7000 - this core must load shaders from memory. */
 655       screen->specs.vs_offset = 0;
 656       screen->specs.ps_offset = 0;
 657       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 658       screen->specs.has_icache = true;
 659    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 660       /* GC3000 - this core is capable of loading shaders from
 661        * memory. It can also run shaders from registers, as a fallback, but
 662        * "max_instructions" does not have the correct value. It has place for
 663        * 2*256 instructions just like GC2000, but the offsets are slightly
 664        * different.
 665        */
 666       screen->specs.vs_offset = 0xC000;
 667       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 668        * this mirror for writing PS instructions, probably safest to do the
 669        * same.
 670        */
 671       screen->specs.ps_offset = 0x8000 + 0x1000;
 672       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 673       screen->specs.has_icache = true;
 674    } else {
 675       if (instruction_count > 256) { /* unified instruction memory? */
 676          screen->specs.vs_offset = 0xC000;
 677          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 678          screen->specs.max_instructions = 256;
 679       } else {
 680          screen->specs.vs_offset = 0x4000;
 681          screen->specs.ps_offset = 0x6000;
 682          screen->specs.max_instructions = instruction_count / 2;
 683       }
 684       screen->specs.has_icache = false;
 685    }
 686
 687    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 688       screen->specs.max_varyings = 12;
 689       screen->specs.vertex_max_elements = 16;
 690    } else {
 691       screen->specs.max_varyings = 8;
 692       /* Etna_viv documentation seems confused over the correct value
 693        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 694        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 695       screen->specs.vertex_max_elements = 10;
 696    }
 697
 698    /* Etna_viv documentation does not indicate where varyings above 8 are
 699     * stored. Moreover, if we are passed more than 8 varyings, we will
 700     * walk off the end of some arrays. Limit the maximum number of varyings. */
 701    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 702       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 703
 704    etna_determine_uniform_limits(screen);
 705
 706    if (screen->specs.halti >= 5) {
 707       screen->specs.has_unified_uniforms = true;
 708       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 709       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 710    } else if (screen->specs.halti >= 1) {
 711       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 712       */
 713       screen->specs.has_unified_uniforms = true;
 714       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 715       /* hardcode PS uniforms to start after end of VS uniforms -
 716        * for more flexibility this offset could be variable based on the
 717        * shader.
 718        */
 719       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 720    } else {
 721       screen->specs.has_unified_uniforms = false;
 722       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 723       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 724    }
 725
 726    screen->specs.max_texture_size =
 727       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 728    screen->specs.max_rendertarget_size =
 729       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 730
 731    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 732    if (screen->specs.single_buffer)
 733       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
 734
 735    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 736
 737    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 738
 739    return true;
 740
 741 fail:
 742    return false;
 743 }
 744
 745 struct etna_bo *
 746 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 747                            struct winsys_handle *whandle, unsigned *out_stride)
 748 {
 749    struct etna_screen *screen = etna_screen(pscreen);
 750    struct etna_bo *bo;
 751
 752    if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 753       bo = etna_bo_from_name(screen->dev, whandle->handle);
 754    } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 755       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 756    } else {
 757       DBG("Attempt to import unsupported handle type %d", whandle->type);
 758       return NULL;
 759    }
 760
 761    if (!bo) {
 762       DBG("ref name 0x%08x failed", whandle->handle);
 763       return NULL;
 764    }
 765
 766    *out_stride = whandle->stride;
 767
 768    return bo;
 769 }
 770
 771 static const void *
 772 etna_get_compiler_options(struct pipe_screen *pscreen,
 773                           enum pipe_shader_ir ir, unsigned shader)
 774 {
 775    return &etna_screen(pscreen)->options;
 776 }
 777
 778 struct pipe_screen *
 779 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 780                    struct renderonly *ro)
 781 {
 782    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 783    struct pipe_screen *pscreen;
 784    drmVersionPtr version;
 785    uint64_t val;
 786
 787    if (!screen)
 788       return NULL;
 789
 790    pscreen = &screen->base;
 791    screen->dev = dev;
 792    screen->gpu = gpu;
 793    screen->ro = renderonly_dup(ro);
 794    screen->refcnt = 1;
 795
 796    if (!screen->ro) {
 797       DBG("could not create renderonly object");
 798       goto fail;
 799    }
 800
 801    version = drmGetVersion(screen->ro->gpu_fd);
 802    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 803                                           version->version_minor);
 804    drmFreeVersion(version);
 805
 806    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 807
 808    /* Disable autodisable for correct rendering with TS */
 809    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 810
 811    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 812    if (!screen->pipe) {
 813       DBG("could not create 3d pipe");
 814       goto fail;
 815    }
 816
 817    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 818       DBG("could not get ETNA_GPU_MODEL");
 819       goto fail;
 820    }
 821    screen->model = val;
 822
 823    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 824       DBG("could not get ETNA_GPU_REVISION");
 825       goto fail;
 826    }
 827    screen->revision = val;
 828
 829    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 830       DBG("could not get ETNA_GPU_FEATURES_0");
 831       goto fail;
 832    }
 833    screen->features[0] = val;
 834
 835    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 836       DBG("could not get ETNA_GPU_FEATURES_1");
 837       goto fail;
 838    }
 839    screen->features[1] = val;
 840
 841    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 842       DBG("could not get ETNA_GPU_FEATURES_2");
 843       goto fail;
 844    }
 845    screen->features[2] = val;
 846
 847    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 848       DBG("could not get ETNA_GPU_FEATURES_3");
 849       goto fail;
 850    }
 851    screen->features[3] = val;
 852
 853    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 854       DBG("could not get ETNA_GPU_FEATURES_4");
 855       goto fail;
 856    }
 857    screen->features[4] = val;
 858
 859    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 860       DBG("could not get ETNA_GPU_FEATURES_5");
 861       goto fail;
 862    }
 863    screen->features[5] = val;
 864
 865    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 866       DBG("could not get ETNA_GPU_FEATURES_6");
 867       goto fail;
 868    }
 869    screen->features[6] = val;
 870
 871    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) {
 872       DBG("could not get ETNA_GPU_FEATURES_7");
 873       goto fail;
 874    }
 875    screen->features[7] = val;
 876
 877    if (!etna_get_specs(screen))
 878       goto fail;
 879
 880    screen->options = (nir_shader_compiler_options) {
 881       .lower_fpow = true,
 882       .lower_sub = true,
 883       .lower_ftrunc = true,
 884       .fuse_ffma = true,
 885       .lower_bitops = true,
 886       .lower_all_io_to_temps = true,
 887       .vertex_id_zero_based = true,
 888       .lower_flrp32 = true,
 889       .lower_fmod = true,
 890       .lower_vector_cmp = true,
 891       .lower_fdph = true,
 892       .lower_fdiv = true, /* !screen->specs.has_new_transcendentals */
 893       .lower_fsign = !screen->specs.has_sign_floor_ceil,
 894       .lower_ffloor = !screen->specs.has_sign_floor_ceil,
 895       .lower_fceil = !screen->specs.has_sign_floor_ceil,
 896       .lower_fsqrt = !screen->specs.has_sin_cos_sqrt,
 897       .lower_sincos = !screen->specs.has_sin_cos_sqrt,
 898    };
 899
 900    /* apply debug options that disable individual features */
 901    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 902       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 903    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 904          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 905    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 906       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 907    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 908       screen->specs.can_supertile = 0;
 909    if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
 910       screen->specs.single_buffer = 0;
 911
 912    pscreen->destroy = etna_screen_destroy;
 913    pscreen->get_param = etna_screen_get_param;
 914    pscreen->get_paramf = etna_screen_get_paramf;
 915    pscreen->get_shader_param = etna_screen_get_shader_param;
 916    pscreen->get_compiler_options = etna_get_compiler_options;
 917
 918    pscreen->get_name = etna_screen_get_name;
 919    pscreen->get_vendor = etna_screen_get_vendor;
 920    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 921
 922    pscreen->get_timestamp = etna_screen_get_timestamp;
 923    pscreen->context_create = etna_context_create;
 924    pscreen->is_format_supported = etna_screen_is_format_supported;
 925    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 926
 927    etna_fence_screen_init(pscreen);
 928    etna_query_screen_init(pscreen);
 929    etna_resource_screen_init(pscreen);
 930
 931    util_dynarray_init(&screen->supported_pm_queries, NULL);
 932    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 933
 934    if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
 935       etna_pm_query_setup(screen);
 936
 937    mtx_init(&screen->lock, mtx_recursive);
 938    screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer,
 939                                              _mesa_key_pointer_equal);
 940    if (!screen->used_resources)
 941       goto fail2;
 942
 943    return pscreen;
 944
 945 fail2:
 946    mtx_destroy(&screen->lock);
 947 fail:
 948    etna_screen_destroy(pscreen);
 949    return NULL;
 950 }