src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 static const struct debug_named_value debug_options[] = {
  49    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  50    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  51    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  52    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  53    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  54    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  55    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  56    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  57    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  58    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  59    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  60    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  61    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  62    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  63    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  64    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  65    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  66    DEBUG_NAMED_VALUE_END
  67 };
  68
  69 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  70 int etna_mesa_debug = 0;
  71
  72 static void
  73 etna_screen_destroy(struct pipe_screen *pscreen)
  74 {
  75    struct etna_screen *screen = etna_screen(pscreen);
  76
  77    if (screen->pipe)
  78       etna_pipe_del(screen->pipe);
  79
  80    if (screen->gpu)
  81       etna_gpu_del(screen->gpu);
  82
  83    if (screen->ro)
  84       FREE(screen->ro);
  85
  86    if (screen->dev)
  87       etna_device_del(screen->dev);
  88
  89    FREE(screen);
  90 }
  91
  92 static const char *
  93 etna_screen_get_name(struct pipe_screen *pscreen)
  94 {
  95    struct etna_screen *priv = etna_screen(pscreen);
  96    static char buffer[128];
  97
  98    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
  99                  priv->revision);
 100
 101    return buffer;
 102 }
 103
 104 static const char *
 105 etna_screen_get_vendor(struct pipe_screen *pscreen)
 106 {
 107    return "etnaviv";
 108 }
 109
 110 static const char *
 111 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 112 {
 113    return "Vivante";
 114 }
 115
 116 static int
 117 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 118 {
 119    struct etna_screen *screen = etna_screen(pscreen);
 120
 121    switch (param) {
 122    /* Supported features (boolean caps). */
 123    case PIPE_CAP_TWO_SIDED_STENCIL:
 124    case PIPE_CAP_ANISOTROPIC_FILTER:
 125    case PIPE_CAP_POINT_SPRITE:
 126    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 127    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 128    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 129    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 130    case PIPE_CAP_SM3:
 131    case PIPE_CAP_TEXTURE_BARRIER:
 132    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 133    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 134    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 135    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 136    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 137    case PIPE_CAP_TGSI_TEXCOORD:
 138    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 139       return 1;
 140
 141    /* Memory */
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 145       return 4; /* XXX could easily be supported */
 146    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 147       return 120;
 148
 149    case PIPE_CAP_NPOT_TEXTURES:
 150       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 151                       NON_POWER_OF_TWO); */
 152
 153    case PIPE_CAP_PRIMITIVE_RESTART:
 154       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 155
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 158                                     ENDIANNESS_CONFIG) */
 159
 160    /* Unsupported features. */
 161    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 162    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
 163    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 164    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 165    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 166    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 167    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 168    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 169    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 170    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 172    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 173    case PIPE_CAP_INDEP_BLEND_ENABLE:
 174    case PIPE_CAP_INDEP_BLEND_FUNC:
 175    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 177    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 178    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 179    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 180    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 181    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 182    case PIPE_CAP_USER_VERTEX_BUFFERS:
 183    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 184    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 185    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 186    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 187    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 188    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189    case PIPE_CAP_TEXTURE_GATHER_SM5:
 190    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 191    case PIPE_CAP_FAKE_SW_MSAA:
 192    case PIPE_CAP_TEXTURE_QUERY_LOD:
 193    case PIPE_CAP_SAMPLE_SHADING:
 194    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 195    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 196    case PIPE_CAP_DRAW_INDIRECT:
 197    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 198    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 199    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 200    case PIPE_CAP_CLIP_HALFZ:
 201    case PIPE_CAP_VERTEXID_NOBASE:
 202    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 203    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 204    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 205    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 206    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 207    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 208    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 209    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 210    case PIPE_CAP_TGSI_TXQS:
 211    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 212    case PIPE_CAP_SHAREABLE_SHADERS:
 213    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 214    case PIPE_CAP_CLEAR_TEXTURE:
 215    case PIPE_CAP_DRAW_PARAMETERS:
 216    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 217    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 218    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 219    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 220    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 221    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 222    case PIPE_CAP_INVALIDATE_BUFFER:
 223    case PIPE_CAP_GENERATE_MIPMAP:
 224    case PIPE_CAP_STRING_MARKER:
 225    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 227    case PIPE_CAP_QUERY_MEMORY_INFO:
 228    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 229    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 230    case PIPE_CAP_CULL_DISTANCE:
 231    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 232    case PIPE_CAP_TGSI_VOTE:
 233    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 234    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 235    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 236    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 237    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 238    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 239    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 240    case PIPE_CAP_NATIVE_FENCE_FD:
 241    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 242    case PIPE_CAP_TGSI_FS_FBFETCH:
 243    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 244    case PIPE_CAP_DOUBLES:
 245    case PIPE_CAP_INT64:
 246    case PIPE_CAP_INT64_DIVMOD:
 247       return 0;
 248
 249    /* Stream output. */
 250    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 251    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 252    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 253    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 254       return 0;
 255
 256    /* Geometry shader output, unsupported. */
 257    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 258    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 259    case PIPE_CAP_MAX_VERTEX_STREAMS:
 260       return 0;
 261
 262    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 263       return 128;
 264
 265    /* Texturing. */
 266    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 267    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 268    {
 269       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 270       assert(log2_max_tex_size > 0);
 271       return log2_max_tex_size;
 272    }
 273    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 274       return 5;
 275    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 276       return 0;
 277    case PIPE_CAP_CUBE_MAP_ARRAY:
 278       return 0;
 279    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 280    case PIPE_CAP_MIN_TEXEL_OFFSET:
 281       return -8;
 282    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 283    case PIPE_CAP_MAX_TEXEL_OFFSET:
 284       return 7;
 285    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 286       return 0;
 287    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 288       return 65536;
 289
 290    /* Render targets. */
 291    case PIPE_CAP_MAX_RENDER_TARGETS:
 292       return 1;
 293
 294    /* Viewports and scissors. */
 295    case PIPE_CAP_MAX_VIEWPORTS:
 296       return 1;
 297
 298    /* Timer queries. */
 299    case PIPE_CAP_QUERY_TIME_ELAPSED:
 300    case PIPE_CAP_OCCLUSION_QUERY:
 301       return 0;
 302    case PIPE_CAP_QUERY_TIMESTAMP:
 303       return 1;
 304    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 305       return 0;
 306
 307    /* Preferences */
 308    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 309       return 0;
 310
 311    case PIPE_CAP_PCI_GROUP:
 312    case PIPE_CAP_PCI_BUS:
 313    case PIPE_CAP_PCI_DEVICE:
 314    case PIPE_CAP_PCI_FUNCTION:
 315       return 0;
 316    case PIPE_CAP_VENDOR_ID:
 317    case PIPE_CAP_DEVICE_ID:
 318       return 0xFFFFFFFF;
 319    case PIPE_CAP_ACCELERATED:
 320       return 1;
 321    case PIPE_CAP_VIDEO_MEMORY:
 322       return 0;
 323    case PIPE_CAP_UMA:
 324       return 1;
 325    }
 326
 327    debug_printf("unknown param %d", param);
 328    return 0;
 329 }
 330
 331 static float
 332 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 333 {
 334    switch (param) {
 335    case PIPE_CAPF_MAX_LINE_WIDTH:
 336    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 337    case PIPE_CAPF_MAX_POINT_WIDTH:
 338    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 339       return 8192.0f;
 340    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 341       return 16.0f;
 342    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 343       return 16.0f;
 344    case PIPE_CAPF_GUARD_BAND_LEFT:
 345    case PIPE_CAPF_GUARD_BAND_TOP:
 346    case PIPE_CAPF_GUARD_BAND_RIGHT:
 347    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 348       return 0.0f;
 349    }
 350
 351    debug_printf("unknown paramf %d", param);
 352    return 0;
 353 }
 354
 355 static int
 356 etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 357                              enum pipe_shader_cap param)
 358 {
 359    struct etna_screen *screen = etna_screen(pscreen);
 360
 361    switch (shader) {
 362    case PIPE_SHADER_FRAGMENT:
 363    case PIPE_SHADER_VERTEX:
 364       break;
 365    case PIPE_SHADER_COMPUTE:
 366    case PIPE_SHADER_GEOMETRY:
 367    case PIPE_SHADER_TESS_CTRL:
 368    case PIPE_SHADER_TESS_EVAL:
 369       return 0;
 370    default:
 371       DBG("unknown shader type %d", shader);
 372       return 0;
 373    }
 374
 375    switch (param) {
 376    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 377    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 378    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 379    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 380       return ETNA_MAX_TOKENS;
 381    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 382       return ETNA_MAX_DEPTH; /* XXX */
 383    case PIPE_SHADER_CAP_MAX_INPUTS:
 384       /* Maximum number of inputs for the vertex shader is the number
 385        * of vertex elements - each element defines one vertex shader
 386        * input register.  For the fragment shader, this is the number
 387        * of varyings. */
 388       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 389                                             : screen->specs.vertex_max_elements;
 390    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 391       return 16; /* see VIVS_VS_OUTPUT */
 392    case PIPE_SHADER_CAP_MAX_TEMPS:
 393       return 64; /* Max native temporaries. */
 394    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 395       return 1;
 396    case PIPE_SHADER_CAP_MAX_PREDS:
 397       return 0; /* nothing uses this */
 398    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 399       return 1;
 400    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 401    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 402    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 403    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 404       return 1;
 405    case PIPE_SHADER_CAP_SUBROUTINES:
 406       return 0;
 407    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 408       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 409    case PIPE_SHADER_CAP_INTEGERS:
 410       return 0;
 411    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 412    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 413       return shader == PIPE_SHADER_FRAGMENT
 414                 ? screen->specs.fragment_sampler_count
 415                 : screen->specs.vertex_sampler_count;
 416    case PIPE_SHADER_CAP_PREFERRED_IR:
 417       return PIPE_SHADER_IR_TGSI;
 418    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 419       return 4096;
 420    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 421    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 422    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 423    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 424       return false;
 425    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 426       return 0;
 427    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 428       return 32;
 429    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 430    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 431    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 432       return 0;
 433    }
 434
 435    debug_printf("unknown shader param %d", param);
 436    return 0;
 437 }
 438
 439 static uint64_t
 440 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 441 {
 442    return os_time_get_nano();
 443 }
 444
 445 static bool
 446 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
 447 {
 448    if (fmt == TEXTURE_FORMAT_ETC1)
 449       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 450
 451    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 452       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 453
 454    return true;
 455 }
 456
 457 static boolean
 458 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 459                                 enum pipe_format format,
 460                                 enum pipe_texture_target target,
 461                                 unsigned sample_count, unsigned usage)
 462 {
 463    struct etna_screen *screen = etna_screen(pscreen);
 464    unsigned allowed = 0;
 465
 466    if (target != PIPE_BUFFER &&
 467        target != PIPE_TEXTURE_1D &&
 468        target != PIPE_TEXTURE_2D &&
 469        target != PIPE_TEXTURE_3D &&
 470        target != PIPE_TEXTURE_CUBE &&
 471        target != PIPE_TEXTURE_RECT)
 472       return FALSE;
 473
 474    if (usage & PIPE_BIND_RENDER_TARGET) {
 475       /* If render target, must be RS-supported format that is not rb swapped.
 476        * Exposing rb swapped (or other swizzled) formats for rendering would
 477        * involve swizzing in the pixel shader.
 478        */
 479       if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) {
 480          /* Validate MSAA; number of samples must be allowed, and render target
 481           * must have MSAA'able format. */
 482          if (sample_count > 1) {
 483             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 484                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 485                allowed |= PIPE_BIND_RENDER_TARGET;
 486             }
 487          } else {
 488             allowed |= PIPE_BIND_RENDER_TARGET;
 489          }
 490       }
 491    }
 492
 493    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 494       if (translate_depth_format(format) != ETNA_NO_MATCH)
 495          allowed |= PIPE_BIND_DEPTH_STENCIL;
 496    }
 497
 498    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 499       uint32_t fmt = translate_texture_format(format);
 500
 501       if (!gpu_supports_texure_format(screen, fmt))
 502          fmt = ETNA_NO_MATCH;
 503
 504       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 505          allowed |= PIPE_BIND_SAMPLER_VIEW;
 506    }
 507
 508    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 509       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 510          allowed |= PIPE_BIND_VERTEX_BUFFER;
 511    }
 512
 513    if (usage & PIPE_BIND_INDEX_BUFFER) {
 514       /* must be supported index format */
 515       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 516           (format == PIPE_FORMAT_I32_UINT &&
 517            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 518          allowed |= PIPE_BIND_INDEX_BUFFER;
 519       }
 520    }
 521
 522    /* Always allowed */
 523    allowed |=
 524       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 525
 526    if (usage != allowed) {
 527       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 528           "usage=%x, allowed=%x",
 529           util_format_name(format), target, sample_count, usage, allowed);
 530    }
 531
 532    return usage == allowed;
 533 }
 534
 535 static boolean
 536 etna_get_specs(struct etna_screen *screen)
 537 {
 538    uint64_t val;
 539    uint32_t instruction_count;
 540
 541    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 542       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 543       goto fail;
 544    }
 545    instruction_count = val;
 546
 547    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 548                           &val)) {
 549       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 550       goto fail;
 551    }
 552    screen->specs.vertex_output_buffer_size = val;
 553
 554    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 555       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 556       goto fail;
 557    }
 558    screen->specs.vertex_cache_size = val;
 559
 560    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 561       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 562       goto fail;
 563    }
 564    screen->specs.shader_core_count = val;
 565
 566    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 567       DBG("could not get ETNA_GPU_STREAM_COUNT");
 568       goto fail;
 569    }
 570    screen->specs.stream_count = val;
 571
 572    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 573       DBG("could not get ETNA_GPU_REGISTER_MAX");
 574       goto fail;
 575    }
 576    screen->specs.max_registers = val;
 577
 578    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 579       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 580       goto fail;
 581    }
 582    screen->specs.pixel_pipes = val;
 583
 584    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 585       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 586       goto fail;
 587    }
 588    if (val == 0) {
 589       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 590       val = 168;
 591    }
 592    screen->specs.num_constants = val;
 593
 594    screen->specs.can_supertile =
 595       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 596    screen->specs.bits_per_tile =
 597       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 598    screen->specs.ts_clear_value =
 599       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 600                                                            : 0x11111111;
 601
 602    /* vertex and fragment samplers live in one address space */
 603    screen->specs.vertex_sampler_offset = 8;
 604    screen->specs.fragment_sampler_count = 8;
 605    screen->specs.vertex_sampler_count = 4;
 606    screen->specs.vs_need_z_div =
 607       screen->model < 0x1000 && screen->model != 0x880;
 608    screen->specs.has_sin_cos_sqrt =
 609       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 610    screen->specs.has_sign_floor_ceil =
 611       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 612    screen->specs.has_shader_range_registers =
 613       screen->model >= 0x1000 || screen->model == 0x880;
 614    screen->specs.npot_tex_any_wrap =
 615       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 616    screen->specs.has_new_sin_cos =
 617       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 618
 619    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 620       /* GC3000 - this core is capable of loading shaders from
 621        * memory. It can also run shaders from registers, as a fallback, but
 622        * "max_instructions" does not have the correct value. It has place for
 623        * 2*256 instructions just like GC2000, but the offsets are slightly
 624        * different.
 625        */
 626       screen->specs.vs_offset = 0xC000;
 627       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 628        * this mirror for writing PS instructions, probably safest to do the
 629        * same.
 630        */
 631       screen->specs.ps_offset = 0x8000 + 0x1000;
 632       screen->specs.max_instructions = 256;
 633    } else {
 634       if (instruction_count > 256) { /* unified instruction memory? */
 635          screen->specs.vs_offset = 0xC000;
 636          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 637          screen->specs.max_instructions = 256;
 638       } else {
 639          screen->specs.vs_offset = 0x4000;
 640          screen->specs.ps_offset = 0x6000;
 641          screen->specs.max_instructions = instruction_count / 2;
 642       }
 643    }
 644
 645    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 646       screen->specs.max_varyings = 12;
 647       screen->specs.vertex_max_elements = 16;
 648    } else {
 649       screen->specs.max_varyings = 8;
 650       /* Etna_viv documentation seems confused over the correct value
 651        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 652        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 653       screen->specs.vertex_max_elements = 10;
 654    }
 655
 656    /* Etna_viv documentation does not indicate where varyings above 8 are
 657     * stored. Moreover, if we are passed more than 8 varyings, we will
 658     * walk off the end of some arrays. Limit the maximum number of varyings. */
 659    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 660       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 661
 662    /* from QueryShaderCaps in kernel driver */
 663    if (screen->model < chipModel_GC4000) {
 664       screen->specs.max_vs_uniforms = 168;
 665       screen->specs.max_ps_uniforms = 64;
 666    } else {
 667       screen->specs.max_vs_uniforms = 256;
 668       screen->specs.max_ps_uniforms = 256;
 669    }
 670
 671    screen->specs.max_texture_size =
 672       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 673    screen->specs.max_rendertarget_size =
 674       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 675
 676    return true;
 677
 678 fail:
 679    return false;
 680 }
 681
 682 boolean
 683 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
 684                           unsigned stride, struct winsys_handle *whandle)
 685 {
 686    whandle->stride = stride;
 687
 688    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 689       return etna_bo_get_name(bo, &whandle->handle) == 0;
 690    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 691       whandle->handle = etna_bo_handle(bo);
 692       return TRUE;
 693    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 694       whandle->handle = etna_bo_dmabuf(bo);
 695       return TRUE;
 696    } else {
 697       return FALSE;
 698    }
 699 }
 700
 701 struct etna_bo *
 702 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 703                            struct winsys_handle *whandle, unsigned *out_stride)
 704 {
 705    struct etna_screen *screen = etna_screen(pscreen);
 706    struct etna_bo *bo;
 707
 708    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 709       bo = etna_bo_from_name(screen->dev, whandle->handle);
 710    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 711       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 712    } else {
 713       DBG("Attempt to import unsupported handle type %d", whandle->type);
 714       return NULL;
 715    }
 716
 717    if (!bo) {
 718       DBG("ref name 0x%08x failed", whandle->handle);
 719       return NULL;
 720    }
 721
 722    *out_stride = whandle->stride;
 723
 724    return bo;
 725 }
 726
 727 struct pipe_screen *
 728 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 729                    struct renderonly *ro)
 730 {
 731    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 732    struct pipe_screen *pscreen;
 733    uint64_t val;
 734
 735    if (!screen)
 736       return NULL;
 737
 738    pscreen = &screen->base;
 739    screen->dev = dev;
 740    screen->gpu = gpu;
 741    screen->ro = renderonly_dup(ro);
 742
 743    if (!screen->ro) {
 744       DBG("could not create renderonly object");
 745       goto fail;
 746    }
 747
 748    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 749
 750    /* FIXME: Disable tile status for stability at the moment */
 751    etna_mesa_debug |= ETNA_DBG_NO_TS;
 752
 753    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 754    if (!screen->pipe) {
 755       DBG("could not create 3d pipe");
 756       goto fail;
 757    }
 758
 759    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 760       DBG("could not get ETNA_GPU_MODEL");
 761       goto fail;
 762    }
 763    screen->model = val;
 764
 765    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 766       DBG("could not get ETNA_GPU_REVISION");
 767       goto fail;
 768    }
 769    screen->revision = val;
 770
 771    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 772       DBG("could not get ETNA_GPU_FEATURES_0");
 773       goto fail;
 774    }
 775    screen->features[0] = val;
 776
 777    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 778       DBG("could not get ETNA_GPU_FEATURES_1");
 779       goto fail;
 780    }
 781    screen->features[1] = val;
 782
 783    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 784       DBG("could not get ETNA_GPU_FEATURES_2");
 785       goto fail;
 786    }
 787    screen->features[2] = val;
 788
 789    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 790       DBG("could not get ETNA_GPU_FEATURES_3");
 791       goto fail;
 792    }
 793    screen->features[3] = val;
 794
 795    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 796       DBG("could not get ETNA_GPU_FEATURES_4");
 797       goto fail;
 798    }
 799    screen->features[4] = val;
 800
 801    if (!etna_get_specs(screen))
 802       goto fail;
 803
 804    pscreen->destroy = etna_screen_destroy;
 805    pscreen->get_param = etna_screen_get_param;
 806    pscreen->get_paramf = etna_screen_get_paramf;
 807    pscreen->get_shader_param = etna_screen_get_shader_param;
 808
 809    pscreen->get_name = etna_screen_get_name;
 810    pscreen->get_vendor = etna_screen_get_vendor;
 811    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 812
 813    pscreen->get_timestamp = etna_screen_get_timestamp;
 814    pscreen->context_create = etna_context_create;
 815    pscreen->is_format_supported = etna_screen_is_format_supported;
 816
 817    etna_fence_screen_init(pscreen);
 818    etna_query_screen_init(pscreen);
 819    etna_resource_screen_init(pscreen);
 820
 821    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 822
 823    return pscreen;
 824
 825 fail:
 826    etna_screen_destroy(pscreen);
 827    return NULL;
 828 }