2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
28 #include "etnaviv_screen.h"
30 #include "hw/common.xml.h"
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
48 #include "state_tracker/drm_driver.h"
50 #include "drm-uapi/drm_fourcc.h"
52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
53 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
54 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
56 static const struct debug_named_value debug_options
[] = {
57 {"dbg_msgs", ETNA_DBG_MSGS
, "Print debug messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS
, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS
, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS
, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS
, "Print linker messages"},
62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS
, "Dump shaders"},
63 {"no_ts", ETNA_DBG_NO_TS
, "Disable TS"},
64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE
, "Disable autodisable"},
65 {"no_supertile", ETNA_DBG_NO_SUPERTILE
, "Disable supertiles"},
66 {"no_early_z", ETNA_DBG_NO_EARLY_Z
, "Disable early z"},
67 {"cflush_all", ETNA_DBG_CFLUSH_ALL
, "Flush every cache before state update"},
68 {"msaa2x", ETNA_DBG_MSAA_2X
, "Force 2x msaa"},
69 {"msaa4x", ETNA_DBG_MSAA_4X
, "Force 4x msaa"},
70 {"flush_all", ETNA_DBG_FLUSH_ALL
, "Flush after every rendered primitive"},
71 {"zero", ETNA_DBG_ZERO
, "Zero all resources after allocation"},
72 {"draw_stall", ETNA_DBG_DRAW_STALL
, "Stall FE/PE after each rendered primitive"},
73 {"shaderdb", ETNA_DBG_SHADERDB
, "Enable shaderdb output"},
74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF
, "Disable single buffer feature"},
75 {"nir", ETNA_DBG_NIR
, "use new NIR compiler"},
76 {"deqp", ETNA_DBG_DEQP
, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */
80 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug
, "ETNA_MESA_DEBUG", debug_options
, 0)
81 int etna_mesa_debug
= 0;
84 etna_screen_destroy(struct pipe_screen
*pscreen
)
86 struct etna_screen
*screen
= etna_screen(pscreen
);
89 etna_perfmon_del(screen
->perfmon
);
92 etna_pipe_del(screen
->pipe
);
95 etna_gpu_del(screen
->gpu
);
101 etna_device_del(screen
->dev
);
107 etna_screen_get_name(struct pipe_screen
*pscreen
)
109 struct etna_screen
*priv
= etna_screen(pscreen
);
110 static char buffer
[128];
112 snprintf(buffer
, sizeof(buffer
), "Vivante GC%x rev %04x", priv
->model
,
119 etna_screen_get_vendor(struct pipe_screen
*pscreen
)
125 etna_screen_get_device_vendor(struct pipe_screen
*pscreen
)
131 etna_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
133 struct etna_screen
*screen
= etna_screen(pscreen
);
136 /* Supported features (boolean caps). */
137 case PIPE_CAP_ANISOTROPIC_FILTER
:
138 case PIPE_CAP_POINT_SPRITE
:
139 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
140 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
141 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
142 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
143 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
144 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
145 case PIPE_CAP_TEXTURE_BARRIER
:
146 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
147 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
148 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
149 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
150 case PIPE_CAP_TGSI_TEXCOORD
:
151 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
152 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
153 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
155 case PIPE_CAP_NATIVE_FENCE_FD
:
156 return screen
->drm_version
>= ETNA_DRM_VERSION_FENCE_FD
;
157 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
158 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
: /* note: not integer */
159 return DBG_ENABLED(ETNA_DBG_NIR
);
160 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
164 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
166 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
167 return 4; /* XXX could easily be supported */
169 case PIPE_CAP_NPOT_TEXTURES
:
170 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
171 NON_POWER_OF_TWO); */
173 case PIPE_CAP_TEXTURE_SWIZZLE
:
174 case PIPE_CAP_PRIMITIVE_RESTART
:
175 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
177 /* Unsupported features. */
178 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
179 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
180 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
184 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
185 return DBG_ENABLED(ETNA_DBG_DEQP
) ? 4 : 0;
186 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
187 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
190 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
192 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
194 case PIPE_CAP_MAX_VERTEX_BUFFERS
:
195 return screen
->specs
.stream_count
;
196 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
197 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
201 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
202 return DBG_ENABLED(ETNA_DBG_NIR
) && screen
->specs
.halti
>= 2;
203 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
204 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
: /* TODO: verify */
205 return screen
->specs
.max_texture_size
;
206 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
207 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
209 int log2_max_tex_size
= util_last_bit(screen
->specs
.max_texture_size
);
210 assert(log2_max_tex_size
> 0);
211 return log2_max_tex_size
;
214 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
215 case PIPE_CAP_MIN_TEXEL_OFFSET
:
217 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
218 case PIPE_CAP_MAX_TEXEL_OFFSET
:
220 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
221 return VIV_FEATURE(screen
, chipMinorFeatures2
, SEAMLESS_CUBE_MAP
);
224 case PIPE_CAP_OCCLUSION_QUERY
:
225 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
226 case PIPE_CAP_QUERY_TIMESTAMP
:
230 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
233 case PIPE_CAP_MAX_VARYINGS
:
234 return screen
->specs
.max_varyings
;
236 case PIPE_CAP_PCI_GROUP
:
237 case PIPE_CAP_PCI_BUS
:
238 case PIPE_CAP_PCI_DEVICE
:
239 case PIPE_CAP_PCI_FUNCTION
:
241 case PIPE_CAP_ACCELERATED
:
243 case PIPE_CAP_VIDEO_MEMORY
:
248 return u_pipe_screen_get_param_defaults(pscreen
, param
);
253 etna_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
255 struct etna_screen
*screen
= etna_screen(pscreen
);
258 case PIPE_CAPF_MAX_LINE_WIDTH
:
259 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
260 case PIPE_CAPF_MAX_POINT_WIDTH
:
261 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
263 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
265 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
266 return util_last_bit(screen
->specs
.max_texture_size
);
267 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
268 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
269 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
273 debug_printf("unknown paramf %d", param
);
278 etna_screen_get_shader_param(struct pipe_screen
*pscreen
,
279 enum pipe_shader_type shader
,
280 enum pipe_shader_cap param
)
282 struct etna_screen
*screen
= etna_screen(pscreen
);
283 bool ubo_enable
= screen
->specs
.halti
>= 2 && DBG_ENABLED(ETNA_DBG_NIR
);
285 if (DBG_ENABLED(ETNA_DBG_DEQP
))
289 case PIPE_SHADER_FRAGMENT
:
290 case PIPE_SHADER_VERTEX
:
292 case PIPE_SHADER_COMPUTE
:
293 case PIPE_SHADER_GEOMETRY
:
294 case PIPE_SHADER_TESS_CTRL
:
295 case PIPE_SHADER_TESS_EVAL
:
298 DBG("unknown shader type %d", shader
);
303 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
304 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
305 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
306 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
307 return ETNA_MAX_TOKENS
;
308 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
309 return ETNA_MAX_DEPTH
; /* XXX */
310 case PIPE_SHADER_CAP_MAX_INPUTS
:
311 /* Maximum number of inputs for the vertex shader is the number
312 * of vertex elements - each element defines one vertex shader
313 * input register. For the fragment shader, this is the number
315 return shader
== PIPE_SHADER_FRAGMENT
? screen
->specs
.max_varyings
316 : screen
->specs
.vertex_max_elements
;
317 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
318 return 16; /* see VIVS_VS_OUTPUT */
319 case PIPE_SHADER_CAP_MAX_TEMPS
:
320 return 64; /* Max native temporaries. */
321 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
322 return ubo_enable
? ETNA_MAX_CONST_BUF
: 1;
323 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
325 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
326 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
327 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
328 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
330 case PIPE_SHADER_CAP_SUBROUTINES
:
332 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
333 return VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
334 case PIPE_SHADER_CAP_INT64_ATOMICS
:
335 case PIPE_SHADER_CAP_FP16
:
337 case PIPE_SHADER_CAP_INTEGERS
:
338 return DBG_ENABLED(ETNA_DBG_NIR
) && screen
->specs
.halti
>= 2;
339 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
340 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
341 return shader
== PIPE_SHADER_FRAGMENT
342 ? screen
->specs
.fragment_sampler_count
343 : screen
->specs
.vertex_sampler_count
;
344 case PIPE_SHADER_CAP_PREFERRED_IR
:
345 return DBG_ENABLED(ETNA_DBG_NIR
) ? PIPE_SHADER_IR_NIR
: PIPE_SHADER_IR_TGSI
;
346 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
348 return 16384; /* 16384 so state tracker enables UBOs */
349 return shader
== PIPE_SHADER_FRAGMENT
350 ? screen
->specs
.max_ps_uniforms
* sizeof(float[4])
351 : screen
->specs
.max_vs_uniforms
* sizeof(float[4]);
352 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
353 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
354 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
355 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
356 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
358 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
360 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
362 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
363 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
364 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
365 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
366 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
367 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
371 debug_printf("unknown shader param %d", param
);
376 etna_screen_get_timestamp(struct pipe_screen
*pscreen
)
378 return os_time_get_nano();
382 gpu_supports_texture_target(struct etna_screen
*screen
,
383 enum pipe_texture_target target
)
385 if (target
== PIPE_TEXTURE_CUBE_ARRAY
)
388 /* pre-halti has no array/3D */
389 if (screen
->specs
.halti
< 0 &&
390 (target
== PIPE_TEXTURE_1D_ARRAY
||
391 target
== PIPE_TEXTURE_2D_ARRAY
||
392 target
== PIPE_TEXTURE_3D
))
399 gpu_supports_texture_format(struct etna_screen
*screen
, uint32_t fmt
,
400 enum pipe_format format
)
402 bool supported
= true;
404 if (fmt
== TEXTURE_FORMAT_ETC1
)
405 supported
= VIV_FEATURE(screen
, chipFeatures
, ETC1_TEXTURE_COMPRESSION
);
407 if (fmt
>= TEXTURE_FORMAT_DXT1
&& fmt
<= TEXTURE_FORMAT_DXT4_DXT5
)
408 supported
= VIV_FEATURE(screen
, chipFeatures
, DXT_TEXTURE_COMPRESSION
);
410 if (util_format_is_srgb(format
))
411 supported
= VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
413 if (fmt
& EXT_FORMAT
)
414 supported
= VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
416 if (fmt
& ASTC_FORMAT
) {
417 supported
= screen
->specs
.tex_astc
;
420 if (util_format_is_snorm(format
))
421 supported
= VIV_FEATURE(screen
, chipMinorFeatures2
, HALTI1
);
423 if (format
!= PIPE_FORMAT_S8_UINT_Z24_UNORM
&&
424 (util_format_is_pure_integer(format
) || util_format_is_float(format
)))
425 supported
= VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
431 if (texture_format_needs_swiz(format
))
432 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
438 gpu_supports_render_format(struct etna_screen
*screen
, enum pipe_format format
,
439 unsigned sample_count
)
441 const uint32_t fmt
= translate_pe_format(format
);
443 if (fmt
== ETNA_NO_MATCH
)
446 /* Validate MSAA; number of samples must be allowed, and render target
447 * must have MSAA'able format. */
448 if (sample_count
> 1) {
449 if (!VIV_FEATURE(screen
, chipFeatures
, MSAA
))
451 if (!translate_samples_to_xyscale(sample_count
, NULL
, NULL
))
453 if (translate_ts_format(format
) == ETNA_NO_MATCH
)
457 if (format
== PIPE_FORMAT_R8_UNORM
)
458 return VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
);
460 /* figure out 8bpp RS clear to enable these formats */
461 if (format
== PIPE_FORMAT_R8_SINT
|| format
== PIPE_FORMAT_R8_UINT
)
462 return VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
);
464 if (util_format_is_srgb(format
))
465 return VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI3
);
467 if (util_format_is_pure_integer(format
) || util_format_is_float(format
))
468 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
470 if (format
== PIPE_FORMAT_R8G8_UNORM
)
471 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
473 /* any other extended format is HALTI0 (only R10G10B10A2?) */
474 if (fmt
>= PE_FORMAT_R16F
)
475 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
481 gpu_supports_vertex_format(struct etna_screen
*screen
, enum pipe_format format
)
483 if (translate_vertex_format_type(format
) == ETNA_NO_MATCH
)
486 if (util_format_is_pure_integer(format
))
487 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
493 etna_screen_is_format_supported(struct pipe_screen
*pscreen
,
494 enum pipe_format format
,
495 enum pipe_texture_target target
,
496 unsigned sample_count
,
497 unsigned storage_sample_count
,
500 struct etna_screen
*screen
= etna_screen(pscreen
);
501 unsigned allowed
= 0;
503 if (!gpu_supports_texture_target(screen
, target
))
506 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
509 if (usage
& PIPE_BIND_RENDER_TARGET
) {
510 if (gpu_supports_render_format(screen
, format
, sample_count
))
511 allowed
|= PIPE_BIND_RENDER_TARGET
;
514 if (usage
& PIPE_BIND_DEPTH_STENCIL
) {
515 if (translate_depth_format(format
) != ETNA_NO_MATCH
)
516 allowed
|= PIPE_BIND_DEPTH_STENCIL
;
519 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
520 uint32_t fmt
= translate_texture_format(format
);
522 if (!gpu_supports_texture_format(screen
, fmt
, format
))
525 if (sample_count
< 2 && fmt
!= ETNA_NO_MATCH
)
526 allowed
|= PIPE_BIND_SAMPLER_VIEW
;
529 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
530 if (gpu_supports_vertex_format(screen
, format
))
531 allowed
|= PIPE_BIND_VERTEX_BUFFER
;
534 if (usage
& PIPE_BIND_INDEX_BUFFER
) {
535 /* must be supported index format */
536 if (format
== PIPE_FORMAT_I8_UINT
|| format
== PIPE_FORMAT_I16_UINT
||
537 (format
== PIPE_FORMAT_I32_UINT
&&
538 VIV_FEATURE(screen
, chipFeatures
, 32_BIT_INDICES
))) {
539 allowed
|= PIPE_BIND_INDEX_BUFFER
;
545 usage
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
);
547 if (usage
!= allowed
) {
548 DBG("not supported: format=%s, target=%d, sample_count=%d, "
549 "usage=%x, allowed=%x",
550 util_format_name(format
), target
, sample_count
, usage
, allowed
);
553 return usage
== allowed
;
556 const uint64_t supported_modifiers
[] = {
557 DRM_FORMAT_MOD_LINEAR
,
558 DRM_FORMAT_MOD_VIVANTE_TILED
,
559 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED
,
560 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED
,
561 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED
,
565 etna_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
566 enum pipe_format format
, int max
,
568 unsigned int *external_only
, int *count
)
570 struct etna_screen
*screen
= etna_screen(pscreen
);
571 int i
, num_modifiers
= 0;
573 if (max
> ARRAY_SIZE(supported_modifiers
))
574 max
= ARRAY_SIZE(supported_modifiers
);
578 max
= ARRAY_SIZE(supported_modifiers
);
581 for (i
= 0; num_modifiers
< max
; i
++) {
582 /* don't advertise split tiled formats on single pipe/buffer GPUs */
583 if ((screen
->specs
.pixel_pipes
== 1 || screen
->specs
.single_buffer
) &&
588 modifiers
[num_modifiers
] = supported_modifiers
[i
];
590 external_only
[num_modifiers
] = util_format_is_yuv(format
) ? 1 : 0;
594 *count
= num_modifiers
;
598 etna_determine_uniform_limits(struct etna_screen
*screen
)
600 /* values for the non unified case are taken from
601 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
602 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
604 if (screen
->model
== chipModel_GC2000
&&
605 (screen
->revision
== 0x5118 || screen
->revision
== 0x5140)) {
606 screen
->specs
.max_vs_uniforms
= 256;
607 screen
->specs
.max_ps_uniforms
= 64;
608 } else if (screen
->specs
.num_constants
== 320) {
609 screen
->specs
.max_vs_uniforms
= 256;
610 screen
->specs
.max_ps_uniforms
= 64;
611 } else if (screen
->specs
.num_constants
> 256 &&
612 screen
->model
== chipModel_GC1000
) {
613 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
614 screen
->specs
.max_vs_uniforms
= 256;
615 screen
->specs
.max_ps_uniforms
= 64;
616 } else if (screen
->specs
.num_constants
> 256) {
617 screen
->specs
.max_vs_uniforms
= 256;
618 screen
->specs
.max_ps_uniforms
= 256;
619 } else if (screen
->specs
.num_constants
== 256) {
620 screen
->specs
.max_vs_uniforms
= 256;
621 screen
->specs
.max_ps_uniforms
= 256;
623 screen
->specs
.max_vs_uniforms
= 168;
624 screen
->specs
.max_ps_uniforms
= 64;
629 etna_get_specs(struct etna_screen
*screen
)
632 uint32_t instruction_count
;
634 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_INSTRUCTION_COUNT
, &val
)) {
635 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
638 instruction_count
= val
;
640 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE
,
642 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
645 screen
->specs
.vertex_output_buffer_size
= val
;
647 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_CACHE_SIZE
, &val
)) {
648 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
651 screen
->specs
.vertex_cache_size
= val
;
653 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_SHADER_CORE_COUNT
, &val
)) {
654 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
657 screen
->specs
.shader_core_count
= val
;
659 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_STREAM_COUNT
, &val
)) {
660 DBG("could not get ETNA_GPU_STREAM_COUNT");
663 screen
->specs
.stream_count
= val
;
665 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REGISTER_MAX
, &val
)) {
666 DBG("could not get ETNA_GPU_REGISTER_MAX");
669 screen
->specs
.max_registers
= val
;
671 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_PIXEL_PIPES
, &val
)) {
672 DBG("could not get ETNA_GPU_PIXEL_PIPES");
675 screen
->specs
.pixel_pipes
= val
;
677 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_NUM_CONSTANTS
, &val
)) {
678 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
682 fprintf(stderr
, "Warning: zero num constants (update kernel?)\n");
685 screen
->specs
.num_constants
= val
;
687 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
688 * description of the differences. */
689 if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
))
690 screen
->specs
.halti
= 5; /* New GC7000/GC8x00 */
691 else if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI4
))
692 screen
->specs
.halti
= 4; /* Old GC7000/GC7400 */
693 else if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI3
))
694 screen
->specs
.halti
= 3; /* None? */
695 else if (VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
))
696 screen
->specs
.halti
= 2; /* GC2500/GC3000/GC5000/GC6400 */
697 else if (VIV_FEATURE(screen
, chipMinorFeatures2
, HALTI1
))
698 screen
->specs
.halti
= 1; /* GC900/GC4000/GC7000UL */
699 else if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
))
700 screen
->specs
.halti
= 0; /* GC880/GC2000/GC7000TM */
702 screen
->specs
.halti
= -1; /* GC7000nanolite / pre-GC2000 except GC880 */
703 if (screen
->specs
.halti
>= 0)
704 DBG("etnaviv: GPU arch: HALTI%d", screen
->specs
.halti
);
706 DBG("etnaviv: GPU arch: pre-HALTI");
708 screen
->specs
.can_supertile
=
709 VIV_FEATURE(screen
, chipMinorFeatures0
, SUPER_TILED
);
710 screen
->specs
.bits_per_tile
=
711 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 2 : 4;
712 screen
->specs
.ts_clear_value
=
713 VIV_FEATURE(screen
, chipMinorFeatures5
, BLT_ENGINE
) ? 0xffffffff :
714 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 0x55555555 :
718 /* vertex and fragment samplers live in one address space */
719 screen
->specs
.vertex_sampler_offset
= 8;
720 screen
->specs
.fragment_sampler_count
= 8;
721 screen
->specs
.vertex_sampler_count
= 4;
723 if (screen
->model
== 0x400)
724 screen
->specs
.vertex_sampler_count
= 0;
726 screen
->specs
.vs_need_z_div
=
727 screen
->model
< 0x1000 && screen
->model
!= 0x880;
728 screen
->specs
.has_sin_cos_sqrt
=
729 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
730 screen
->specs
.has_sign_floor_ceil
=
731 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SIGN_FLOOR_CEIL
);
732 screen
->specs
.has_shader_range_registers
=
733 screen
->model
>= 0x1000 || screen
->model
== 0x880;
734 screen
->specs
.npot_tex_any_wrap
=
735 VIV_FEATURE(screen
, chipMinorFeatures1
, NON_POWER_OF_TWO
);
736 screen
->specs
.has_new_transcendentals
=
737 VIV_FEATURE(screen
, chipMinorFeatures3
, HAS_FAST_TRANSCENDENTALS
);
738 screen
->specs
.has_halti2_instructions
=
739 VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
740 screen
->specs
.v4_compression
=
741 VIV_FEATURE(screen
, chipMinorFeatures6
, V4_COMPRESSION
);
743 if (screen
->specs
.halti
>= 5) {
744 /* GC7000 - this core must load shaders from memory. */
745 screen
->specs
.vs_offset
= 0;
746 screen
->specs
.ps_offset
= 0;
747 screen
->specs
.max_instructions
= 0; /* Do not program shaders manually */
748 screen
->specs
.has_icache
= true;
749 } else if (VIV_FEATURE(screen
, chipMinorFeatures3
, INSTRUCTION_CACHE
)) {
750 /* GC3000 - this core is capable of loading shaders from
751 * memory. It can also run shaders from registers, as a fallback, but
752 * "max_instructions" does not have the correct value. It has place for
753 * 2*256 instructions just like GC2000, but the offsets are slightly
756 screen
->specs
.vs_offset
= 0xC000;
757 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
758 * this mirror for writing PS instructions, probably safest to do the
761 screen
->specs
.ps_offset
= 0x8000 + 0x1000;
762 screen
->specs
.max_instructions
= 256; /* maximum number instructions for non-icache use */
763 screen
->specs
.has_icache
= true;
765 if (instruction_count
> 256) { /* unified instruction memory? */
766 screen
->specs
.vs_offset
= 0xC000;
767 screen
->specs
.ps_offset
= 0xD000; /* like vivante driver */
768 screen
->specs
.max_instructions
= 256;
770 screen
->specs
.vs_offset
= 0x4000;
771 screen
->specs
.ps_offset
= 0x6000;
772 screen
->specs
.max_instructions
= instruction_count
/ 2;
774 screen
->specs
.has_icache
= false;
777 if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
)) {
778 screen
->specs
.max_varyings
= 12;
779 screen
->specs
.vertex_max_elements
= 16;
781 screen
->specs
.max_varyings
= 8;
782 /* Etna_viv documentation seems confused over the correct value
783 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
784 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
785 screen
->specs
.vertex_max_elements
= 10;
788 /* Etna_viv documentation does not indicate where varyings above 8 are
789 * stored. Moreover, if we are passed more than 8 varyings, we will
790 * walk off the end of some arrays. Limit the maximum number of varyings. */
791 if (screen
->specs
.max_varyings
> ETNA_NUM_VARYINGS
)
792 screen
->specs
.max_varyings
= ETNA_NUM_VARYINGS
;
794 etna_determine_uniform_limits(screen
);
796 if (screen
->specs
.halti
>= 5) {
797 screen
->specs
.has_unified_uniforms
= true;
798 screen
->specs
.vs_uniforms_offset
= VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
799 screen
->specs
.ps_uniforms_offset
= VIVS_SH_HALTI5_UNIFORMS(screen
->specs
.max_vs_uniforms
*4);
800 } else if (screen
->specs
.halti
>= 1) {
801 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
803 screen
->specs
.has_unified_uniforms
= true;
804 screen
->specs
.vs_uniforms_offset
= VIVS_SH_UNIFORMS(0);
805 /* hardcode PS uniforms to start after end of VS uniforms -
806 * for more flexibility this offset could be variable based on the
809 screen
->specs
.ps_uniforms_offset
= VIVS_SH_UNIFORMS(screen
->specs
.max_vs_uniforms
*4);
811 screen
->specs
.has_unified_uniforms
= false;
812 screen
->specs
.vs_uniforms_offset
= VIVS_VS_UNIFORMS(0);
813 screen
->specs
.ps_uniforms_offset
= VIVS_PS_UNIFORMS(0);
816 screen
->specs
.max_texture_size
=
817 VIV_FEATURE(screen
, chipMinorFeatures0
, TEXTURE_8K
) ? 8192 : 2048;
818 screen
->specs
.max_rendertarget_size
=
819 VIV_FEATURE(screen
, chipMinorFeatures0
, RENDERTARGET_8K
) ? 8192 : 2048;
821 screen
->specs
.single_buffer
= VIV_FEATURE(screen
, chipMinorFeatures4
, SINGLE_BUFFER
);
822 if (screen
->specs
.single_buffer
)
823 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen
->specs
.pixel_pipes
);
825 screen
->specs
.tex_astc
= VIV_FEATURE(screen
, chipMinorFeatures4
, TEXTURE_ASTC
) &&
826 !VIV_FEATURE(screen
, chipMinorFeatures6
, NO_ASTC
);
828 screen
->specs
.use_blt
= VIV_FEATURE(screen
, chipMinorFeatures5
, BLT_ENGINE
);
837 etna_screen_bo_from_handle(struct pipe_screen
*pscreen
,
838 struct winsys_handle
*whandle
, unsigned *out_stride
)
840 struct etna_screen
*screen
= etna_screen(pscreen
);
843 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
844 bo
= etna_bo_from_name(screen
->dev
, whandle
->handle
);
845 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
846 bo
= etna_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
848 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
853 DBG("ref name 0x%08x failed", whandle
->handle
);
857 *out_stride
= whandle
->stride
;
863 etna_get_compiler_options(struct pipe_screen
*pscreen
,
864 enum pipe_shader_ir ir
, unsigned shader
)
866 return &etna_screen(pscreen
)->options
;
870 etna_screen_create(struct etna_device
*dev
, struct etna_gpu
*gpu
,
871 struct renderonly
*ro
)
873 struct etna_screen
*screen
= CALLOC_STRUCT(etna_screen
);
874 struct pipe_screen
*pscreen
;
875 drmVersionPtr version
;
881 pscreen
= &screen
->base
;
884 screen
->ro
= renderonly_dup(ro
);
888 DBG("could not create renderonly object");
892 version
= drmGetVersion(screen
->ro
->gpu_fd
);
893 screen
->drm_version
= ETNA_DRM_VERSION(version
->version_major
,
894 version
->version_minor
);
895 drmFreeVersion(version
);
897 etna_mesa_debug
= debug_get_option_etna_mesa_debug();
899 /* Disable autodisable for correct rendering with TS */
900 etna_mesa_debug
|= ETNA_DBG_NO_AUTODISABLE
;
902 screen
->pipe
= etna_pipe_new(gpu
, ETNA_PIPE_3D
);
904 DBG("could not create 3d pipe");
908 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_MODEL
, &val
)) {
909 DBG("could not get ETNA_GPU_MODEL");
914 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REVISION
, &val
)) {
915 DBG("could not get ETNA_GPU_REVISION");
918 screen
->revision
= val
;
920 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_0
, &val
)) {
921 DBG("could not get ETNA_GPU_FEATURES_0");
924 screen
->features
[0] = val
;
926 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_1
, &val
)) {
927 DBG("could not get ETNA_GPU_FEATURES_1");
930 screen
->features
[1] = val
;
932 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_2
, &val
)) {
933 DBG("could not get ETNA_GPU_FEATURES_2");
936 screen
->features
[2] = val
;
938 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_3
, &val
)) {
939 DBG("could not get ETNA_GPU_FEATURES_3");
942 screen
->features
[3] = val
;
944 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_4
, &val
)) {
945 DBG("could not get ETNA_GPU_FEATURES_4");
948 screen
->features
[4] = val
;
950 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_5
, &val
)) {
951 DBG("could not get ETNA_GPU_FEATURES_5");
954 screen
->features
[5] = val
;
956 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_6
, &val
)) {
957 DBG("could not get ETNA_GPU_FEATURES_6");
960 screen
->features
[6] = val
;
962 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_7
, &val
)) {
963 DBG("could not get ETNA_GPU_FEATURES_7");
966 screen
->features
[7] = val
;
968 if (!etna_get_specs(screen
))
971 if (screen
->specs
.halti
>= 5 && !etnaviv_device_softpin_capable(dev
)) {
972 DBG("halti5 requires softpin");
976 screen
->options
= (nir_shader_compiler_options
) {
979 .lower_ftrunc
= true,
981 .lower_bitops
= true,
982 .lower_all_io_to_temps
= true,
983 .vertex_id_zero_based
= true,
984 .lower_flrp32
= true,
986 .lower_vector_cmp
= true,
988 .lower_fdiv
= true, /* !screen->specs.has_new_transcendentals */
989 .lower_fsign
= !screen
->specs
.has_sign_floor_ceil
,
990 .lower_ffloor
= !screen
->specs
.has_sign_floor_ceil
,
991 .lower_fceil
= !screen
->specs
.has_sign_floor_ceil
,
992 .lower_fsqrt
= !screen
->specs
.has_sin_cos_sqrt
,
993 .lower_sincos
= !screen
->specs
.has_sin_cos_sqrt
,
996 /* apply debug options that disable individual features */
997 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z
))
998 screen
->features
[viv_chipFeatures
] |= chipFeatures_NO_EARLY_Z
;
999 if (DBG_ENABLED(ETNA_DBG_NO_TS
))
1000 screen
->features
[viv_chipFeatures
] &= ~chipFeatures_FAST_CLEAR
;
1001 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE
))
1002 screen
->features
[viv_chipMinorFeatures1
] &= ~chipMinorFeatures1_AUTO_DISABLE
;
1003 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE
))
1004 screen
->specs
.can_supertile
= 0;
1005 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF
))
1006 screen
->specs
.single_buffer
= 0;
1008 pscreen
->destroy
= etna_screen_destroy
;
1009 pscreen
->get_param
= etna_screen_get_param
;
1010 pscreen
->get_paramf
= etna_screen_get_paramf
;
1011 pscreen
->get_shader_param
= etna_screen_get_shader_param
;
1012 pscreen
->get_compiler_options
= etna_get_compiler_options
;
1014 pscreen
->get_name
= etna_screen_get_name
;
1015 pscreen
->get_vendor
= etna_screen_get_vendor
;
1016 pscreen
->get_device_vendor
= etna_screen_get_device_vendor
;
1018 pscreen
->get_timestamp
= etna_screen_get_timestamp
;
1019 pscreen
->context_create
= etna_context_create
;
1020 pscreen
->is_format_supported
= etna_screen_is_format_supported
;
1021 pscreen
->query_dmabuf_modifiers
= etna_screen_query_dmabuf_modifiers
;
1023 etna_fence_screen_init(pscreen
);
1024 etna_query_screen_init(pscreen
);
1025 etna_resource_screen_init(pscreen
);
1027 util_dynarray_init(&screen
->supported_pm_queries
, NULL
);
1028 slab_create_parent(&screen
->transfer_pool
, sizeof(struct etna_transfer
), 16);
1030 if (screen
->drm_version
>= ETNA_DRM_VERSION_PERFMON
)
1031 etna_pm_query_setup(screen
);
1036 etna_screen_destroy(pscreen
);