src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/hash_table.h"
  42 #include "util/os_time.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_screen.h"
  46 #include "util/u_string.h"
  47
  48 #include "state_tracker/drm_driver.h"
  49
  50 #include "drm-uapi/drm_fourcc.h"
  51
  52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  53 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  54 #define ETNA_DRM_VERSION_PERFMON       ETNA_DRM_VERSION(1, 2)
  55
  56 static const struct debug_named_value debug_options[] = {
  57    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  58    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  59    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  60    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  61    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  62    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  63    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  64    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  65    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  66    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  67    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
  68    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  69    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  70    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  71    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  72    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  73    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  74    {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
  75    {"nir",            ETNA_DBG_NIR, "use new NIR compiler"},
  76    DEBUG_NAMED_VALUE_END
  77 };
  78
  79 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  80 int etna_mesa_debug = 0;
  81
  82 static void
  83 etna_screen_destroy(struct pipe_screen *pscreen)
  84 {
  85    struct etna_screen *screen = etna_screen(pscreen);
  86
  87    _mesa_set_destroy(screen->used_resources, NULL);
  88    mtx_destroy(&screen->lock);
  89
  90    if (screen->perfmon)
  91       etna_perfmon_del(screen->perfmon);
  92
  93    if (screen->pipe)
  94       etna_pipe_del(screen->pipe);
  95
  96    if (screen->gpu)
  97       etna_gpu_del(screen->gpu);
  98
  99    if (screen->ro)
 100       FREE(screen->ro);
 101
 102    if (screen->dev)
 103       etna_device_del(screen->dev);
 104
 105    FREE(screen);
 106 }
 107
 108 static const char *
 109 etna_screen_get_name(struct pipe_screen *pscreen)
 110 {
 111    struct etna_screen *priv = etna_screen(pscreen);
 112    static char buffer[128];
 113
 114    snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 115             priv->revision);
 116
 117    return buffer;
 118 }
 119
 120 static const char *
 121 etna_screen_get_vendor(struct pipe_screen *pscreen)
 122 {
 123    return "etnaviv";
 124 }
 125
 126 static const char *
 127 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 128 {
 129    return "Vivante";
 130 }
 131
 132 static int
 133 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 134 {
 135    struct etna_screen *screen = etna_screen(pscreen);
 136
 137    switch (param) {
 138    /* Supported features (boolean caps). */
 139    case PIPE_CAP_ANISOTROPIC_FILTER:
 140    case PIPE_CAP_POINT_SPRITE:
 141    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 142    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 143    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 144    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 145    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 146    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 147    case PIPE_CAP_TEXTURE_BARRIER:
 148    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 149    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 150    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 151    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 152    case PIPE_CAP_TGSI_TEXCOORD:
 153    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 154    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 155    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 156       return 1;
 157    case PIPE_CAP_NATIVE_FENCE_FD:
 158       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 159    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 160    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: /* note: not integer */
 161       return DBG_ENABLED(ETNA_DBG_NIR);
 162    case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 163       return 0;
 164
 165    /* Memory */
 166    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 167       return 256;
 168    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 169       return 4; /* XXX could easily be supported */
 170
 171    case PIPE_CAP_NPOT_TEXTURES:
 172       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 173                       NON_POWER_OF_TWO); */
 174
 175    case PIPE_CAP_TEXTURE_SWIZZLE:
 176    case PIPE_CAP_PRIMITIVE_RESTART:
 177       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 178
 179    /* Unsupported features. */
 180    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 181    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 182    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 183       return 0;
 184
 185    /* Stream output. */
 186    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 187    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 188       return 0;
 189
 190    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 191       return 128;
 192    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 193       return 255;
 194
 195    /* Texturing. */
 196    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 197       return 0;
 198    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 199    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */
 200       return screen->specs.max_texture_size;
 201    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 202    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 203    {
 204       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 205       assert(log2_max_tex_size > 0);
 206       return log2_max_tex_size;
 207    }
 208
 209    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 210    case PIPE_CAP_MIN_TEXEL_OFFSET:
 211       return -8;
 212    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 213    case PIPE_CAP_MAX_TEXEL_OFFSET:
 214       return 7;
 215    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 216       return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
 217
 218    /* Timer queries. */
 219    case PIPE_CAP_OCCLUSION_QUERY:
 220       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 221    case PIPE_CAP_QUERY_TIMESTAMP:
 222       return 1;
 223
 224    /* Preferences */
 225    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 226       return 0;
 227
 228    case PIPE_CAP_MAX_VARYINGS:
 229       return screen->specs.max_varyings;
 230
 231    case PIPE_CAP_PCI_GROUP:
 232    case PIPE_CAP_PCI_BUS:
 233    case PIPE_CAP_PCI_DEVICE:
 234    case PIPE_CAP_PCI_FUNCTION:
 235       return 0;
 236    case PIPE_CAP_ACCELERATED:
 237       return 1;
 238    case PIPE_CAP_VIDEO_MEMORY:
 239       return 0;
 240    case PIPE_CAP_UMA:
 241       return 1;
 242    default:
 243       return u_pipe_screen_get_param_defaults(pscreen, param);
 244    }
 245 }
 246
 247 static float
 248 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 249 {
 250    struct etna_screen *screen = etna_screen(pscreen);
 251
 252    switch (param) {
 253    case PIPE_CAPF_MAX_LINE_WIDTH:
 254    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 255    case PIPE_CAPF_MAX_POINT_WIDTH:
 256    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 257       return 8192.0f;
 258    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 259       return 16.0f;
 260    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 261       return util_last_bit(screen->specs.max_texture_size);
 262    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 263    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 264    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 265       return 0.0f;
 266    }
 267
 268    debug_printf("unknown paramf %d", param);
 269    return 0;
 270 }
 271
 272 static int
 273 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 274                              enum pipe_shader_type shader,
 275                              enum pipe_shader_cap param)
 276 {
 277    struct etna_screen *screen = etna_screen(pscreen);
 278
 279    switch (shader) {
 280    case PIPE_SHADER_FRAGMENT:
 281    case PIPE_SHADER_VERTEX:
 282       break;
 283    case PIPE_SHADER_COMPUTE:
 284    case PIPE_SHADER_GEOMETRY:
 285    case PIPE_SHADER_TESS_CTRL:
 286    case PIPE_SHADER_TESS_EVAL:
 287       return 0;
 288    default:
 289       DBG("unknown shader type %d", shader);
 290       return 0;
 291    }
 292
 293    switch (param) {
 294    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 295    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 296    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 297    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 298       return ETNA_MAX_TOKENS;
 299    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 300       return ETNA_MAX_DEPTH; /* XXX */
 301    case PIPE_SHADER_CAP_MAX_INPUTS:
 302       /* Maximum number of inputs for the vertex shader is the number
 303        * of vertex elements - each element defines one vertex shader
 304        * input register.  For the fragment shader, this is the number
 305        * of varyings. */
 306       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 307                                             : screen->specs.vertex_max_elements;
 308    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 309       return 16; /* see VIVS_VS_OUTPUT */
 310    case PIPE_SHADER_CAP_MAX_TEMPS:
 311       return 64; /* Max native temporaries. */
 312    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 313       return 1;
 314    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 315       return 1;
 316    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 317    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 318    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 319    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 320       return 1;
 321    case PIPE_SHADER_CAP_SUBROUTINES:
 322       return 0;
 323    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 324       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 325    case PIPE_SHADER_CAP_INT64_ATOMICS:
 326    case PIPE_SHADER_CAP_FP16:
 327       return 0;
 328    case PIPE_SHADER_CAP_INTEGERS:
 329       return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2;
 330    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 331    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 332       return shader == PIPE_SHADER_FRAGMENT
 333                 ? screen->specs.fragment_sampler_count
 334                 : screen->specs.vertex_sampler_count;
 335    case PIPE_SHADER_CAP_PREFERRED_IR:
 336       return DBG_ENABLED(ETNA_DBG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
 337    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 338       return shader == PIPE_SHADER_FRAGMENT
 339                 ? screen->specs.max_ps_uniforms * sizeof(float[4])
 340                 : screen->specs.max_vs_uniforms * sizeof(float[4]);
 341    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 342    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 343    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 344    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 345    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 346       return false;
 347    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 348       return 0;
 349    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 350       return 32;
 351    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 352    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 353    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 354    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 355    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 356    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 357    case PIPE_SHADER_CAP_SCALAR_ISA:
 358       return 0;
 359    }
 360
 361    debug_printf("unknown shader param %d", param);
 362    return 0;
 363 }
 364
 365 static uint64_t
 366 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 367 {
 368    return os_time_get_nano();
 369 }
 370
 371 static bool
 372 gpu_supports_texture_target(struct etna_screen *screen,
 373                             enum pipe_texture_target target)
 374 {
 375    if (target == PIPE_TEXTURE_CUBE_ARRAY)
 376       return false;
 377
 378    /* pre-halti has no array/3D */
 379    if (screen->specs.halti < 0 &&
 380        (target == PIPE_TEXTURE_1D_ARRAY ||
 381         target == PIPE_TEXTURE_2D_ARRAY ||
 382         target == PIPE_TEXTURE_3D))
 383       return false;
 384
 385    return true;
 386 }
 387
 388 static bool
 389 gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
 390                             enum pipe_format format)
 391 {
 392    bool supported = true;
 393
 394    if (fmt == TEXTURE_FORMAT_ETC1)
 395       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 396
 397    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 398       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 399
 400    if (util_format_is_srgb(format))
 401       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 402
 403    if (fmt & EXT_FORMAT)
 404       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 405
 406    if (fmt & ASTC_FORMAT) {
 407       supported = screen->specs.tex_astc;
 408    }
 409
 410    if (!supported)
 411       return false;
 412
 413    if (texture_format_needs_swiz(format))
 414       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 415
 416    return true;
 417 }
 418
 419 static bool
 420 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 421                                 enum pipe_format format,
 422                                 enum pipe_texture_target target,
 423                                 unsigned sample_count,
 424                                 unsigned storage_sample_count,
 425                                 unsigned usage)
 426 {
 427    struct etna_screen *screen = etna_screen(pscreen);
 428    unsigned allowed = 0;
 429
 430    if (!gpu_supports_texture_target(screen, target))
 431       return false;
 432
 433    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 434       return false;
 435
 436    if (usage & PIPE_BIND_RENDER_TARGET) {
 437       /* if render target, must be RS-supported format */
 438       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 439          /* Validate MSAA; number of samples must be allowed, and render target
 440           * must have MSAA'able format. */
 441          if (sample_count > 1) {
 442             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 443                 translate_ts_format(format) != ETNA_NO_MATCH) {
 444                allowed |= PIPE_BIND_RENDER_TARGET;
 445             }
 446          } else {
 447             allowed |= PIPE_BIND_RENDER_TARGET;
 448          }
 449       }
 450    }
 451
 452    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 453       if (translate_depth_format(format) != ETNA_NO_MATCH)
 454          allowed |= PIPE_BIND_DEPTH_STENCIL;
 455    }
 456
 457    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 458       uint32_t fmt = translate_texture_format(format);
 459
 460       if (!gpu_supports_texture_format(screen, fmt, format))
 461          fmt = ETNA_NO_MATCH;
 462
 463       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 464          allowed |= PIPE_BIND_SAMPLER_VIEW;
 465    }
 466
 467    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 468       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 469          allowed |= PIPE_BIND_VERTEX_BUFFER;
 470    }
 471
 472    if (usage & PIPE_BIND_INDEX_BUFFER) {
 473       /* must be supported index format */
 474       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 475           (format == PIPE_FORMAT_I32_UINT &&
 476            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 477          allowed |= PIPE_BIND_INDEX_BUFFER;
 478       }
 479    }
 480
 481    /* Always allowed */
 482    allowed |=
 483       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 484
 485    if (usage != allowed) {
 486       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 487           "usage=%x, allowed=%x",
 488           util_format_name(format), target, sample_count, usage, allowed);
 489    }
 490
 491    return usage == allowed;
 492 }
 493
 494 const uint64_t supported_modifiers[] = {
 495    DRM_FORMAT_MOD_LINEAR,
 496    DRM_FORMAT_MOD_VIVANTE_TILED,
 497    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 498    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 499    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 500 };
 501
 502 static void
 503 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 504                                    enum pipe_format format, int max,
 505                                    uint64_t *modifiers,
 506                                    unsigned int *external_only, int *count)
 507 {
 508    struct etna_screen *screen = etna_screen(pscreen);
 509    int i, num_modifiers = 0;
 510
 511    if (max > ARRAY_SIZE(supported_modifiers))
 512       max = ARRAY_SIZE(supported_modifiers);
 513
 514    if (!max) {
 515       modifiers = NULL;
 516       max = ARRAY_SIZE(supported_modifiers);
 517    }
 518
 519    for (i = 0; num_modifiers < max; i++) {
 520       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 521       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 522           i >= 3)
 523          break;
 524
 525       if (modifiers)
 526          modifiers[num_modifiers] = supported_modifiers[i];
 527       if (external_only)
 528          external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
 529       num_modifiers++;
 530    }
 531
 532    *count = num_modifiers;
 533 }
 534
 535 static void
 536 etna_determine_uniform_limits(struct etna_screen *screen)
 537 {
 538    /* values for the non unified case are taken from
 539     * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
 540     * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
 541     */
 542    if (screen->model == chipModel_GC2000 &&
 543        (screen->revision == 0x5118 || screen->revision == 0x5140)) {
 544       screen->specs.max_vs_uniforms = 256;
 545       screen->specs.max_ps_uniforms = 64;
 546    } else if (screen->specs.num_constants == 320) {
 547       screen->specs.max_vs_uniforms = 256;
 548       screen->specs.max_ps_uniforms = 64;
 549    } else if (screen->specs.num_constants > 256 &&
 550               screen->model == chipModel_GC1000) {
 551       /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
 552       screen->specs.max_vs_uniforms = 256;
 553       screen->specs.max_ps_uniforms = 64;
 554    } else if (screen->specs.num_constants > 256) {
 555       screen->specs.max_vs_uniforms = 256;
 556       screen->specs.max_ps_uniforms = 256;
 557    } else if (screen->specs.num_constants == 256) {
 558       screen->specs.max_vs_uniforms = 256;
 559       screen->specs.max_ps_uniforms = 256;
 560    } else {
 561       screen->specs.max_vs_uniforms = 168;
 562       screen->specs.max_ps_uniforms = 64;
 563    }
 564 }
 565
 566 static bool
 567 etna_get_specs(struct etna_screen *screen)
 568 {
 569    uint64_t val;
 570    uint32_t instruction_count;
 571
 572    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 573       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 574       goto fail;
 575    }
 576    instruction_count = val;
 577
 578    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 579                           &val)) {
 580       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 581       goto fail;
 582    }
 583    screen->specs.vertex_output_buffer_size = val;
 584
 585    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 586       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 587       goto fail;
 588    }
 589    screen->specs.vertex_cache_size = val;
 590
 591    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 592       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 593       goto fail;
 594    }
 595    screen->specs.shader_core_count = val;
 596
 597    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 598       DBG("could not get ETNA_GPU_STREAM_COUNT");
 599       goto fail;
 600    }
 601    screen->specs.stream_count = val;
 602
 603    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 604       DBG("could not get ETNA_GPU_REGISTER_MAX");
 605       goto fail;
 606    }
 607    screen->specs.max_registers = val;
 608
 609    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 610       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 611       goto fail;
 612    }
 613    screen->specs.pixel_pipes = val;
 614
 615    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 616       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 617       goto fail;
 618    }
 619    if (val == 0) {
 620       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 621       val = 168;
 622    }
 623    screen->specs.num_constants = val;
 624
 625    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 626     * description of the differences. */
 627    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 628       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 629    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 630       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 631    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 632       screen->specs.halti = 3; /* None? */
 633    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 634       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 635    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 636       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 637    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 638       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 639    else
 640       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 641    if (screen->specs.halti >= 0)
 642       DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
 643    else
 644       DBG("etnaviv: GPU arch: pre-HALTI");
 645
 646    screen->specs.can_supertile =
 647       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 648    screen->specs.bits_per_tile =
 649       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 650    screen->specs.ts_clear_value =
 651       VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE)  ? 0xffffffff :
 652       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 :
 653                                                              0x11111111;
 654
 655
 656    /* vertex and fragment samplers live in one address space */
 657    screen->specs.vertex_sampler_offset = 8;
 658    screen->specs.fragment_sampler_count = 8;
 659    screen->specs.vertex_sampler_count = 4;
 660    screen->specs.vs_need_z_div =
 661       screen->model < 0x1000 && screen->model != 0x880;
 662    screen->specs.has_sin_cos_sqrt =
 663       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 664    screen->specs.has_sign_floor_ceil =
 665       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 666    screen->specs.has_shader_range_registers =
 667       screen->model >= 0x1000 || screen->model == 0x880;
 668    screen->specs.npot_tex_any_wrap =
 669       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 670    screen->specs.has_new_transcendentals =
 671       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 672    screen->specs.has_halti2_instructions =
 673       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 674    screen->specs.v4_compression =
 675       VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
 676
 677    if (screen->specs.halti >= 5) {
 678       /* GC7000 - this core must load shaders from memory. */
 679       screen->specs.vs_offset = 0;
 680       screen->specs.ps_offset = 0;
 681       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 682       screen->specs.has_icache = true;
 683    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 684       /* GC3000 - this core is capable of loading shaders from
 685        * memory. It can also run shaders from registers, as a fallback, but
 686        * "max_instructions" does not have the correct value. It has place for
 687        * 2*256 instructions just like GC2000, but the offsets are slightly
 688        * different.
 689        */
 690       screen->specs.vs_offset = 0xC000;
 691       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 692        * this mirror for writing PS instructions, probably safest to do the
 693        * same.
 694        */
 695       screen->specs.ps_offset = 0x8000 + 0x1000;
 696       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 697       screen->specs.has_icache = true;
 698    } else {
 699       if (instruction_count > 256) { /* unified instruction memory? */
 700          screen->specs.vs_offset = 0xC000;
 701          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 702          screen->specs.max_instructions = 256;
 703       } else {
 704          screen->specs.vs_offset = 0x4000;
 705          screen->specs.ps_offset = 0x6000;
 706          screen->specs.max_instructions = instruction_count / 2;
 707       }
 708       screen->specs.has_icache = false;
 709    }
 710
 711    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 712       screen->specs.max_varyings = 12;
 713       screen->specs.vertex_max_elements = 16;
 714    } else {
 715       screen->specs.max_varyings = 8;
 716       /* Etna_viv documentation seems confused over the correct value
 717        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 718        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 719       screen->specs.vertex_max_elements = 10;
 720    }
 721
 722    /* Etna_viv documentation does not indicate where varyings above 8 are
 723     * stored. Moreover, if we are passed more than 8 varyings, we will
 724     * walk off the end of some arrays. Limit the maximum number of varyings. */
 725    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 726       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 727
 728    etna_determine_uniform_limits(screen);
 729
 730    if (screen->specs.halti >= 5) {
 731       screen->specs.has_unified_uniforms = true;
 732       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 733       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 734    } else if (screen->specs.halti >= 1) {
 735       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 736       */
 737       screen->specs.has_unified_uniforms = true;
 738       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 739       /* hardcode PS uniforms to start after end of VS uniforms -
 740        * for more flexibility this offset could be variable based on the
 741        * shader.
 742        */
 743       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 744    } else {
 745       screen->specs.has_unified_uniforms = false;
 746       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 747       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 748    }
 749
 750    screen->specs.max_texture_size =
 751       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 752    screen->specs.max_rendertarget_size =
 753       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 754
 755    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 756    if (screen->specs.single_buffer)
 757       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
 758
 759    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 760
 761    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 762
 763    return true;
 764
 765 fail:
 766    return false;
 767 }
 768
 769 struct etna_bo *
 770 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 771                            struct winsys_handle *whandle, unsigned *out_stride)
 772 {
 773    struct etna_screen *screen = etna_screen(pscreen);
 774    struct etna_bo *bo;
 775
 776    if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 777       bo = etna_bo_from_name(screen->dev, whandle->handle);
 778    } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 779       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 780    } else {
 781       DBG("Attempt to import unsupported handle type %d", whandle->type);
 782       return NULL;
 783    }
 784
 785    if (!bo) {
 786       DBG("ref name 0x%08x failed", whandle->handle);
 787       return NULL;
 788    }
 789
 790    *out_stride = whandle->stride;
 791
 792    return bo;
 793 }
 794
 795 static const void *
 796 etna_get_compiler_options(struct pipe_screen *pscreen,
 797                           enum pipe_shader_ir ir, unsigned shader)
 798 {
 799    return &etna_screen(pscreen)->options;
 800 }
 801
 802 struct pipe_screen *
 803 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 804                    struct renderonly *ro)
 805 {
 806    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 807    struct pipe_screen *pscreen;
 808    drmVersionPtr version;
 809    uint64_t val;
 810
 811    if (!screen)
 812       return NULL;
 813
 814    pscreen = &screen->base;
 815    screen->dev = dev;
 816    screen->gpu = gpu;
 817    screen->ro = renderonly_dup(ro);
 818    screen->refcnt = 1;
 819
 820    if (!screen->ro) {
 821       DBG("could not create renderonly object");
 822       goto fail;
 823    }
 824
 825    version = drmGetVersion(screen->ro->gpu_fd);
 826    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 827                                           version->version_minor);
 828    drmFreeVersion(version);
 829
 830    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 831
 832    /* Disable autodisable for correct rendering with TS */
 833    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 834
 835    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 836    if (!screen->pipe) {
 837       DBG("could not create 3d pipe");
 838       goto fail;
 839    }
 840
 841    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 842       DBG("could not get ETNA_GPU_MODEL");
 843       goto fail;
 844    }
 845    screen->model = val;
 846
 847    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 848       DBG("could not get ETNA_GPU_REVISION");
 849       goto fail;
 850    }
 851    screen->revision = val;
 852
 853    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 854       DBG("could not get ETNA_GPU_FEATURES_0");
 855       goto fail;
 856    }
 857    screen->features[0] = val;
 858
 859    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 860       DBG("could not get ETNA_GPU_FEATURES_1");
 861       goto fail;
 862    }
 863    screen->features[1] = val;
 864
 865    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 866       DBG("could not get ETNA_GPU_FEATURES_2");
 867       goto fail;
 868    }
 869    screen->features[2] = val;
 870
 871    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 872       DBG("could not get ETNA_GPU_FEATURES_3");
 873       goto fail;
 874    }
 875    screen->features[3] = val;
 876
 877    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 878       DBG("could not get ETNA_GPU_FEATURES_4");
 879       goto fail;
 880    }
 881    screen->features[4] = val;
 882
 883    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 884       DBG("could not get ETNA_GPU_FEATURES_5");
 885       goto fail;
 886    }
 887    screen->features[5] = val;
 888
 889    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 890       DBG("could not get ETNA_GPU_FEATURES_6");
 891       goto fail;
 892    }
 893    screen->features[6] = val;
 894
 895    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) {
 896       DBG("could not get ETNA_GPU_FEATURES_7");
 897       goto fail;
 898    }
 899    screen->features[7] = val;
 900
 901    if (!etna_get_specs(screen))
 902       goto fail;
 903
 904    screen->options = (nir_shader_compiler_options) {
 905       .lower_fpow = true,
 906       .lower_sub = true,
 907       .lower_ftrunc = true,
 908       .fuse_ffma = true,
 909       .lower_bitops = true,
 910       .lower_all_io_to_temps = true,
 911       .vertex_id_zero_based = true,
 912       .lower_flrp32 = true,
 913       .lower_fmod = true,
 914       .lower_vector_cmp = true,
 915       .lower_fdph = true,
 916       .lower_fdiv = true, /* !screen->specs.has_new_transcendentals */
 917       .lower_fsign = !screen->specs.has_sign_floor_ceil,
 918       .lower_ffloor = !screen->specs.has_sign_floor_ceil,
 919       .lower_fceil = !screen->specs.has_sign_floor_ceil,
 920       .lower_fsqrt = !screen->specs.has_sin_cos_sqrt,
 921       .lower_sincos = !screen->specs.has_sin_cos_sqrt,
 922    };
 923
 924    /* apply debug options that disable individual features */
 925    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 926       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 927    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 928          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 929    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 930       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 931    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 932       screen->specs.can_supertile = 0;
 933    if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
 934       screen->specs.single_buffer = 0;
 935
 936    pscreen->destroy = etna_screen_destroy;
 937    pscreen->get_param = etna_screen_get_param;
 938    pscreen->get_paramf = etna_screen_get_paramf;
 939    pscreen->get_shader_param = etna_screen_get_shader_param;
 940    pscreen->get_compiler_options = etna_get_compiler_options;
 941
 942    pscreen->get_name = etna_screen_get_name;
 943    pscreen->get_vendor = etna_screen_get_vendor;
 944    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 945
 946    pscreen->get_timestamp = etna_screen_get_timestamp;
 947    pscreen->context_create = etna_context_create;
 948    pscreen->is_format_supported = etna_screen_is_format_supported;
 949    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 950
 951    etna_fence_screen_init(pscreen);
 952    etna_query_screen_init(pscreen);
 953    etna_resource_screen_init(pscreen);
 954
 955    util_dynarray_init(&screen->supported_pm_queries, NULL);
 956    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 957
 958    if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
 959       etna_pm_query_setup(screen);
 960
 961    mtx_init(&screen->lock, mtx_recursive);
 962    screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer,
 963                                              _mesa_key_pointer_equal);
 964    if (!screen->used_resources)
 965       goto fail2;
 966
 967    return pscreen;
 968
 969 fail2:
 970    mtx_destroy(&screen->lock);
 971 fail:
 972    etna_screen_destroy(pscreen);
 973    return NULL;
 974 }