src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/hash_table.h"
  42 #include "util/os_time.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_screen.h"
  46 #include "util/u_string.h"
  47
  48 #include "state_tracker/drm_driver.h"
  49
  50 #include "drm-uapi/drm_fourcc.h"
  51
  52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  53 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  54 #define ETNA_DRM_VERSION_PERFMON       ETNA_DRM_VERSION(1, 2)
  55
  56 static const struct debug_named_value debug_options[] = {
  57    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  58    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  59    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  60    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  61    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  62    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  63    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  64    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  65    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  66    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  67    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
  68    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  69    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  70    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  71    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  72    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  73    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  74    {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
  75    DEBUG_NAMED_VALUE_END
  76 };
  77
  78 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  79 int etna_mesa_debug = 0;
  80
  81 static void
  82 etna_screen_destroy(struct pipe_screen *pscreen)
  83 {
  84    struct etna_screen *screen = etna_screen(pscreen);
  85
  86    _mesa_set_destroy(screen->used_resources, NULL);
  87    mtx_destroy(&screen->lock);
  88
  89    if (screen->perfmon)
  90       etna_perfmon_del(screen->perfmon);
  91
  92    if (screen->pipe)
  93       etna_pipe_del(screen->pipe);
  94
  95    if (screen->gpu)
  96       etna_gpu_del(screen->gpu);
  97
  98    if (screen->ro)
  99       FREE(screen->ro);
 100
 101    if (screen->dev)
 102       etna_device_del(screen->dev);
 103
 104    FREE(screen);
 105 }
 106
 107 static const char *
 108 etna_screen_get_name(struct pipe_screen *pscreen)
 109 {
 110    struct etna_screen *priv = etna_screen(pscreen);
 111    static char buffer[128];
 112
 113    snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 114             priv->revision);
 115
 116    return buffer;
 117 }
 118
 119 static const char *
 120 etna_screen_get_vendor(struct pipe_screen *pscreen)
 121 {
 122    return "etnaviv";
 123 }
 124
 125 static const char *
 126 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 127 {
 128    return "Vivante";
 129 }
 130
 131 static int
 132 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 133 {
 134    struct etna_screen *screen = etna_screen(pscreen);
 135
 136    switch (param) {
 137    /* Supported features (boolean caps). */
 138    case PIPE_CAP_ANISOTROPIC_FILTER:
 139    case PIPE_CAP_POINT_SPRITE:
 140    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 141    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 142    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 143    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 144    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
 145    case PIPE_CAP_VERTEX_SHADER_SATURATE:
 146    case PIPE_CAP_TEXTURE_BARRIER:
 147    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 148    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 149    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 150    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 151    case PIPE_CAP_TGSI_TEXCOORD:
 152    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 153    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 154       return 1;
 155    case PIPE_CAP_NATIVE_FENCE_FD:
 156       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 157
 158    /* Memory */
 159    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 160       return 256;
 161    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 162       return 4; /* XXX could easily be supported */
 163
 164    case PIPE_CAP_NPOT_TEXTURES:
 165       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 166                       NON_POWER_OF_TWO); */
 167
 168    case PIPE_CAP_TEXTURE_SWIZZLE:
 169    case PIPE_CAP_PRIMITIVE_RESTART:
 170       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 171
 172    /* Unsupported features. */
 173    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 174    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 175    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 176       return 0;
 177
 178    /* Stream output. */
 179    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 180    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 181       return 0;
 182
 183    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 184       return 128;
 185    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 186       return 255;
 187
 188    /* Texturing. */
 189    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 190       return screen->specs.max_texture_size;
 191    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 192    {
 193       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 194       assert(log2_max_tex_size > 0);
 195       return log2_max_tex_size;
 196    }
 197    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 198       return 5;
 199    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 200    case PIPE_CAP_MIN_TEXEL_OFFSET:
 201       return -8;
 202    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 203    case PIPE_CAP_MAX_TEXEL_OFFSET:
 204       return 7;
 205    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 206       return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
 207
 208    /* Timer queries. */
 209    case PIPE_CAP_OCCLUSION_QUERY:
 210       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 211    case PIPE_CAP_QUERY_TIMESTAMP:
 212       return 1;
 213
 214    /* Preferences */
 215    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 216       return 0;
 217
 218    case PIPE_CAP_MAX_VARYINGS:
 219       return screen->specs.max_varyings;
 220
 221    case PIPE_CAP_PCI_GROUP:
 222    case PIPE_CAP_PCI_BUS:
 223    case PIPE_CAP_PCI_DEVICE:
 224    case PIPE_CAP_PCI_FUNCTION:
 225       return 0;
 226    case PIPE_CAP_ACCELERATED:
 227       return 1;
 228    case PIPE_CAP_VIDEO_MEMORY:
 229       return 0;
 230    case PIPE_CAP_UMA:
 231       return 1;
 232    default:
 233       return u_pipe_screen_get_param_defaults(pscreen, param);
 234    }
 235 }
 236
 237 static float
 238 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 239 {
 240    struct etna_screen *screen = etna_screen(pscreen);
 241
 242    switch (param) {
 243    case PIPE_CAPF_MAX_LINE_WIDTH:
 244    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 245    case PIPE_CAPF_MAX_POINT_WIDTH:
 246    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 247       return 8192.0f;
 248    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 249       return 16.0f;
 250    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 251       return util_last_bit(screen->specs.max_texture_size);
 252    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 253    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 254    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 255       return 0.0f;
 256    }
 257
 258    debug_printf("unknown paramf %d", param);
 259    return 0;
 260 }
 261
 262 static int
 263 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 264                              enum pipe_shader_type shader,
 265                              enum pipe_shader_cap param)
 266 {
 267    struct etna_screen *screen = etna_screen(pscreen);
 268
 269    switch (shader) {
 270    case PIPE_SHADER_FRAGMENT:
 271    case PIPE_SHADER_VERTEX:
 272       break;
 273    case PIPE_SHADER_COMPUTE:
 274    case PIPE_SHADER_GEOMETRY:
 275    case PIPE_SHADER_TESS_CTRL:
 276    case PIPE_SHADER_TESS_EVAL:
 277       return 0;
 278    default:
 279       DBG("unknown shader type %d", shader);
 280       return 0;
 281    }
 282
 283    switch (param) {
 284    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 285    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 286    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 287    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 288       return ETNA_MAX_TOKENS;
 289    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 290       return ETNA_MAX_DEPTH; /* XXX */
 291    case PIPE_SHADER_CAP_MAX_INPUTS:
 292       /* Maximum number of inputs for the vertex shader is the number
 293        * of vertex elements - each element defines one vertex shader
 294        * input register.  For the fragment shader, this is the number
 295        * of varyings. */
 296       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 297                                             : screen->specs.vertex_max_elements;
 298    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 299       return 16; /* see VIVS_VS_OUTPUT */
 300    case PIPE_SHADER_CAP_MAX_TEMPS:
 301       return 64; /* Max native temporaries. */
 302    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 303       return 1;
 304    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 305       return 1;
 306    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 307    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 308    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 309    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 310       return 1;
 311    case PIPE_SHADER_CAP_SUBROUTINES:
 312       return 0;
 313    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 314       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 315    case PIPE_SHADER_CAP_INTEGERS:
 316    case PIPE_SHADER_CAP_INT64_ATOMICS:
 317    case PIPE_SHADER_CAP_FP16:
 318       return 0;
 319    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 320    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 321       return shader == PIPE_SHADER_FRAGMENT
 322                 ? screen->specs.fragment_sampler_count
 323                 : screen->specs.vertex_sampler_count;
 324    case PIPE_SHADER_CAP_PREFERRED_IR:
 325       return PIPE_SHADER_IR_TGSI;
 326    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 327       return 4096;
 328    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 329    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 330    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 331    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 332    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 333       return false;
 334    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 335       return 0;
 336    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 337       return 32;
 338    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 339    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 340    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 341    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 342    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 343    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 344    case PIPE_SHADER_CAP_SCALAR_ISA:
 345       return 0;
 346    }
 347
 348    debug_printf("unknown shader param %d", param);
 349    return 0;
 350 }
 351
 352 static uint64_t
 353 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 354 {
 355    return os_time_get_nano();
 356 }
 357
 358 static bool
 359 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 360                            enum pipe_format format)
 361 {
 362    bool supported = true;
 363
 364    if (fmt == TEXTURE_FORMAT_ETC1)
 365       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 366
 367    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 368       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 369
 370    if (util_format_is_srgb(format))
 371       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 372
 373    if (fmt & EXT_FORMAT)
 374       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 375
 376    if (fmt & ASTC_FORMAT) {
 377       supported = screen->specs.tex_astc;
 378    }
 379
 380    if (!supported)
 381       return false;
 382
 383    if (texture_format_needs_swiz(format))
 384       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 385
 386    return true;
 387 }
 388
 389 static boolean
 390 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 391                                 enum pipe_format format,
 392                                 enum pipe_texture_target target,
 393                                 unsigned sample_count,
 394                                 unsigned storage_sample_count,
 395                                 unsigned usage)
 396 {
 397    struct etna_screen *screen = etna_screen(pscreen);
 398    unsigned allowed = 0;
 399
 400    if (target != PIPE_BUFFER &&
 401        target != PIPE_TEXTURE_1D &&
 402        target != PIPE_TEXTURE_2D &&
 403        target != PIPE_TEXTURE_3D &&
 404        target != PIPE_TEXTURE_CUBE &&
 405        target != PIPE_TEXTURE_RECT)
 406       return FALSE;
 407
 408    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 409       return false;
 410
 411    if (usage & PIPE_BIND_RENDER_TARGET) {
 412       /* if render target, must be RS-supported format */
 413       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 414          /* Validate MSAA; number of samples must be allowed, and render target
 415           * must have MSAA'able format. */
 416          if (sample_count > 1) {
 417             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 418                 translate_ts_format(format) != ETNA_NO_MATCH) {
 419                allowed |= PIPE_BIND_RENDER_TARGET;
 420             }
 421          } else {
 422             allowed |= PIPE_BIND_RENDER_TARGET;
 423          }
 424       }
 425    }
 426
 427    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 428       if (translate_depth_format(format) != ETNA_NO_MATCH)
 429          allowed |= PIPE_BIND_DEPTH_STENCIL;
 430    }
 431
 432    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 433       uint32_t fmt = translate_texture_format(format);
 434
 435       if (!gpu_supports_texure_format(screen, fmt, format))
 436          fmt = ETNA_NO_MATCH;
 437
 438       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 439          allowed |= PIPE_BIND_SAMPLER_VIEW;
 440    }
 441
 442    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 443       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 444          allowed |= PIPE_BIND_VERTEX_BUFFER;
 445    }
 446
 447    if (usage & PIPE_BIND_INDEX_BUFFER) {
 448       /* must be supported index format */
 449       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 450           (format == PIPE_FORMAT_I32_UINT &&
 451            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 452          allowed |= PIPE_BIND_INDEX_BUFFER;
 453       }
 454    }
 455
 456    /* Always allowed */
 457    allowed |=
 458       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 459
 460    if (usage != allowed) {
 461       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 462           "usage=%x, allowed=%x",
 463           util_format_name(format), target, sample_count, usage, allowed);
 464    }
 465
 466    return usage == allowed;
 467 }
 468
 469 const uint64_t supported_modifiers[] = {
 470    DRM_FORMAT_MOD_LINEAR,
 471    DRM_FORMAT_MOD_VIVANTE_TILED,
 472    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 473    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 474    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 475 };
 476
 477 static void
 478 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 479                                    enum pipe_format format, int max,
 480                                    uint64_t *modifiers,
 481                                    unsigned int *external_only, int *count)
 482 {
 483    struct etna_screen *screen = etna_screen(pscreen);
 484    int i, num_modifiers = 0;
 485
 486    if (max > ARRAY_SIZE(supported_modifiers))
 487       max = ARRAY_SIZE(supported_modifiers);
 488
 489    if (!max) {
 490       modifiers = NULL;
 491       max = ARRAY_SIZE(supported_modifiers);
 492    }
 493
 494    for (i = 0; num_modifiers < max; i++) {
 495       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 496       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 497           i >= 3)
 498          break;
 499
 500       if (modifiers)
 501          modifiers[num_modifiers] = supported_modifiers[i];
 502       if (external_only)
 503          external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
 504       num_modifiers++;
 505    }
 506
 507    *count = num_modifiers;
 508 }
 509
 510 static boolean
 511 etna_get_specs(struct etna_screen *screen)
 512 {
 513    uint64_t val;
 514    uint32_t instruction_count;
 515
 516    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 517       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 518       goto fail;
 519    }
 520    instruction_count = val;
 521
 522    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 523                           &val)) {
 524       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 525       goto fail;
 526    }
 527    screen->specs.vertex_output_buffer_size = val;
 528
 529    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 530       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 531       goto fail;
 532    }
 533    screen->specs.vertex_cache_size = val;
 534
 535    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 536       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 537       goto fail;
 538    }
 539    screen->specs.shader_core_count = val;
 540
 541    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 542       DBG("could not get ETNA_GPU_STREAM_COUNT");
 543       goto fail;
 544    }
 545    screen->specs.stream_count = val;
 546
 547    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 548       DBG("could not get ETNA_GPU_REGISTER_MAX");
 549       goto fail;
 550    }
 551    screen->specs.max_registers = val;
 552
 553    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 554       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 555       goto fail;
 556    }
 557    screen->specs.pixel_pipes = val;
 558
 559    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 560       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 561       goto fail;
 562    }
 563    if (val == 0) {
 564       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 565       val = 168;
 566    }
 567    screen->specs.num_constants = val;
 568
 569    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 570     * description of the differences. */
 571    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 572       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 573    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 574       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 575    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 576       screen->specs.halti = 3; /* None? */
 577    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 578       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 579    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 580       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 581    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 582       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 583    else
 584       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 585    if (screen->specs.halti >= 0)
 586       DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
 587    else
 588       DBG("etnaviv: GPU arch: pre-HALTI");
 589
 590    screen->specs.can_supertile =
 591       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 592    screen->specs.bits_per_tile =
 593       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 594    screen->specs.ts_clear_value =
 595       VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE)  ? 0xffffffff :
 596       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 :
 597                                                              0x11111111;
 598
 599
 600    /* vertex and fragment samplers live in one address space */
 601    screen->specs.vertex_sampler_offset = 8;
 602    screen->specs.fragment_sampler_count = 8;
 603    screen->specs.vertex_sampler_count = 4;
 604    screen->specs.vs_need_z_div =
 605       screen->model < 0x1000 && screen->model != 0x880;
 606    screen->specs.has_sin_cos_sqrt =
 607       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 608    screen->specs.has_sign_floor_ceil =
 609       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 610    screen->specs.has_shader_range_registers =
 611       screen->model >= 0x1000 || screen->model == 0x880;
 612    screen->specs.npot_tex_any_wrap =
 613       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 614    screen->specs.has_new_transcendentals =
 615       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 616    screen->specs.has_halti2_instructions =
 617       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 618    screen->specs.v4_compression =
 619       VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
 620
 621    if (screen->specs.halti >= 5) {
 622       /* GC7000 - this core must load shaders from memory. */
 623       screen->specs.vs_offset = 0;
 624       screen->specs.ps_offset = 0;
 625       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 626       screen->specs.has_icache = true;
 627    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 628       /* GC3000 - this core is capable of loading shaders from
 629        * memory. It can also run shaders from registers, as a fallback, but
 630        * "max_instructions" does not have the correct value. It has place for
 631        * 2*256 instructions just like GC2000, but the offsets are slightly
 632        * different.
 633        */
 634       screen->specs.vs_offset = 0xC000;
 635       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 636        * this mirror for writing PS instructions, probably safest to do the
 637        * same.
 638        */
 639       screen->specs.ps_offset = 0x8000 + 0x1000;
 640       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 641       screen->specs.has_icache = true;
 642    } else {
 643       if (instruction_count > 256) { /* unified instruction memory? */
 644          screen->specs.vs_offset = 0xC000;
 645          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 646          screen->specs.max_instructions = 256;
 647       } else {
 648          screen->specs.vs_offset = 0x4000;
 649          screen->specs.ps_offset = 0x6000;
 650          screen->specs.max_instructions = instruction_count / 2;
 651       }
 652       screen->specs.has_icache = false;
 653    }
 654
 655    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 656       screen->specs.max_varyings = 12;
 657       screen->specs.vertex_max_elements = 16;
 658    } else {
 659       screen->specs.max_varyings = 8;
 660       /* Etna_viv documentation seems confused over the correct value
 661        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 662        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 663       screen->specs.vertex_max_elements = 10;
 664    }
 665
 666    /* Etna_viv documentation does not indicate where varyings above 8 are
 667     * stored. Moreover, if we are passed more than 8 varyings, we will
 668     * walk off the end of some arrays. Limit the maximum number of varyings. */
 669    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 670       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 671
 672    /* from QueryShaderCaps in kernel driver */
 673    if (screen->model < chipModel_GC4000) {
 674       screen->specs.max_vs_uniforms = 168;
 675       screen->specs.max_ps_uniforms = 64;
 676    } else {
 677       screen->specs.max_vs_uniforms = 256;
 678       screen->specs.max_ps_uniforms = 256;
 679    }
 680
 681    if (screen->specs.halti >= 5) {
 682       screen->specs.has_unified_uniforms = true;
 683       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 684       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 685    } else if (screen->specs.halti >= 1) {
 686       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 687       */
 688       screen->specs.has_unified_uniforms = true;
 689       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 690       /* hardcode PS uniforms to start after end of VS uniforms -
 691        * for more flexibility this offset could be variable based on the
 692        * shader.
 693        */
 694       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 695    } else {
 696       screen->specs.has_unified_uniforms = false;
 697       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 698       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 699    }
 700
 701    screen->specs.max_texture_size =
 702       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 703    screen->specs.max_rendertarget_size =
 704       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 705
 706    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 707    if (screen->specs.single_buffer)
 708       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
 709
 710    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 711
 712    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 713
 714    return true;
 715
 716 fail:
 717    return false;
 718 }
 719
 720 struct etna_bo *
 721 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 722                            struct winsys_handle *whandle, unsigned *out_stride)
 723 {
 724    struct etna_screen *screen = etna_screen(pscreen);
 725    struct etna_bo *bo;
 726
 727    if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 728       bo = etna_bo_from_name(screen->dev, whandle->handle);
 729    } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 730       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 731    } else {
 732       DBG("Attempt to import unsupported handle type %d", whandle->type);
 733       return NULL;
 734    }
 735
 736    if (!bo) {
 737       DBG("ref name 0x%08x failed", whandle->handle);
 738       return NULL;
 739    }
 740
 741    *out_stride = whandle->stride;
 742
 743    return bo;
 744 }
 745
 746 struct pipe_screen *
 747 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 748                    struct renderonly *ro)
 749 {
 750    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 751    struct pipe_screen *pscreen;
 752    drmVersionPtr version;
 753    uint64_t val;
 754
 755    if (!screen)
 756       return NULL;
 757
 758    pscreen = &screen->base;
 759    screen->dev = dev;
 760    screen->gpu = gpu;
 761    screen->ro = renderonly_dup(ro);
 762    screen->refcnt = 1;
 763
 764    if (!screen->ro) {
 765       DBG("could not create renderonly object");
 766       goto fail;
 767    }
 768
 769    version = drmGetVersion(screen->ro->gpu_fd);
 770    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 771                                           version->version_minor);
 772    drmFreeVersion(version);
 773
 774    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 775
 776    /* Disable autodisable for correct rendering with TS */
 777    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 778
 779    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 780    if (!screen->pipe) {
 781       DBG("could not create 3d pipe");
 782       goto fail;
 783    }
 784
 785    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 786       DBG("could not get ETNA_GPU_MODEL");
 787       goto fail;
 788    }
 789    screen->model = val;
 790
 791    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 792       DBG("could not get ETNA_GPU_REVISION");
 793       goto fail;
 794    }
 795    screen->revision = val;
 796
 797    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 798       DBG("could not get ETNA_GPU_FEATURES_0");
 799       goto fail;
 800    }
 801    screen->features[0] = val;
 802
 803    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 804       DBG("could not get ETNA_GPU_FEATURES_1");
 805       goto fail;
 806    }
 807    screen->features[1] = val;
 808
 809    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 810       DBG("could not get ETNA_GPU_FEATURES_2");
 811       goto fail;
 812    }
 813    screen->features[2] = val;
 814
 815    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 816       DBG("could not get ETNA_GPU_FEATURES_3");
 817       goto fail;
 818    }
 819    screen->features[3] = val;
 820
 821    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 822       DBG("could not get ETNA_GPU_FEATURES_4");
 823       goto fail;
 824    }
 825    screen->features[4] = val;
 826
 827    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 828       DBG("could not get ETNA_GPU_FEATURES_5");
 829       goto fail;
 830    }
 831    screen->features[5] = val;
 832
 833    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 834       DBG("could not get ETNA_GPU_FEATURES_6");
 835       goto fail;
 836    }
 837    screen->features[6] = val;
 838
 839    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) {
 840       DBG("could not get ETNA_GPU_FEATURES_7");
 841       goto fail;
 842    }
 843    screen->features[7] = val;
 844
 845    if (!etna_get_specs(screen))
 846       goto fail;
 847
 848    /* apply debug options that disable individual features */
 849    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 850       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 851    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 852          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 853    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 854       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 855    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 856       screen->specs.can_supertile = 0;
 857    if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
 858       screen->specs.single_buffer = 0;
 859
 860    pscreen->destroy = etna_screen_destroy;
 861    pscreen->get_param = etna_screen_get_param;
 862    pscreen->get_paramf = etna_screen_get_paramf;
 863    pscreen->get_shader_param = etna_screen_get_shader_param;
 864
 865    pscreen->get_name = etna_screen_get_name;
 866    pscreen->get_vendor = etna_screen_get_vendor;
 867    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 868
 869    pscreen->get_timestamp = etna_screen_get_timestamp;
 870    pscreen->context_create = etna_context_create;
 871    pscreen->is_format_supported = etna_screen_is_format_supported;
 872    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 873
 874    etna_fence_screen_init(pscreen);
 875    etna_query_screen_init(pscreen);
 876    etna_resource_screen_init(pscreen);
 877
 878    util_dynarray_init(&screen->supported_pm_queries, NULL);
 879    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 880
 881    if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
 882       etna_pm_query_setup(screen);
 883
 884    mtx_init(&screen->lock, mtx_recursive);
 885    screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer,
 886                                              _mesa_key_pointer_equal);
 887    if (!screen->used_resources)
 888       goto fail2;
 889
 890    return pscreen;
 891
 892 fail2:
 893    mtx_destroy(&screen->lock);
 894 fail:
 895    etna_screen_destroy(pscreen);
 896    return NULL;
 897 }