src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_upload_mgr.h"
  46
  47 static void
  48 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  49 {
  50    struct etna_context *ctx = etna_context(pctx);
  51    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  52
  53    ctx->stencil_ref_s = *sr;
  54
  55    for (unsigned i = 0; i < 2; i++) {
  56       cs->PE_STENCIL_CONFIG[i] =
  57          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  58       cs->PE_STENCIL_CONFIG_EXT[i] =
  59          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  60    }
  61    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  62 }
  63
  64 static void
  65 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  66 {
  67    /* NOOP */
  68 }
  69
  70 static void
  71 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  72 {
  73    struct etna_context *ctx = etna_context(pctx);
  74
  75    ctx->sample_mask = sample_mask;
  76    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  77 }
  78
  79 static void
  80 etna_set_constant_buffer(struct pipe_context *pctx,
  81       enum pipe_shader_type shader, uint index,
  82       const struct pipe_constant_buffer *cb)
  83 {
  84    struct etna_context *ctx = etna_context(pctx);
  85    struct etna_constbuf_state *so = &ctx->constant_buffer[shader];
  86
  87    assert(index < ETNA_MAX_CONST_BUF);
  88
  89    util_copy_constant_buffer(&so->cb[index], cb);
  90
  91    /* Note that the state tracker can unbind constant buffers by
  92     * passing NULL here. */
  93    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) {
  94       so->enabled_mask &= ~(1 << index);
  95       return;
  96    }
  97
  98    assert(index != 0 || cb->user_buffer != NULL);
  99
 100    if (!cb->buffer) {
 101       struct pipe_constant_buffer *cb = &so->cb[index];
 102       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 103    }
 104
 105    so->enabled_mask |= 1 << index;
 106    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 107 }
 108
 109 static void
 110 etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
 111 {
 112    struct etna_resource *to = base, *from = base;
 113
 114    if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
 115       from = etna_resource(base->texture);
 116
 117    if (base->render)
 118       to = etna_resource(base->render);
 119
 120    if ((to != from) && etna_resource_older(to, from)) {
 121       etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
 122       to->seqno = from->seqno;
 123    }
 124 }
 125
 126 static void
 127 etna_set_framebuffer_state(struct pipe_context *pctx,
 128       const struct pipe_framebuffer_state *fb)
 129 {
 130    struct etna_context *ctx = etna_context(pctx);
 131    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 132    int nr_samples_color = -1;
 133    int nr_samples_depth = -1;
 134
 135    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 136    uint32_t ts_mem_config = 0;
 137    uint32_t pe_mem_config = 0;
 138    uint32_t pe_logic_op = 0;
 139
 140    if (fb->nr_cbufs > 0) { /* at least one color buffer? */
 141       struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
 142       struct etna_resource *res = etna_resource(cbuf->base.texture);
 143       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 144       uint32_t fmt = translate_pe_format(cbuf->base.format);
 145
 146       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 147       etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
 148
 149       if (fmt >= PE_FORMAT_R16F)
 150           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
 151                                 VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
 152       else
 153           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
 154
 155       cs->PE_COLOR_FORMAT |=
 156          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 157          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 158          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 159          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 160       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 161        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 162        * but only if we set the bits above. */
 163       /* merged with depth_stencil_alpha */
 164       if ((cbuf->surf.offset & 63) ||
 165           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 166          /* XXX Must make temporary surface here.
 167           * Need the same mechanism on gc2000 when we want to do mipmap
 168           * generation by
 169           * rendering to levels > 1 due to multitiled / tiled conversion. */
 170          BUG("Alignment error, trying to render to offset %08x with tile "
 171              "stride %i",
 172              cbuf->surf.offset, cbuf->surf.stride * 4);
 173       }
 174
 175       if (ctx->specs.pixel_pipes == 1) {
 176          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 177          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 178       } else {
 179          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 180          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 181          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 182             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 183             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 184          }
 185       }
 186       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 187
 188       if (cbuf->surf.ts_size) {
 189          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 190          cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
 191
 192          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 193          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 194
 195          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 196          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 197
 198          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 199
 200          if (cbuf->level->ts_compress_fmt >= 0) {
 201             /* overwrite bit breaks v1/v2 compression */
 202             if (!ctx->specs.v4_compression)
 203                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 204
 205             ts_mem_config |=
 206                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 207                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 208          }
 209       }
 210
 211       nr_samples_color = cbuf->base.texture->nr_samples;
 212
 213       if (util_format_is_srgb(cbuf->base.format))
 214          pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB;
 215
 216       cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
 217       cs->PS_CONTROL_EXT =
 218          VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, ctx->specs.halti >= 5));
 219    } else {
 220       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 221        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 222        * color target */
 223       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 224       cs->PE_COLOR_STRIDE = 0;
 225       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 226       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 227
 228       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 229       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 230          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 231    }
 232
 233    if (fb->zsbuf != NULL) {
 234       struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
 235       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 236
 237       etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
 238
 239       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 240
 241       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 242       unsigned depth_bits =
 243          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 244       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 245
 246       cs->PE_DEPTH_CONFIG =
 247          depth_format |
 248          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 249          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 250          VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
 251          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 252          ;
 253       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 254       /* merged with depth_stencil_alpha */
 255
 256       if (ctx->specs.pixel_pipes == 1) {
 257          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 258          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 259       } else {
 260          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 261             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 262             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 263          }
 264       }
 265
 266       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 267       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 268       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 269
 270       if (zsbuf->surf.ts_size) {
 271          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 272
 273          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 274          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 275
 276          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 277          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 278
 279          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 280
 281          if (zsbuf->level->ts_compress_fmt >= 0) {
 282             ts_mem_config |=
 283                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 284                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 285                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 286          }
 287       }
 288
 289       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 290
 291       nr_samples_depth = zsbuf->base.texture->nr_samples;
 292    } else {
 293       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 294       cs->PE_DEPTH_ADDR.bo = NULL;
 295       cs->PE_DEPTH_STRIDE = 0;
 296       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 297       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 298
 299       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 300          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 301    }
 302
 303    /* MSAA setup */
 304    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 305        nr_samples_depth != nr_samples_color) {
 306       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 307           nr_samples_color, nr_samples_depth);
 308    }
 309
 310    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 311    case 0:
 312    case 1: /* Are 0 and 1 samples allowed? */
 313       cs->GL_MULTI_SAMPLE_CONFIG =
 314          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 315       cs->msaa_mode = false;
 316       break;
 317    case 2:
 318       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 319       cs->msaa_mode = true; /* Add input to PS */
 320       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 321       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 322       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 323       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 324       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 325       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 326       break;
 327    case 4:
 328       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 329       cs->msaa_mode = true; /* Add input to PS */
 330       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 331       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 332       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 333       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 334       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 335       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 336       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 337       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 338       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 339       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 340       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 341       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 342       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 343       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 344       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 345       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 346       break;
 347    }
 348
 349    /* Scissor setup */
 350    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 351    cs->SE_SCISSOR_TOP = 0;
 352    cs->SE_SCISSOR_RIGHT = (fb->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 353    cs->SE_SCISSOR_BOTTOM = (fb->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 354    cs->SE_CLIP_RIGHT = (fb->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 355    cs->SE_CLIP_BOTTOM = (fb->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 356
 357    cs->TS_MEM_CONFIG = ts_mem_config;
 358    cs->PE_MEM_CONFIG = pe_mem_config;
 359
 360    /* Single buffer setup. There is only one switch for this, not a separate
 361     * one per color buffer / depth buffer. To keep the logic simple always use
 362     * single buffer when this feature is available.
 363     * note: the blob will use 2 in some situations, figure out why?
 364     */
 365    pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 366    cs->PE_LOGIC_OP = pe_logic_op;
 367
 368    /* keep copy of original structure */
 369    util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
 370    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 371 }
 372
 373 static void
 374 etna_set_polygon_stipple(struct pipe_context *pctx,
 375       const struct pipe_poly_stipple *stipple)
 376 {
 377    /* NOP */
 378 }
 379
 380 static void
 381 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 382       unsigned num_scissors, const struct pipe_scissor_state *ss)
 383 {
 384    struct etna_context *ctx = etna_context(pctx);
 385    struct compiled_scissor_state *cs = &ctx->scissor;
 386    assert(ss->minx <= ss->maxx);
 387    assert(ss->miny <= ss->maxy);
 388
 389    /* note that this state is only used when rasterizer_state->scissor is on */
 390    ctx->scissor_s = *ss;
 391    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 392    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 393    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 394    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 395    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 396    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 397
 398    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 399 }
 400
 401 static void
 402 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 403       unsigned num_scissors, const struct pipe_viewport_state *vs)
 404 {
 405    struct etna_context *ctx = etna_context(pctx);
 406    struct compiled_viewport_state *cs = &ctx->viewport;
 407
 408    ctx->viewport_s = *vs;
 409    /**
 410     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 411     * -1..1 to 0..1.
 412     * scaling and translation to 0..1 already happened, so remove that
 413     *
 414     * z' = (z * 2 - 1) * scale + translate
 415     *    = z * (2 * scale) + (translate - scale)
 416     *
 417     * scale' = 2 * scale
 418     * translate' = translate - scale
 419     */
 420
 421    /* must be fixp as v4 state deltas assume it is */
 422    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 423    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 424    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 425    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 426    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 427    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 428
 429    /* Compute scissor rectangle (fixp) from viewport.
 430     * Make sure left is always < right and top always < bottom.
 431     */
 432    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 433    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 434    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 435    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 436    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 437    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 438    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 439    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 440
 441    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 442    cs->PE_DEPTH_FAR = fui(1.0);
 443    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 444 }
 445
 446 static void
 447 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 448       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 449 {
 450    struct etna_context *ctx = etna_context(pctx);
 451    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 452
 453    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 454    so->count = util_last_bit(so->enabled_mask);
 455
 456    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 457       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 458       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 459
 460       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 461                                        etna_usermem_map */
 462
 463       if (vbi->buffer.resource) { /* GPU buffer */
 464          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 465          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 466          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 467          cs->FE_VERTEX_STREAM_CONTROL =
 468             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 469       } else {
 470          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 471          cs->FE_VERTEX_STREAM_CONTROL = 0;
 472       }
 473    }
 474
 475    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 476 }
 477
 478 static void
 479 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 480 {
 481    struct etna_context *ctx = etna_context(pctx);
 482
 483    ctx->blend = bs;
 484    ctx->dirty |= ETNA_DIRTY_BLEND;
 485 }
 486
 487 static void
 488 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 489 {
 490    FREE(bs);
 491 }
 492
 493 static void
 494 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 495 {
 496    struct etna_context *ctx = etna_context(pctx);
 497
 498    ctx->rasterizer = rs;
 499    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 500 }
 501
 502 static void
 503 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 504 {
 505    FREE(rs);
 506 }
 507
 508 static void
 509 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 510 {
 511    struct etna_context *ctx = etna_context(pctx);
 512
 513    ctx->zsa = zs;
 514    ctx->dirty |= ETNA_DIRTY_ZSA;
 515 }
 516
 517 static void
 518 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 519 {
 520    FREE(zs);
 521 }
 522
 523 /** Create vertex element states, which define a layout for fetching
 524  * vertices for rendering.
 525  */
 526 static void *
 527 etna_vertex_elements_state_create(struct pipe_context *pctx,
 528       unsigned num_elements, const struct pipe_vertex_element *elements)
 529 {
 530    struct etna_context *ctx = etna_context(pctx);
 531    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 532
 533    if (!cs)
 534       return NULL;
 535
 536    if (num_elements > ctx->specs.vertex_max_elements) {
 537       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 538           ctx->specs.vertex_max_elements);
 539       return NULL;
 540    }
 541
 542    /* XXX could minimize number of consecutive stretches here by sorting, and
 543     * permuting the inputs in shader or does Mesa do this already? */
 544
 545    cs->num_elements = num_elements;
 546
 547    unsigned start_offset = 0; /* start of current consecutive stretch */
 548    bool nonconsecutive = true; /* previous value of nonconsecutive */
 549    uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */
 550
 551    for (unsigned idx = 0; idx < num_elements; ++idx) {
 552       unsigned buffer_idx = elements[idx].vertex_buffer_index;
 553       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 554       unsigned end_offset = elements[idx].src_offset + element_size;
 555       uint32_t format_type, normalize;
 556
 557       if (nonconsecutive)
 558          start_offset = elements[idx].src_offset;
 559
 560       /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
 561       assert(buffer_idx < ctx->specs.stream_count);
 562
 563       /* maximum vertex size is 256 bytes */
 564       assert(element_size != 0 && (end_offset - start_offset) < 256);
 565
 566       /* check whether next element is consecutive to this one */
 567       nonconsecutive = (idx == (num_elements - 1)) ||
 568                        elements[idx + 1].vertex_buffer_index != buffer_idx ||
 569                        end_offset != elements[idx + 1].src_offset;
 570
 571       format_type = translate_vertex_format_type(elements[idx].src_format);
 572       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 573
 574       assert(format_type != ETNA_NO_MATCH);
 575       assert(normalize != ETNA_NO_MATCH);
 576
 577       if (ctx->specs.halti < 5) {
 578          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 579             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 580             format_type |
 581             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 582             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 583             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) |
 584             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 585             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 586       } else { /* HALTI5 spread vertex attrib config over two registers */
 587          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 588             format_type |
 589             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 590             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 591             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) |
 592             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 593          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 594             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 595             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 596       }
 597
 598       if (util_format_is_pure_integer(elements[idx].src_format))
 599          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
 600       else
 601          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
 602
 603       /* instance_divisor is part of elements state but should be the same for all buffers */
 604       if (buffer_mask & 1 << buffer_idx)
 605          assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor);
 606       else
 607          cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor;
 608
 609       buffer_mask |= 1 << buffer_idx;
 610       cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1);
 611    }
 612
 613    return cs;
 614 }
 615
 616 static void
 617 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 618 {
 619    FREE(ve);
 620 }
 621
 622 static void
 623 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 624 {
 625    struct etna_context *ctx = etna_context(pctx);
 626
 627    ctx->vertex_elements = ve;
 628    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 629 }
 630
 631 static bool
 632 etna_update_ts_config(struct etna_context *ctx)
 633 {
 634    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 635
 636    if (ctx->framebuffer_s.nr_cbufs > 0) {
 637       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 638
 639       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 640          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 641       } else {
 642          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 643       }
 644    }
 645
 646    if (ctx->framebuffer_s.zsbuf) {
 647       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 648
 649       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 650          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 651       } else {
 652          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 653       }
 654    }
 655
 656    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 657        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 658       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 659       ctx->dirty |= ETNA_DIRTY_TS;
 660    }
 661
 662    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 663
 664    return true;
 665 }
 666
 667 struct etna_state_updater {
 668    bool (*update)(struct etna_context *ctx);
 669    uint32_t dirty;
 670 };
 671
 672 static const struct etna_state_updater etna_state_updates[] = {
 673    {
 674       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 675    },
 676    {
 677       etna_shader_link, ETNA_DIRTY_SHADER,
 678    },
 679    {
 680       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 681    },
 682    {
 683       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 684    },
 685    {
 686       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 687    }
 688 };
 689
 690 bool
 691 etna_state_update(struct etna_context *ctx)
 692 {
 693    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 694       if (ctx->dirty & etna_state_updates[i].dirty)
 695          if (!etna_state_updates[i].update(ctx))
 696             return false;
 697
 698    return true;
 699 }
 700
 701 void
 702 etna_state_init(struct pipe_context *pctx)
 703 {
 704    pctx->set_blend_color = etna_set_blend_color;
 705    pctx->set_stencil_ref = etna_set_stencil_ref;
 706    pctx->set_clip_state = etna_set_clip_state;
 707    pctx->set_sample_mask = etna_set_sample_mask;
 708    pctx->set_constant_buffer = etna_set_constant_buffer;
 709    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 710    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 711    pctx->set_scissor_states = etna_set_scissor_states;
 712    pctx->set_viewport_states = etna_set_viewport_states;
 713
 714    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 715
 716    pctx->bind_blend_state = etna_blend_state_bind;
 717    pctx->delete_blend_state = etna_blend_state_delete;
 718
 719    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 720    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 721
 722    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 723    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 724
 725    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 726    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 727    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 728 }