src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_rasterizer.h"
  37 #include "etnaviv_screen.h"
  38 #include "etnaviv_shader.h"
  39 #include "etnaviv_surface.h"
  40 #include "etnaviv_translate.h"
  41 #include "etnaviv_util.h"
  42 #include "util/u_framebuffer.h"
  43 #include "util/u_helpers.h"
  44 #include "util/u_inlines.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "util/u_upload_mgr.h"
  48
  49 static void
  50 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  51 {
  52    struct etna_context *ctx = etna_context(pctx);
  53    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  54
  55    ctx->stencil_ref_s = *sr;
  56
  57    for (unsigned i = 0; i < 2; i++) {
  58       cs->PE_STENCIL_CONFIG[i] =
  59          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  60       cs->PE_STENCIL_CONFIG_EXT[i] =
  61          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  62    }
  63    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  64 }
  65
  66 static void
  67 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  68 {
  69    /* NOOP */
  70 }
  71
  72 static void
  73 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  74 {
  75    struct etna_context *ctx = etna_context(pctx);
  76
  77    ctx->sample_mask = sample_mask;
  78    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  79 }
  80
  81 static void
  82 etna_set_constant_buffer(struct pipe_context *pctx,
  83       enum pipe_shader_type shader, uint index,
  84       const struct pipe_constant_buffer *cb)
  85 {
  86    struct etna_context *ctx = etna_context(pctx);
  87    struct etna_constbuf_state *so = &ctx->constant_buffer[shader];
  88
  89    assert(index < ETNA_MAX_CONST_BUF);
  90
  91    util_copy_constant_buffer(&so->cb[index], cb);
  92
  93    /* Note that the gallium frontends can unbind constant buffers by
  94     * passing NULL here. */
  95    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) {
  96       so->enabled_mask &= ~(1 << index);
  97       return;
  98    }
  99
 100    assert(index != 0 || cb->user_buffer != NULL);
 101
 102    if (!cb->buffer) {
 103       struct pipe_constant_buffer *cb = &so->cb[index];
 104       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 105    }
 106
 107    so->enabled_mask |= 1 << index;
 108    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 109 }
 110
 111 static void
 112 etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
 113 {
 114    struct etna_resource *to = base, *from = base;
 115
 116    if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
 117       from = etna_resource(base->texture);
 118
 119    if (base->render)
 120       to = etna_resource(base->render);
 121
 122    if ((to != from) && etna_resource_older(to, from)) {
 123       etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
 124       to->seqno = from->seqno;
 125    }
 126 }
 127
 128 static void
 129 etna_set_framebuffer_state(struct pipe_context *pctx,
 130       const struct pipe_framebuffer_state *fb)
 131 {
 132    struct etna_context *ctx = etna_context(pctx);
 133    struct etna_screen *screen = ctx->screen;
 134    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 135    int nr_samples_color = -1;
 136    int nr_samples_depth = -1;
 137
 138    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 139    uint32_t ts_mem_config = 0;
 140    uint32_t pe_mem_config = 0;
 141    uint32_t pe_logic_op = 0;
 142
 143    if (fb->nr_cbufs > 0) { /* at least one color buffer? */
 144       struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
 145       struct etna_resource *res = etna_resource(cbuf->base.texture);
 146       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 147       uint32_t fmt = translate_pe_format(cbuf->base.format);
 148
 149       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 150       etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
 151
 152       if (fmt >= PE_FORMAT_R16F)
 153           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
 154                                 VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
 155       else
 156           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
 157
 158       cs->PE_COLOR_FORMAT |=
 159          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 160          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 161          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 162          COND(color_supertiled && screen->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 163       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 164        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 165        * but only if we set the bits above. */
 166       /* merged with depth_stencil_alpha */
 167       if ((cbuf->surf.offset & 63) ||
 168           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 169          /* XXX Must make temporary surface here.
 170           * Need the same mechanism on gc2000 when we want to do mipmap
 171           * generation by
 172           * rendering to levels > 1 due to multitiled / tiled conversion. */
 173          BUG("Alignment error, trying to render to offset %08x with tile "
 174              "stride %i",
 175              cbuf->surf.offset, cbuf->surf.stride * 4);
 176       }
 177
 178       if (screen->specs.pixel_pipes == 1) {
 179          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 180          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 181       } else {
 182          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 183          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer);
 184          for (int i = 0; i < screen->specs.pixel_pipes; i++) {
 185             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 186             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 187          }
 188       }
 189       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 190
 191       if (cbuf->surf.ts_size) {
 192          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 193          cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
 194
 195          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 196          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 197
 198          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 199          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 200
 201          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 202
 203          if (cbuf->level->ts_compress_fmt >= 0) {
 204             /* overwrite bit breaks v1/v2 compression */
 205             if (!screen->specs.v4_compression)
 206                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 207
 208             ts_mem_config |=
 209                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 210                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 211          }
 212       }
 213
 214       nr_samples_color = cbuf->base.texture->nr_samples;
 215
 216       if (util_format_is_srgb(cbuf->base.format))
 217          pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB;
 218
 219       cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
 220       cs->PS_CONTROL_EXT =
 221          VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5));
 222    } else {
 223       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 224        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 225        * color target */
 226       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 227       cs->PE_COLOR_STRIDE = 0;
 228       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 229       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 230
 231       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 232       for (int i = 0; i < screen->specs.pixel_pipes; i++)
 233          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 234    }
 235
 236    if (fb->zsbuf != NULL) {
 237       struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
 238       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 239
 240       etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
 241
 242       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 243
 244       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 245       unsigned depth_bits =
 246          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 247       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 248
 249       cs->PE_DEPTH_CONFIG =
 250          depth_format |
 251          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 252          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 253          VIVS_PE_DEPTH_CONFIG_UNK18; /* something to do with clipping? */
 254       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 255       /* merged with depth_stencil_alpha */
 256
 257       if (screen->specs.pixel_pipes == 1) {
 258          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 259          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 260       } else {
 261          for (int i = 0; i < screen->specs.pixel_pipes; i++) {
 262             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 263             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 264          }
 265       }
 266
 267       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 268       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 269       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 270
 271       if (zsbuf->surf.ts_size) {
 272          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 273
 274          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 275          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 276
 277          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 278          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 279
 280          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 281
 282          if (zsbuf->level->ts_compress_fmt >= 0) {
 283             ts_mem_config |=
 284                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 285                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 286                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 287          }
 288       }
 289
 290       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 291
 292       nr_samples_depth = zsbuf->base.texture->nr_samples;
 293    } else {
 294       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 295       cs->PE_DEPTH_ADDR.bo = NULL;
 296       cs->PE_DEPTH_STRIDE = 0;
 297       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 298       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 299
 300       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 301          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 302    }
 303
 304    /* MSAA setup */
 305    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 306        nr_samples_depth != nr_samples_color) {
 307       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 308           nr_samples_color, nr_samples_depth);
 309    }
 310
 311    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 312    case 0:
 313    case 1: /* Are 0 and 1 samples allowed? */
 314       cs->GL_MULTI_SAMPLE_CONFIG =
 315          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 316       cs->msaa_mode = false;
 317       break;
 318    case 2:
 319       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 320       cs->msaa_mode = true; /* Add input to PS */
 321       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 322       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 323       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 324       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 325       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 326       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 327       break;
 328    case 4:
 329       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 330       cs->msaa_mode = true; /* Add input to PS */
 331       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 332       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 333       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 334       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 335       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 336       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 337       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 338       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 339       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 340       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 341       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 342       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 343       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 344       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 345       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 346       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 347       break;
 348    }
 349
 350    cs->TS_MEM_CONFIG = ts_mem_config;
 351    cs->PE_MEM_CONFIG = pe_mem_config;
 352
 353    /* Single buffer setup. There is only one switch for this, not a separate
 354     * one per color buffer / depth buffer. To keep the logic simple always use
 355     * single buffer when this feature is available.
 356     * note: the blob will use 2 in some situations, figure out why?
 357     */
 358    pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(screen->specs.single_buffer ? 3 : 0);
 359    cs->PE_LOGIC_OP = pe_logic_op;
 360
 361    /* keep copy of original structure */
 362    util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
 363    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 364 }
 365
 366 static void
 367 etna_set_polygon_stipple(struct pipe_context *pctx,
 368       const struct pipe_poly_stipple *stipple)
 369 {
 370    /* NOP */
 371 }
 372
 373 static void
 374 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 375       unsigned num_scissors, const struct pipe_scissor_state *ss)
 376 {
 377    struct etna_context *ctx = etna_context(pctx);
 378    assert(ss->minx <= ss->maxx);
 379    assert(ss->miny <= ss->maxy);
 380
 381    ctx->scissor = *ss;
 382    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 383 }
 384
 385 static void
 386 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 387       unsigned num_scissors, const struct pipe_viewport_state *vs)
 388 {
 389    struct etna_context *ctx = etna_context(pctx);
 390    struct compiled_viewport_state *cs = &ctx->viewport;
 391
 392    ctx->viewport_s = *vs;
 393    /**
 394     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 395     * -1..1 to 0..1.
 396     * scaling and translation to 0..1 already happened, so remove that
 397     *
 398     * z' = (z * 2 - 1) * scale + translate
 399     *    = z * (2 * scale) + (translate - scale)
 400     *
 401     * scale' = 2 * scale
 402     * translate' = translate - scale
 403     */
 404
 405    /* must be fixp as v4 state deltas assume it is */
 406    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 407    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 408    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 409    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 410    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 411    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 412
 413    /* Compute scissor rectangle (fixp) from viewport.
 414     * Make sure left is always < right and top always < bottom.
 415     */
 416    cs->SE_SCISSOR_LEFT = MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f);
 417    cs->SE_SCISSOR_TOP = MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f);
 418    cs->SE_SCISSOR_RIGHT = ceilf(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 419    cs->SE_SCISSOR_BOTTOM = ceilf(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 420
 421    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 422    cs->PE_DEPTH_FAR = fui(1.0);
 423    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 424 }
 425
 426 static void
 427 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 428       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 429 {
 430    struct etna_context *ctx = etna_context(pctx);
 431    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 432
 433    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 434    so->count = util_last_bit(so->enabled_mask);
 435
 436    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 437       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 438       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 439
 440       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 441                                        etna_usermem_map */
 442
 443       if (vbi->buffer.resource) { /* GPU buffer */
 444          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 445          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 446          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 447          cs->FE_VERTEX_STREAM_CONTROL =
 448             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 449       } else {
 450          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 451          cs->FE_VERTEX_STREAM_CONTROL = 0;
 452       }
 453    }
 454
 455    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 456 }
 457
 458 static void
 459 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 460 {
 461    struct etna_context *ctx = etna_context(pctx);
 462
 463    ctx->blend = bs;
 464    ctx->dirty |= ETNA_DIRTY_BLEND;
 465 }
 466
 467 static void
 468 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 469 {
 470    FREE(bs);
 471 }
 472
 473 static void
 474 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 475 {
 476    struct etna_context *ctx = etna_context(pctx);
 477
 478    ctx->rasterizer = rs;
 479    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 480 }
 481
 482 static void
 483 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 484 {
 485    FREE(rs);
 486 }
 487
 488 static void
 489 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 490 {
 491    struct etna_context *ctx = etna_context(pctx);
 492
 493    ctx->zsa = zs;
 494    ctx->dirty |= ETNA_DIRTY_ZSA;
 495 }
 496
 497 static void
 498 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 499 {
 500    FREE(zs);
 501 }
 502
 503 /** Create vertex element states, which define a layout for fetching
 504  * vertices for rendering.
 505  */
 506 static void *
 507 etna_vertex_elements_state_create(struct pipe_context *pctx,
 508       unsigned num_elements, const struct pipe_vertex_element *elements)
 509 {
 510    struct etna_context *ctx = etna_context(pctx);
 511    struct etna_screen *screen = ctx->screen;
 512    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 513
 514    if (!cs)
 515       return NULL;
 516
 517    if (num_elements > screen->specs.vertex_max_elements) {
 518       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 519           screen->specs.vertex_max_elements);
 520       return NULL;
 521    }
 522
 523    /* XXX could minimize number of consecutive stretches here by sorting, and
 524     * permuting the inputs in shader or does Mesa do this already? */
 525
 526    cs->num_elements = num_elements;
 527
 528    unsigned start_offset = 0; /* start of current consecutive stretch */
 529    bool nonconsecutive = true; /* previous value of nonconsecutive */
 530    uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */
 531
 532    for (unsigned idx = 0; idx < num_elements; ++idx) {
 533       unsigned buffer_idx = elements[idx].vertex_buffer_index;
 534       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 535       unsigned end_offset = elements[idx].src_offset + element_size;
 536       uint32_t format_type, normalize;
 537
 538       if (nonconsecutive)
 539          start_offset = elements[idx].src_offset;
 540
 541       /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
 542       assert(buffer_idx < screen->specs.stream_count);
 543
 544       /* maximum vertex size is 256 bytes */
 545       assert(element_size != 0 && (end_offset - start_offset) < 256);
 546
 547       /* check whether next element is consecutive to this one */
 548       nonconsecutive = (idx == (num_elements - 1)) ||
 549                        elements[idx + 1].vertex_buffer_index != buffer_idx ||
 550                        end_offset != elements[idx + 1].src_offset;
 551
 552       format_type = translate_vertex_format_type(elements[idx].src_format);
 553       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 554
 555       assert(format_type != ETNA_NO_MATCH);
 556       assert(normalize != ETNA_NO_MATCH);
 557
 558       if (screen->specs.halti < 5) {
 559          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 560             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 561             format_type |
 562             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 563             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 564             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) |
 565             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 566             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 567       } else { /* HALTI5 spread vertex attrib config over two registers */
 568          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 569             format_type |
 570             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 571             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 572             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) |
 573             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 574          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 575             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 576             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 577       }
 578
 579       if (util_format_is_pure_integer(elements[idx].src_format))
 580          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
 581       else
 582          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
 583
 584       /* instance_divisor is part of elements state but should be the same for all buffers */
 585       if (buffer_mask & 1 << buffer_idx)
 586          assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor);
 587       else
 588          cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor;
 589
 590       buffer_mask |= 1 << buffer_idx;
 591       cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1);
 592    }
 593
 594    return cs;
 595 }
 596
 597 static void
 598 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 599 {
 600    FREE(ve);
 601 }
 602
 603 static void
 604 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 605 {
 606    struct etna_context *ctx = etna_context(pctx);
 607
 608    ctx->vertex_elements = ve;
 609    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 610 }
 611
 612 static bool
 613 etna_update_ts_config(struct etna_context *ctx)
 614 {
 615    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 616
 617    if (ctx->framebuffer_s.nr_cbufs > 0) {
 618       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 619
 620       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 621          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 622       } else {
 623          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 624       }
 625    }
 626
 627    if (ctx->framebuffer_s.zsbuf) {
 628       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 629
 630       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 631          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 632       } else {
 633          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 634       }
 635    }
 636
 637    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 638        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 639       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 640       ctx->dirty |= ETNA_DIRTY_TS;
 641    }
 642
 643    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 644
 645    return true;
 646 }
 647
 648 static bool
 649 etna_update_clipping(struct etna_context *ctx)
 650 {
 651    const struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
 652    const struct pipe_framebuffer_state *fb = &ctx->framebuffer_s;
 653
 654    /* clip framebuffer against viewport */
 655    uint32_t scissor_left = ctx->viewport.SE_SCISSOR_LEFT;
 656    uint32_t scissor_top = ctx->viewport.SE_SCISSOR_TOP;
 657    uint32_t scissor_right = MIN2(fb->width, ctx->viewport.SE_SCISSOR_RIGHT);
 658    uint32_t scissor_bottom = MIN2(fb->height, ctx->viewport.SE_SCISSOR_BOTTOM);
 659
 660    /* clip against scissor */
 661    if (rasterizer->scissor) {
 662       scissor_left = MAX2(ctx->scissor.minx, scissor_left);
 663       scissor_top = MAX2(ctx->scissor.miny, scissor_top);
 664       scissor_right = MIN2(ctx->scissor.maxx, scissor_right);
 665       scissor_bottom = MIN2(ctx->scissor.maxy, scissor_bottom);
 666    }
 667
 668    ctx->clipping.minx = scissor_left;
 669    ctx->clipping.miny = scissor_top;
 670    ctx->clipping.maxx = scissor_right;
 671    ctx->clipping.maxy = scissor_bottom;
 672
 673    ctx->dirty |= ETNA_DIRTY_SCISSOR_CLIP;
 674
 675    return true;
 676 }
 677
 678 struct etna_state_updater {
 679    bool (*update)(struct etna_context *ctx);
 680    uint32_t dirty;
 681 };
 682
 683 static const struct etna_state_updater etna_state_updates[] = {
 684    {
 685       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 686    },
 687    {
 688       etna_shader_link, ETNA_DIRTY_SHADER,
 689    },
 690    {
 691       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 692    },
 693    {
 694       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 695    },
 696    {
 697       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 698    },
 699    {
 700       etna_update_clipping, ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
 701                             ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT,
 702    }
 703 };
 704
 705 bool
 706 etna_state_update(struct etna_context *ctx)
 707 {
 708    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 709       if (ctx->dirty & etna_state_updates[i].dirty)
 710          if (!etna_state_updates[i].update(ctx))
 711             return false;
 712
 713    return true;
 714 }
 715
 716 void
 717 etna_state_init(struct pipe_context *pctx)
 718 {
 719    pctx->set_blend_color = etna_set_blend_color;
 720    pctx->set_stencil_ref = etna_set_stencil_ref;
 721    pctx->set_clip_state = etna_set_clip_state;
 722    pctx->set_sample_mask = etna_set_sample_mask;
 723    pctx->set_constant_buffer = etna_set_constant_buffer;
 724    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 725    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 726    pctx->set_scissor_states = etna_set_scissor_states;
 727    pctx->set_viewport_states = etna_set_viewport_states;
 728
 729    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 730
 731    pctx->bind_blend_state = etna_blend_state_bind;
 732    pctx->delete_blend_state = etna_blend_state_delete;
 733
 734    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 735    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 736
 737    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 738    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 739
 740    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 741    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 742    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 743 }