src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_upload_mgr.h"
  46
  47 static void
  48 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  49 {
  50    struct etna_context *ctx = etna_context(pctx);
  51    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  52
  53    ctx->stencil_ref_s = *sr;
  54
  55    for (unsigned i = 0; i < 2; i++) {
  56       cs->PE_STENCIL_CONFIG[i] =
  57          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  58       cs->PE_STENCIL_CONFIG_EXT[i] =
  59          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  60    }
  61    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  62 }
  63
  64 static void
  65 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  66 {
  67    /* NOOP */
  68 }
  69
  70 static void
  71 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  72 {
  73    struct etna_context *ctx = etna_context(pctx);
  74
  75    ctx->sample_mask = sample_mask;
  76    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  77 }
  78
  79 static void
  80 etna_set_constant_buffer(struct pipe_context *pctx,
  81       enum pipe_shader_type shader, uint index,
  82       const struct pipe_constant_buffer *cb)
  83 {
  84    struct etna_context *ctx = etna_context(pctx);
  85
  86    if (unlikely(index > 0)) {
  87       DBG("Unhandled buffer index %i", index);
  88       return;
  89    }
  90
  91
  92    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
  93
  94    /* Note that the state tracker can unbind constant buffers by
  95     * passing NULL here. */
  96    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  97       return;
  98
  99    /* there is no support for ARB_uniform_buffer_object */
 100    assert(cb->buffer == NULL && cb->user_buffer != NULL);
 101
 102    if (!cb->buffer) {
 103       struct pipe_constant_buffer *cb = &ctx->constant_buffer[shader];
 104       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 105    }
 106
 107    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 108 }
 109
 110 static void
 111 etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
 112 {
 113    struct etna_resource *to = base, *from = base;
 114
 115    if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
 116       from = etna_resource(base->texture);
 117
 118    if (base->render)
 119       to = etna_resource(base->render);
 120
 121    if ((to != from) && etna_resource_older(to, from)) {
 122       etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
 123       to->seqno = from->seqno;
 124    }
 125 }
 126
 127 static void
 128 etna_set_framebuffer_state(struct pipe_context *pctx,
 129       const struct pipe_framebuffer_state *sv)
 130 {
 131    struct etna_context *ctx = etna_context(pctx);
 132    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 133    int nr_samples_color = -1;
 134    int nr_samples_depth = -1;
 135
 136    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 137    uint32_t ts_mem_config = 0;
 138    uint32_t pe_mem_config = 0;
 139
 140    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 141       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 142       struct etna_resource *res = etna_resource(cbuf->base.texture);
 143       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 144
 145       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 146       etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
 147
 148       cs->PE_COLOR_FORMAT =
 149          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 150          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 151          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 152          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 153          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 154       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 155        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 156        * but only if we set the bits above. */
 157       /* merged with depth_stencil_alpha */
 158       if ((cbuf->surf.offset & 63) ||
 159           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 160          /* XXX Must make temporary surface here.
 161           * Need the same mechanism on gc2000 when we want to do mipmap
 162           * generation by
 163           * rendering to levels > 1 due to multitiled / tiled conversion. */
 164          BUG("Alignment error, trying to render to offset %08x with tile "
 165              "stride %i",
 166              cbuf->surf.offset, cbuf->surf.stride * 4);
 167       }
 168
 169       if (ctx->specs.pixel_pipes == 1) {
 170          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 171          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 172       } else {
 173          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 174          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 175          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 176             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 177             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 178          }
 179       }
 180       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 181
 182       if (cbuf->surf.ts_size) {
 183          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 184
 185          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 186          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 187
 188          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 189          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 190
 191          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 192
 193          if (cbuf->level->ts_compress_fmt >= 0) {
 194             /* overwrite bit breaks v1/v2 compression */
 195             if (!ctx->specs.v4_compression)
 196                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 197
 198             ts_mem_config |=
 199                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 200                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 201          }
 202       }
 203
 204       nr_samples_color = cbuf->base.texture->nr_samples;
 205    } else {
 206       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 207        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 208        * color target */
 209       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 210       cs->PE_COLOR_STRIDE = 0;
 211       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 212       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 213
 214       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 215       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 216          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 217    }
 218
 219    if (sv->zsbuf != NULL) {
 220       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 221       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 222
 223       etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
 224
 225       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 226
 227       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 228       unsigned depth_bits =
 229          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 230       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 231
 232       cs->PE_DEPTH_CONFIG =
 233          depth_format |
 234          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 235          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 236          VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
 237          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 238          ;
 239       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 240       /* merged with depth_stencil_alpha */
 241
 242       if (ctx->specs.pixel_pipes == 1) {
 243          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 244          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 245       } else {
 246          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 247             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 248             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 249          }
 250       }
 251
 252       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 253       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 254       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 255
 256       if (zsbuf->surf.ts_size) {
 257          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 258
 259          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 260          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 261
 262          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 263          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 264
 265          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 266
 267          if (zsbuf->level->ts_compress_fmt >= 0) {
 268             ts_mem_config |=
 269                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 270                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 271                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 272          }
 273       }
 274
 275       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 276
 277       nr_samples_depth = zsbuf->base.texture->nr_samples;
 278    } else {
 279       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 280       cs->PE_DEPTH_ADDR.bo = NULL;
 281       cs->PE_DEPTH_STRIDE = 0;
 282       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 283       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 284
 285       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 286          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 287    }
 288
 289    /* MSAA setup */
 290    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 291        nr_samples_depth != nr_samples_color) {
 292       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 293           nr_samples_color, nr_samples_depth);
 294    }
 295
 296    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 297    case 0:
 298    case 1: /* Are 0 and 1 samples allowed? */
 299       cs->GL_MULTI_SAMPLE_CONFIG =
 300          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 301       cs->msaa_mode = false;
 302       break;
 303    case 2:
 304       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 305       cs->msaa_mode = true; /* Add input to PS */
 306       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 307       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 308       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 309       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 310       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 311       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 312       break;
 313    case 4:
 314       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 315       cs->msaa_mode = true; /* Add input to PS */
 316       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 317       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 318       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 319       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 320       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 321       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 322       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 323       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 324       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 325       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 326       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 327       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 328       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 329       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 330       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 331       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 332       break;
 333    }
 334
 335    /* Scissor setup */
 336    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 337    cs->SE_SCISSOR_TOP = 0;
 338    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 339    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 340    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 341    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 342
 343    cs->TS_MEM_CONFIG = ts_mem_config;
 344    cs->PE_MEM_CONFIG = pe_mem_config;
 345
 346    /* Single buffer setup. There is only one switch for this, not a separate
 347     * one per color buffer / depth buffer. To keep the logic simple always use
 348     * single buffer when this feature is available.
 349     */
 350    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 351
 352    /* keep copy of original structure */
 353    util_copy_framebuffer_state(&ctx->framebuffer_s, sv);
 354    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 355 }
 356
 357 static void
 358 etna_set_polygon_stipple(struct pipe_context *pctx,
 359       const struct pipe_poly_stipple *stipple)
 360 {
 361    /* NOP */
 362 }
 363
 364 static void
 365 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 366       unsigned num_scissors, const struct pipe_scissor_state *ss)
 367 {
 368    struct etna_context *ctx = etna_context(pctx);
 369    struct compiled_scissor_state *cs = &ctx->scissor;
 370    assert(ss->minx <= ss->maxx);
 371    assert(ss->miny <= ss->maxy);
 372
 373    /* note that this state is only used when rasterizer_state->scissor is on */
 374    ctx->scissor_s = *ss;
 375    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 376    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 377    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 378    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 379    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 380    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 381
 382    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 383 }
 384
 385 static void
 386 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 387       unsigned num_scissors, const struct pipe_viewport_state *vs)
 388 {
 389    struct etna_context *ctx = etna_context(pctx);
 390    struct compiled_viewport_state *cs = &ctx->viewport;
 391
 392    ctx->viewport_s = *vs;
 393    /**
 394     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 395     * -1..1 to 0..1.
 396     * scaling and translation to 0..1 already happened, so remove that
 397     *
 398     * z' = (z * 2 - 1) * scale + translate
 399     *    = z * (2 * scale) + (translate - scale)
 400     *
 401     * scale' = 2 * scale
 402     * translate' = translate - scale
 403     */
 404
 405    /* must be fixp as v4 state deltas assume it is */
 406    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 407    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 408    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 409    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 410    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 411    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 412
 413    /* Compute scissor rectangle (fixp) from viewport.
 414     * Make sure left is always < right and top always < bottom.
 415     */
 416    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 417    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 418    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 419    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 420    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 421    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 422    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 423    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 424
 425    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 426    cs->PE_DEPTH_FAR = fui(1.0);
 427    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 428 }
 429
 430 static void
 431 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 432       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 433 {
 434    struct etna_context *ctx = etna_context(pctx);
 435    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 436
 437    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 438    so->count = util_last_bit(so->enabled_mask);
 439
 440    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 441       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 442       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 443
 444       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 445                                        etna_usermem_map */
 446
 447       if (vbi->buffer.resource) { /* GPU buffer */
 448          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 449          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 450          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 451          cs->FE_VERTEX_STREAM_CONTROL =
 452             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 453       } else {
 454          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 455          cs->FE_VERTEX_STREAM_CONTROL = 0;
 456       }
 457    }
 458
 459    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 460 }
 461
 462 static void
 463 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 464 {
 465    struct etna_context *ctx = etna_context(pctx);
 466
 467    ctx->blend = bs;
 468    ctx->dirty |= ETNA_DIRTY_BLEND;
 469 }
 470
 471 static void
 472 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 473 {
 474    FREE(bs);
 475 }
 476
 477 static void
 478 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 479 {
 480    struct etna_context *ctx = etna_context(pctx);
 481
 482    ctx->rasterizer = rs;
 483    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 484 }
 485
 486 static void
 487 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 488 {
 489    FREE(rs);
 490 }
 491
 492 static void
 493 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 494 {
 495    struct etna_context *ctx = etna_context(pctx);
 496
 497    ctx->zsa = zs;
 498    ctx->dirty |= ETNA_DIRTY_ZSA;
 499 }
 500
 501 static void
 502 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 503 {
 504    FREE(zs);
 505 }
 506
 507 /** Create vertex element states, which define a layout for fetching
 508  * vertices for rendering.
 509  */
 510 static void *
 511 etna_vertex_elements_state_create(struct pipe_context *pctx,
 512       unsigned num_elements, const struct pipe_vertex_element *elements)
 513 {
 514    struct etna_context *ctx = etna_context(pctx);
 515    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 516
 517    if (!cs)
 518       return NULL;
 519
 520    if (num_elements > ctx->specs.vertex_max_elements) {
 521       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 522           ctx->specs.vertex_max_elements);
 523       return NULL;
 524    }
 525
 526    /* XXX could minimize number of consecutive stretches here by sorting, and
 527     * permuting the inputs in shader or does Mesa do this already? */
 528
 529    /* Check that vertex element binding is compatible with hardware; thus
 530     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 531     * uses more streams than is supported, and u_vbuf should have done some
 532     * reorganization for compatibility. */
 533
 534    /* TODO: does mesa this for us? */
 535    bool incompatible = false;
 536    for (unsigned idx = 0; idx < num_elements; ++idx) {
 537       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 538          incompatible = true;
 539    }
 540
 541    cs->num_elements = num_elements;
 542    if (incompatible || num_elements == 0) {
 543       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 544       FREE(cs);
 545       return NULL;
 546    }
 547
 548    unsigned start_offset = 0; /* start of current consecutive stretch */
 549    bool nonconsecutive = true; /* previous value of nonconsecutive */
 550
 551    for (unsigned idx = 0; idx < num_elements; ++idx) {
 552       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 553       unsigned end_offset = elements[idx].src_offset + element_size;
 554       uint32_t format_type, normalize;
 555
 556       if (nonconsecutive)
 557          start_offset = elements[idx].src_offset;
 558
 559       /* maximum vertex size is 256 bytes */
 560       assert(element_size != 0 && end_offset <= 256);
 561
 562       /* check whether next element is consecutive to this one */
 563       nonconsecutive = (idx == (num_elements - 1)) ||
 564                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 565                        end_offset != elements[idx + 1].src_offset;
 566
 567       format_type = translate_vertex_format_type(elements[idx].src_format);
 568       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 569
 570       assert(format_type != ETNA_NO_MATCH);
 571       assert(normalize != ETNA_NO_MATCH);
 572
 573       if (ctx->specs.halti < 5) {
 574          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 575             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 576             format_type |
 577             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 578             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 579             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 580             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 581             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 582       } else { /* HALTI5 spread vertex attrib config over two registers */
 583          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 584             format_type |
 585             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 586             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 587             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) |
 588             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 589          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 590             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 591             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 592       }
 593       cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */
 594    }
 595
 596    return cs;
 597 }
 598
 599 static void
 600 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 601 {
 602    FREE(ve);
 603 }
 604
 605 static void
 606 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 607 {
 608    struct etna_context *ctx = etna_context(pctx);
 609
 610    ctx->vertex_elements = ve;
 611    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 612 }
 613
 614 static bool
 615 etna_update_ts_config(struct etna_context *ctx)
 616 {
 617    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 618
 619    if (ctx->framebuffer_s.nr_cbufs > 0) {
 620       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 621
 622       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 623          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 624       } else {
 625          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 626       }
 627    }
 628
 629    if (ctx->framebuffer_s.zsbuf) {
 630       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 631
 632       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 633          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 634       } else {
 635          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 636       }
 637    }
 638
 639    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 640        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 641       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 642       ctx->dirty |= ETNA_DIRTY_TS;
 643    }
 644
 645    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 646
 647    return true;
 648 }
 649
 650 struct etna_state_updater {
 651    bool (*update)(struct etna_context *ctx);
 652    uint32_t dirty;
 653 };
 654
 655 static const struct etna_state_updater etna_state_updates[] = {
 656    {
 657       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 658    },
 659    {
 660       etna_shader_link, ETNA_DIRTY_SHADER,
 661    },
 662    {
 663       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 664    },
 665    {
 666       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 667    },
 668    {
 669       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 670    }
 671 };
 672
 673 bool
 674 etna_state_update(struct etna_context *ctx)
 675 {
 676    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 677       if (ctx->dirty & etna_state_updates[i].dirty)
 678          if (!etna_state_updates[i].update(ctx))
 679             return false;
 680
 681    return true;
 682 }
 683
 684 void
 685 etna_state_init(struct pipe_context *pctx)
 686 {
 687    pctx->set_blend_color = etna_set_blend_color;
 688    pctx->set_stencil_ref = etna_set_stencil_ref;
 689    pctx->set_clip_state = etna_set_clip_state;
 690    pctx->set_sample_mask = etna_set_sample_mask;
 691    pctx->set_constant_buffer = etna_set_constant_buffer;
 692    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 693    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 694    pctx->set_scissor_states = etna_set_scissor_states;
 695    pctx->set_viewport_states = etna_set_viewport_states;
 696
 697    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 698
 699    pctx->bind_blend_state = etna_blend_state_bind;
 700    pctx->delete_blend_state = etna_blend_state_delete;
 701
 702    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 703    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 704
 705    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 706    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 707
 708    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 709    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 710    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 711 }