src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_rasterizer.h"
  37 #include "etnaviv_screen.h"
  38 #include "etnaviv_shader.h"
  39 #include "etnaviv_surface.h"
  40 #include "etnaviv_translate.h"
  41 #include "etnaviv_util.h"
  42 #include "util/u_framebuffer.h"
  43 #include "util/u_helpers.h"
  44 #include "util/u_inlines.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "util/u_upload_mgr.h"
  48
  49 static void
  50 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  51 {
  52    struct etna_context *ctx = etna_context(pctx);
  53    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  54
  55    ctx->stencil_ref_s = *sr;
  56
  57    for (unsigned i = 0; i < 2; i++) {
  58       cs->PE_STENCIL_CONFIG[i] =
  59          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  60       cs->PE_STENCIL_CONFIG_EXT[i] =
  61          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  62    }
  63    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  64 }
  65
  66 static void
  67 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  68 {
  69    /* NOOP */
  70 }
  71
  72 static void
  73 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  74 {
  75    struct etna_context *ctx = etna_context(pctx);
  76
  77    ctx->sample_mask = sample_mask;
  78    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  79 }
  80
  81 static void
  82 etna_set_constant_buffer(struct pipe_context *pctx,
  83       enum pipe_shader_type shader, uint index,
  84       const struct pipe_constant_buffer *cb)
  85 {
  86    struct etna_context *ctx = etna_context(pctx);
  87    struct etna_constbuf_state *so = &ctx->constant_buffer[shader];
  88
  89    assert(index < ETNA_MAX_CONST_BUF);
  90
  91    util_copy_constant_buffer(&so->cb[index], cb);
  92
  93    /* Note that the gallium frontends can unbind constant buffers by
  94     * passing NULL here. */
  95    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer))) {
  96       so->enabled_mask &= ~(1 << index);
  97       return;
  98    }
  99
 100    assert(index != 0 || cb->user_buffer != NULL);
 101
 102    if (!cb->buffer) {
 103       struct pipe_constant_buffer *cb = &so->cb[index];
 104       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 105    }
 106
 107    so->enabled_mask |= 1 << index;
 108    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 109 }
 110
 111 static void
 112 etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
 113 {
 114    struct etna_resource *to = base, *from = base;
 115
 116    if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
 117       from = etna_resource(base->texture);
 118
 119    if (base->render)
 120       to = etna_resource(base->render);
 121
 122    if ((to != from) && etna_resource_older(to, from)) {
 123       etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
 124       to->seqno = from->seqno;
 125    }
 126 }
 127
 128 static void
 129 etna_set_framebuffer_state(struct pipe_context *pctx,
 130       const struct pipe_framebuffer_state *fb)
 131 {
 132    struct etna_context *ctx = etna_context(pctx);
 133    struct etna_screen *screen = ctx->screen;
 134    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 135    int nr_samples_color = -1;
 136    int nr_samples_depth = -1;
 137
 138    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 139    uint32_t ts_mem_config = 0;
 140    uint32_t pe_mem_config = 0;
 141    uint32_t pe_logic_op = 0;
 142
 143    if (fb->nr_cbufs > 0) { /* at least one color buffer? */
 144       struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
 145       struct etna_resource *res = etna_resource(cbuf->base.texture);
 146       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 147       uint32_t fmt = translate_pe_format(cbuf->base.format);
 148
 149       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 150       etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
 151
 152       if (fmt >= PE_FORMAT_R16F)
 153           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
 154                                 VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
 155       else
 156           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
 157
 158       cs->PE_COLOR_FORMAT |=
 159          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 160          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 161          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 162          COND(color_supertiled && screen->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 163       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 164        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 165        * but only if we set the bits above. */
 166       /* merged with depth_stencil_alpha */
 167       if ((cbuf->surf.offset & 63) ||
 168           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 169          /* XXX Must make temporary surface here.
 170           * Need the same mechanism on gc2000 when we want to do mipmap
 171           * generation by
 172           * rendering to levels > 1 due to multitiled / tiled conversion. */
 173          BUG("Alignment error, trying to render to offset %08x with tile "
 174              "stride %i",
 175              cbuf->surf.offset, cbuf->surf.stride * 4);
 176       }
 177
 178       if (screen->specs.pixel_pipes == 1) {
 179          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 180          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 181       } else {
 182          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 183          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer);
 184          for (int i = 0; i < screen->specs.pixel_pipes; i++) {
 185             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 186             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 187          }
 188       }
 189       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 190
 191       if (cbuf->surf.ts_size) {
 192          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 193          cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
 194
 195          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 196          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 197
 198          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 199          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 200
 201          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 202
 203          if (cbuf->level->ts_compress_fmt >= 0) {
 204             /* overwrite bit breaks v1/v2 compression */
 205             if (!screen->specs.v4_compression)
 206                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 207
 208             ts_mem_config |=
 209                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 210                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 211          }
 212       }
 213
 214       nr_samples_color = cbuf->base.texture->nr_samples;
 215
 216       if (util_format_is_srgb(cbuf->base.format))
 217          pe_logic_op |= VIVS_PE_LOGIC_OP_SRGB;
 218
 219       cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0);
 220       cs->PS_CONTROL_EXT =
 221          VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5));
 222    } else {
 223       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 224        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 225        * color target */
 226       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 227       cs->PE_COLOR_STRIDE = 0;
 228       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 229       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 230
 231       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 232       for (int i = 0; i < screen->specs.pixel_pipes; i++)
 233          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 234    }
 235
 236    if (fb->zsbuf != NULL) {
 237       struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
 238       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 239
 240       etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
 241
 242       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 243
 244       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 245       unsigned depth_bits =
 246          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 247       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 248
 249       cs->PE_DEPTH_CONFIG =
 250          depth_format |
 251          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 252          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 253          VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
 254          COND(screen->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 255          ;
 256       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 257       /* merged with depth_stencil_alpha */
 258
 259       if (screen->specs.pixel_pipes == 1) {
 260          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 261          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 262       } else {
 263          for (int i = 0; i < screen->specs.pixel_pipes; i++) {
 264             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 265             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 266          }
 267       }
 268
 269       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 270       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 271       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 272
 273       if (zsbuf->surf.ts_size) {
 274          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 275
 276          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 277          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 278
 279          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 280          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 281
 282          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 283
 284          if (zsbuf->level->ts_compress_fmt >= 0) {
 285             ts_mem_config |=
 286                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 287                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 288                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 289          }
 290       }
 291
 292       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 293
 294       nr_samples_depth = zsbuf->base.texture->nr_samples;
 295    } else {
 296       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 297       cs->PE_DEPTH_ADDR.bo = NULL;
 298       cs->PE_DEPTH_STRIDE = 0;
 299       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 300       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 301
 302       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 303          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 304    }
 305
 306    /* MSAA setup */
 307    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 308        nr_samples_depth != nr_samples_color) {
 309       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 310           nr_samples_color, nr_samples_depth);
 311    }
 312
 313    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 314    case 0:
 315    case 1: /* Are 0 and 1 samples allowed? */
 316       cs->GL_MULTI_SAMPLE_CONFIG =
 317          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 318       cs->msaa_mode = false;
 319       break;
 320    case 2:
 321       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 322       cs->msaa_mode = true; /* Add input to PS */
 323       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 324       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 325       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 326       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 327       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 328       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 329       break;
 330    case 4:
 331       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 332       cs->msaa_mode = true; /* Add input to PS */
 333       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 334       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 335       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 336       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 337       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 338       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 339       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 340       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 341       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 342       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 343       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 344       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 345       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 346       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 347       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 348       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 349       break;
 350    }
 351
 352    cs->TS_MEM_CONFIG = ts_mem_config;
 353    cs->PE_MEM_CONFIG = pe_mem_config;
 354
 355    /* Single buffer setup. There is only one switch for this, not a separate
 356     * one per color buffer / depth buffer. To keep the logic simple always use
 357     * single buffer when this feature is available.
 358     * note: the blob will use 2 in some situations, figure out why?
 359     */
 360    pe_logic_op |= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(screen->specs.single_buffer ? 3 : 0);
 361    cs->PE_LOGIC_OP = pe_logic_op;
 362
 363    /* keep copy of original structure */
 364    util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
 365    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 366 }
 367
 368 static void
 369 etna_set_polygon_stipple(struct pipe_context *pctx,
 370       const struct pipe_poly_stipple *stipple)
 371 {
 372    /* NOP */
 373 }
 374
 375 static void
 376 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 377       unsigned num_scissors, const struct pipe_scissor_state *ss)
 378 {
 379    struct etna_context *ctx = etna_context(pctx);
 380    assert(ss->minx <= ss->maxx);
 381    assert(ss->miny <= ss->maxy);
 382
 383    ctx->scissor = *ss;
 384    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 385 }
 386
 387 static void
 388 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 389       unsigned num_scissors, const struct pipe_viewport_state *vs)
 390 {
 391    struct etna_context *ctx = etna_context(pctx);
 392    struct compiled_viewport_state *cs = &ctx->viewport;
 393
 394    ctx->viewport_s = *vs;
 395    /**
 396     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 397     * -1..1 to 0..1.
 398     * scaling and translation to 0..1 already happened, so remove that
 399     *
 400     * z' = (z * 2 - 1) * scale + translate
 401     *    = z * (2 * scale) + (translate - scale)
 402     *
 403     * scale' = 2 * scale
 404     * translate' = translate - scale
 405     */
 406
 407    /* must be fixp as v4 state deltas assume it is */
 408    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 409    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 410    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 411    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 412    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 413    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 414
 415    /* Compute scissor rectangle (fixp) from viewport.
 416     * Make sure left is always < right and top always < bottom.
 417     */
 418    cs->SE_SCISSOR_LEFT = MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f);
 419    cs->SE_SCISSOR_TOP = MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f);
 420    cs->SE_SCISSOR_RIGHT = ceilf(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 421    cs->SE_SCISSOR_BOTTOM = ceilf(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 422
 423    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 424    cs->PE_DEPTH_FAR = fui(1.0);
 425    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 426 }
 427
 428 static void
 429 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 430       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 431 {
 432    struct etna_context *ctx = etna_context(pctx);
 433    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 434
 435    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 436    so->count = util_last_bit(so->enabled_mask);
 437
 438    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 439       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 440       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 441
 442       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 443                                        etna_usermem_map */
 444
 445       if (vbi->buffer.resource) { /* GPU buffer */
 446          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 447          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 448          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 449          cs->FE_VERTEX_STREAM_CONTROL =
 450             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 451       } else {
 452          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 453          cs->FE_VERTEX_STREAM_CONTROL = 0;
 454       }
 455    }
 456
 457    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 458 }
 459
 460 static void
 461 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 462 {
 463    struct etna_context *ctx = etna_context(pctx);
 464
 465    ctx->blend = bs;
 466    ctx->dirty |= ETNA_DIRTY_BLEND;
 467 }
 468
 469 static void
 470 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 471 {
 472    FREE(bs);
 473 }
 474
 475 static void
 476 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 477 {
 478    struct etna_context *ctx = etna_context(pctx);
 479
 480    ctx->rasterizer = rs;
 481    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 482 }
 483
 484 static void
 485 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 486 {
 487    FREE(rs);
 488 }
 489
 490 static void
 491 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 492 {
 493    struct etna_context *ctx = etna_context(pctx);
 494
 495    ctx->zsa = zs;
 496    ctx->dirty |= ETNA_DIRTY_ZSA;
 497 }
 498
 499 static void
 500 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 501 {
 502    FREE(zs);
 503 }
 504
 505 /** Create vertex element states, which define a layout for fetching
 506  * vertices for rendering.
 507  */
 508 static void *
 509 etna_vertex_elements_state_create(struct pipe_context *pctx,
 510       unsigned num_elements, const struct pipe_vertex_element *elements)
 511 {
 512    struct etna_context *ctx = etna_context(pctx);
 513    struct etna_screen *screen = ctx->screen;
 514    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 515
 516    if (!cs)
 517       return NULL;
 518
 519    if (num_elements > screen->specs.vertex_max_elements) {
 520       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 521           screen->specs.vertex_max_elements);
 522       return NULL;
 523    }
 524
 525    /* XXX could minimize number of consecutive stretches here by sorting, and
 526     * permuting the inputs in shader or does Mesa do this already? */
 527
 528    cs->num_elements = num_elements;
 529
 530    unsigned start_offset = 0; /* start of current consecutive stretch */
 531    bool nonconsecutive = true; /* previous value of nonconsecutive */
 532    uint32_t buffer_mask = 0; /* mask of buffer_idx already seen */
 533
 534    for (unsigned idx = 0; idx < num_elements; ++idx) {
 535       unsigned buffer_idx = elements[idx].vertex_buffer_index;
 536       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 537       unsigned end_offset = elements[idx].src_offset + element_size;
 538       uint32_t format_type, normalize;
 539
 540       if (nonconsecutive)
 541          start_offset = elements[idx].src_offset;
 542
 543       /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
 544       assert(buffer_idx < screen->specs.stream_count);
 545
 546       /* maximum vertex size is 256 bytes */
 547       assert(element_size != 0 && (end_offset - start_offset) < 256);
 548
 549       /* check whether next element is consecutive to this one */
 550       nonconsecutive = (idx == (num_elements - 1)) ||
 551                        elements[idx + 1].vertex_buffer_index != buffer_idx ||
 552                        end_offset != elements[idx + 1].src_offset;
 553
 554       format_type = translate_vertex_format_type(elements[idx].src_format);
 555       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 556
 557       assert(format_type != ETNA_NO_MATCH);
 558       assert(normalize != ETNA_NO_MATCH);
 559
 560       if (screen->specs.halti < 5) {
 561          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 562             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 563             format_type |
 564             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 565             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 566             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx) |
 567             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 568             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 569       } else { /* HALTI5 spread vertex attrib config over two registers */
 570          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 571             format_type |
 572             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 573             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 574             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx) |
 575             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 576          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 577             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 578             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 579       }
 580
 581       if (util_format_is_pure_integer(elements[idx].src_format))
 582          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
 583       else
 584          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
 585
 586       /* instance_divisor is part of elements state but should be the same for all buffers */
 587       if (buffer_mask & 1 << buffer_idx)
 588          assert(cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] == elements[idx].instance_divisor);
 589       else
 590          cs->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[buffer_idx] = elements[idx].instance_divisor;
 591
 592       buffer_mask |= 1 << buffer_idx;
 593       cs->num_buffers = MAX2(cs->num_buffers, buffer_idx + 1);
 594    }
 595
 596    return cs;
 597 }
 598
 599 static void
 600 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 601 {
 602    FREE(ve);
 603 }
 604
 605 static void
 606 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 607 {
 608    struct etna_context *ctx = etna_context(pctx);
 609
 610    ctx->vertex_elements = ve;
 611    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 612 }
 613
 614 static bool
 615 etna_update_ts_config(struct etna_context *ctx)
 616 {
 617    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 618
 619    if (ctx->framebuffer_s.nr_cbufs > 0) {
 620       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 621
 622       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 623          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 624       } else {
 625          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 626       }
 627    }
 628
 629    if (ctx->framebuffer_s.zsbuf) {
 630       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 631
 632       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 633          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 634       } else {
 635          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 636       }
 637    }
 638
 639    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 640        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 641       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 642       ctx->dirty |= ETNA_DIRTY_TS;
 643    }
 644
 645    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 646
 647    return true;
 648 }
 649
 650 static bool
 651 etna_update_clipping(struct etna_context *ctx)
 652 {
 653    const struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
 654    const struct pipe_framebuffer_state *fb = &ctx->framebuffer_s;
 655
 656    /* clip framebuffer against viewport */
 657    uint32_t scissor_left = ctx->viewport.SE_SCISSOR_LEFT;
 658    uint32_t scissor_top = ctx->viewport.SE_SCISSOR_TOP;
 659    uint32_t scissor_right = MIN2(fb->width, ctx->viewport.SE_SCISSOR_RIGHT);
 660    uint32_t scissor_bottom = MIN2(fb->height, ctx->viewport.SE_SCISSOR_BOTTOM);
 661
 662    /* clip against scissor */
 663    if (rasterizer->scissor) {
 664       scissor_left = MAX2(ctx->scissor.minx, scissor_left);
 665       scissor_top = MAX2(ctx->scissor.miny, scissor_top);
 666       scissor_right = MIN2(ctx->scissor.maxx, scissor_right);
 667       scissor_bottom = MIN2(ctx->scissor.maxy, scissor_bottom);
 668    }
 669
 670    ctx->clipping.minx = scissor_left;
 671    ctx->clipping.miny = scissor_top;
 672    ctx->clipping.maxx = scissor_right;
 673    ctx->clipping.maxy = scissor_bottom;
 674
 675    ctx->dirty |= ETNA_DIRTY_SCISSOR_CLIP;
 676
 677    return true;
 678 }
 679
 680 struct etna_state_updater {
 681    bool (*update)(struct etna_context *ctx);
 682    uint32_t dirty;
 683 };
 684
 685 static const struct etna_state_updater etna_state_updates[] = {
 686    {
 687       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 688    },
 689    {
 690       etna_shader_link, ETNA_DIRTY_SHADER,
 691    },
 692    {
 693       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 694    },
 695    {
 696       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 697    },
 698    {
 699       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 700    },
 701    {
 702       etna_update_clipping, ETNA_DIRTY_SCISSOR | ETNA_DIRTY_FRAMEBUFFER |
 703                             ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_VIEWPORT,
 704    }
 705 };
 706
 707 bool
 708 etna_state_update(struct etna_context *ctx)
 709 {
 710    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 711       if (ctx->dirty & etna_state_updates[i].dirty)
 712          if (!etna_state_updates[i].update(ctx))
 713             return false;
 714
 715    return true;
 716 }
 717
 718 void
 719 etna_state_init(struct pipe_context *pctx)
 720 {
 721    pctx->set_blend_color = etna_set_blend_color;
 722    pctx->set_stencil_ref = etna_set_stencil_ref;
 723    pctx->set_clip_state = etna_set_clip_state;
 724    pctx->set_sample_mask = etna_set_sample_mask;
 725    pctx->set_constant_buffer = etna_set_constant_buffer;
 726    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 727    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 728    pctx->set_scissor_states = etna_set_scissor_states;
 729    pctx->set_viewport_states = etna_set_viewport_states;
 730
 731    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 732
 733    pctx->bind_blend_state = etna_blend_state_bind;
 734    pctx->delete_blend_state = etna_blend_state_delete;
 735
 736    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 737    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 738
 739    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 740    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 741
 742    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 743    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 744    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 745 }