2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
28 #include "etnaviv_state.h"
30 #include "hw/common.xml.h"
32 #include "etnaviv_blend.h"
33 #include "etnaviv_clear_blit.h"
34 #include "etnaviv_context.h"
35 #include "etnaviv_format.h"
36 #include "etnaviv_screen.h"
37 #include "etnaviv_shader.h"
38 #include "etnaviv_surface.h"
39 #include "etnaviv_translate.h"
40 #include "etnaviv_util.h"
41 #include "util/u_framebuffer.h"
42 #include "util/u_helpers.h"
43 #include "util/u_inlines.h"
44 #include "util/u_math.h"
45 #include "util/u_memory.h"
46 #include "util/u_upload_mgr.h"
49 etna_set_stencil_ref(struct pipe_context
*pctx
, const struct pipe_stencil_ref
*sr
)
51 struct etna_context
*ctx
= etna_context(pctx
);
52 struct compiled_stencil_ref
*cs
= &ctx
->stencil_ref
;
54 ctx
->stencil_ref_s
= *sr
;
56 for (unsigned i
= 0; i
< 2; i
++) {
57 cs
->PE_STENCIL_CONFIG
[i
] =
58 VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr
->ref_value
[i
]);
59 cs
->PE_STENCIL_CONFIG_EXT
[i
] =
60 VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr
->ref_value
[!i
]);
62 ctx
->dirty
|= ETNA_DIRTY_STENCIL_REF
;
66 etna_set_clip_state(struct pipe_context
*pctx
, const struct pipe_clip_state
*pcs
)
72 etna_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
74 struct etna_context
*ctx
= etna_context(pctx
);
76 ctx
->sample_mask
= sample_mask
;
77 ctx
->dirty
|= ETNA_DIRTY_SAMPLE_MASK
;
81 etna_set_constant_buffer(struct pipe_context
*pctx
,
82 enum pipe_shader_type shader
, uint index
,
83 const struct pipe_constant_buffer
*cb
)
85 struct etna_context
*ctx
= etna_context(pctx
);
86 struct etna_constbuf_state
*so
= &ctx
->constant_buffer
[shader
];
88 assert(index
< ETNA_MAX_CONST_BUF
);
90 util_copy_constant_buffer(&so
->cb
[index
], cb
);
92 /* Note that the state tracker can unbind constant buffers by
93 * passing NULL here. */
94 if (unlikely(!cb
|| (!cb
->buffer
&& !cb
->user_buffer
))) {
95 so
->enabled_mask
&= ~(1 << index
);
99 assert(index
!= 0 || cb
->user_buffer
!= NULL
);
102 struct pipe_constant_buffer
*cb
= &so
->cb
[index
];
103 u_upload_data(pctx
->const_uploader
, 0, cb
->buffer_size
, 16, cb
->user_buffer
, &cb
->buffer_offset
, &cb
->buffer
);
106 so
->enabled_mask
|= 1 << index
;
107 ctx
->dirty
|= ETNA_DIRTY_CONSTBUF
;
111 etna_update_render_resource(struct pipe_context
*pctx
, struct etna_resource
*base
)
113 struct etna_resource
*to
= base
, *from
= base
;
115 if (base
->texture
&& etna_resource_newer(etna_resource(base
->texture
), base
))
116 from
= etna_resource(base
->texture
);
119 to
= etna_resource(base
->render
);
121 if ((to
!= from
) && etna_resource_older(to
, from
)) {
122 etna_copy_resource(pctx
, &to
->base
, &from
->base
, 0, base
->base
.last_level
);
123 to
->seqno
= from
->seqno
;
128 etna_set_framebuffer_state(struct pipe_context
*pctx
,
129 const struct pipe_framebuffer_state
*fb
)
131 struct etna_context
*ctx
= etna_context(pctx
);
132 struct etna_screen
*screen
= ctx
->screen
;
133 struct compiled_framebuffer_state
*cs
= &ctx
->framebuffer
;
134 int nr_samples_color
= -1;
135 int nr_samples_depth
= -1;
137 /* Set up TS as well. Warning: this state is used by both the RS and PE */
138 uint32_t ts_mem_config
= 0;
139 uint32_t pe_mem_config
= 0;
140 uint32_t pe_logic_op
= 0;
142 if (fb
->nr_cbufs
> 0) { /* at least one color buffer? */
143 struct etna_surface
*cbuf
= etna_surface(fb
->cbufs
[0]);
144 struct etna_resource
*res
= etna_resource(cbuf
->base
.texture
);
145 bool color_supertiled
= (res
->layout
& ETNA_LAYOUT_BIT_SUPER
) != 0;
146 uint32_t fmt
= translate_pe_format(cbuf
->base
.format
);
148 assert(res
->layout
& ETNA_LAYOUT_BIT_TILE
); /* Cannot render to linear surfaces */
149 etna_update_render_resource(pctx
, etna_resource(cbuf
->prsc
));
151 if (fmt
>= PE_FORMAT_R16F
)
152 cs
->PE_COLOR_FORMAT
= VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt
) |
153 VIVS_PE_COLOR_FORMAT_FORMAT_MASK
;
155 cs
->PE_COLOR_FORMAT
= VIVS_PE_COLOR_FORMAT_FORMAT(fmt
);
157 cs
->PE_COLOR_FORMAT
|=
158 VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK
|
159 VIVS_PE_COLOR_FORMAT_OVERWRITE
|
160 COND(color_supertiled
, VIVS_PE_COLOR_FORMAT_SUPER_TILED
) |
161 COND(color_supertiled
&& screen
->specs
.halti
>= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW
);
162 /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
163 * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
164 * but only if we set the bits above. */
165 /* merged with depth_stencil_alpha */
166 if ((cbuf
->surf
.offset
& 63) ||
167 (((cbuf
->surf
.stride
* 4) & 63) && cbuf
->surf
.height
> 4)) {
168 /* XXX Must make temporary surface here.
169 * Need the same mechanism on gc2000 when we want to do mipmap
171 * rendering to levels > 1 due to multitiled / tiled conversion. */
172 BUG("Alignment error, trying to render to offset %08x with tile "
174 cbuf
->surf
.offset
, cbuf
->surf
.stride
* 4);
177 if (screen
->specs
.pixel_pipes
== 1) {
178 cs
->PE_COLOR_ADDR
= cbuf
->reloc
[0];
179 cs
->PE_COLOR_ADDR
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
181 /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
182 assert((res
->layout
& ETNA_LAYOUT_BIT_MULTI
) || screen
->specs
.single_buffer
);
183 for (int i
= 0; i
< screen
->specs
.pixel_pipes
; i
++) {
184 cs
->PE_PIPE_COLOR_ADDR
[i
] = cbuf
->reloc
[i
];
185 cs
->PE_PIPE_COLOR_ADDR
[i
].flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
188 cs
->PE_COLOR_STRIDE
= cbuf
->surf
.stride
;
190 if (cbuf
->surf
.ts_size
) {
191 cs
->TS_COLOR_CLEAR_VALUE
= cbuf
->level
->clear_value
;
192 cs
->TS_COLOR_CLEAR_VALUE_EXT
= cbuf
->level
->clear_value
>> 32;
194 cs
->TS_COLOR_STATUS_BASE
= cbuf
->ts_reloc
;
195 cs
->TS_COLOR_STATUS_BASE
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
197 cs
->TS_COLOR_SURFACE_BASE
= cbuf
->reloc
[0];
198 cs
->TS_COLOR_SURFACE_BASE
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
200 pe_mem_config
|= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf
->level
->ts_mode
);
202 if (cbuf
->level
->ts_compress_fmt
>= 0) {
203 /* overwrite bit breaks v1/v2 compression */
204 if (!screen
->specs
.v4_compression
)
205 cs
->PE_COLOR_FORMAT
&= ~VIVS_PE_COLOR_FORMAT_OVERWRITE
;
208 VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION
|
209 VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf
->level
->ts_compress_fmt
);
213 nr_samples_color
= cbuf
->base
.texture
->nr_samples
;
215 if (util_format_is_srgb(cbuf
->base
.format
))
216 pe_logic_op
|= VIVS_PE_LOGIC_OP_SRGB
;
218 cs
->PS_CONTROL
= COND(util_format_is_unorm(cbuf
->base
.format
), VIVS_PS_CONTROL_SATURATE_RT0
);
220 VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf
->base
.format
, screen
->specs
.halti
>= 5));
222 /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
223 * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
225 cs
->PE_COLOR_FORMAT
= VIVS_PE_COLOR_FORMAT_OVERWRITE
;
226 cs
->PE_COLOR_STRIDE
= 0;
227 cs
->TS_COLOR_STATUS_BASE
.bo
= NULL
;
228 cs
->TS_COLOR_SURFACE_BASE
.bo
= NULL
;
230 cs
->PE_COLOR_ADDR
= ctx
->dummy_rt_reloc
;
231 for (int i
= 0; i
< screen
->specs
.pixel_pipes
; i
++)
232 cs
->PE_PIPE_COLOR_ADDR
[i
] = ctx
->dummy_rt_reloc
;
235 if (fb
->zsbuf
!= NULL
) {
236 struct etna_surface
*zsbuf
= etna_surface(fb
->zsbuf
);
237 struct etna_resource
*res
= etna_resource(zsbuf
->base
.texture
);
239 etna_update_render_resource(pctx
, etna_resource(zsbuf
->prsc
));
241 assert(res
->layout
&ETNA_LAYOUT_BIT_TILE
); /* Cannot render to linear surfaces */
243 uint32_t depth_format
= translate_depth_format(zsbuf
->base
.format
);
244 unsigned depth_bits
=
245 depth_format
== VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16
? 16 : 24;
246 bool depth_supertiled
= (res
->layout
& ETNA_LAYOUT_BIT_SUPER
) != 0;
248 cs
->PE_DEPTH_CONFIG
=
250 COND(depth_supertiled
, VIVS_PE_DEPTH_CONFIG_SUPER_TILED
) |
251 VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z
|
252 VIVS_PE_DEPTH_CONFIG_UNK18
| /* something to do with clipping? */
253 COND(screen
->specs
.halti
>= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS
) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
255 /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
256 /* merged with depth_stencil_alpha */
258 if (screen
->specs
.pixel_pipes
== 1) {
259 cs
->PE_DEPTH_ADDR
= zsbuf
->reloc
[0];
260 cs
->PE_DEPTH_ADDR
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
262 for (int i
= 0; i
< screen
->specs
.pixel_pipes
; i
++) {
263 cs
->PE_PIPE_DEPTH_ADDR
[i
] = zsbuf
->reloc
[i
];
264 cs
->PE_PIPE_DEPTH_ADDR
[i
].flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
268 cs
->PE_DEPTH_STRIDE
= zsbuf
->surf
.stride
;
269 cs
->PE_HDEPTH_CONTROL
= VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED
;
270 cs
->PE_DEPTH_NORMALIZE
= fui(exp2f(depth_bits
) - 1.0f
);
272 if (zsbuf
->surf
.ts_size
) {
273 cs
->TS_DEPTH_CLEAR_VALUE
= zsbuf
->level
->clear_value
;
275 cs
->TS_DEPTH_STATUS_BASE
= zsbuf
->ts_reloc
;
276 cs
->TS_DEPTH_STATUS_BASE
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
278 cs
->TS_DEPTH_SURFACE_BASE
= zsbuf
->reloc
[0];
279 cs
->TS_DEPTH_SURFACE_BASE
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
281 pe_mem_config
|= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf
->level
->ts_mode
);
283 if (zsbuf
->level
->ts_compress_fmt
>= 0) {
285 VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION
|
286 COND(zsbuf
->level
->ts_compress_fmt
== COMPRESSION_FORMAT_D24S8
,
287 VIVS_TS_MEM_CONFIG_STENCIL_ENABLE
);
291 ts_mem_config
|= COND(depth_bits
== 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP
);
293 nr_samples_depth
= zsbuf
->base
.texture
->nr_samples
;
295 cs
->PE_DEPTH_CONFIG
= VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE
;
296 cs
->PE_DEPTH_ADDR
.bo
= NULL
;
297 cs
->PE_DEPTH_STRIDE
= 0;
298 cs
->TS_DEPTH_STATUS_BASE
.bo
= NULL
;
299 cs
->TS_DEPTH_SURFACE_BASE
.bo
= NULL
;
301 for (int i
= 0; i
< ETNA_MAX_PIXELPIPES
; i
++)
302 cs
->PE_PIPE_DEPTH_ADDR
[i
].bo
= NULL
;
306 if (nr_samples_depth
!= -1 && nr_samples_color
!= -1 &&
307 nr_samples_depth
!= nr_samples_color
) {
308 BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
309 nr_samples_color
, nr_samples_depth
);
312 switch (MAX2(nr_samples_depth
, nr_samples_color
)) {
314 case 1: /* Are 0 and 1 samples allowed? */
315 cs
->GL_MULTI_SAMPLE_CONFIG
=
316 VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE
;
317 cs
->msaa_mode
= false;
320 cs
->GL_MULTI_SAMPLE_CONFIG
= VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X
;
321 cs
->msaa_mode
= true; /* Add input to PS */
322 cs
->RA_MULTISAMPLE_UNK00E04
= 0x0;
323 cs
->RA_MULTISAMPLE_UNK00E10
[0] = 0x0000aa22;
324 cs
->RA_CENTROID_TABLE
[0] = 0x66aa2288;
325 cs
->RA_CENTROID_TABLE
[1] = 0x88558800;
326 cs
->RA_CENTROID_TABLE
[2] = 0x88881100;
327 cs
->RA_CENTROID_TABLE
[3] = 0x33888800;
330 cs
->GL_MULTI_SAMPLE_CONFIG
= VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X
;
331 cs
->msaa_mode
= true; /* Add input to PS */
332 cs
->RA_MULTISAMPLE_UNK00E04
= 0x0;
333 cs
->RA_MULTISAMPLE_UNK00E10
[0] = 0xeaa26e26;
334 cs
->RA_MULTISAMPLE_UNK00E10
[1] = 0xe6ae622a;
335 cs
->RA_MULTISAMPLE_UNK00E10
[2] = 0xaaa22a22;
336 cs
->RA_CENTROID_TABLE
[0] = 0x4a6e2688;
337 cs
->RA_CENTROID_TABLE
[1] = 0x888888a2;
338 cs
->RA_CENTROID_TABLE
[2] = 0x888888ea;
339 cs
->RA_CENTROID_TABLE
[3] = 0x888888c6;
340 cs
->RA_CENTROID_TABLE
[4] = 0x46622a88;
341 cs
->RA_CENTROID_TABLE
[5] = 0x888888ae;
342 cs
->RA_CENTROID_TABLE
[6] = 0x888888e6;
343 cs
->RA_CENTROID_TABLE
[7] = 0x888888ca;
344 cs
->RA_CENTROID_TABLE
[8] = 0x262a2288;
345 cs
->RA_CENTROID_TABLE
[9] = 0x886688a2;
346 cs
->RA_CENTROID_TABLE
[10] = 0x888866aa;
347 cs
->RA_CENTROID_TABLE
[11] = 0x668888a6;
352 cs
->SE_SCISSOR_LEFT
= 0; /* affected by rasterizer and scissor state as well */
353 cs
->SE_SCISSOR_TOP
= 0;
354 cs
->SE_SCISSOR_RIGHT
= (fb
->width
<< 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT
;
355 cs
->SE_SCISSOR_BOTTOM
= (fb
->height
<< 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM
;
356 cs
->SE_CLIP_RIGHT
= (fb
->width
<< 16) + ETNA_SE_CLIP_MARGIN_RIGHT
;
357 cs
->SE_CLIP_BOTTOM
= (fb
->height
<< 16) + ETNA_SE_CLIP_MARGIN_BOTTOM
;
359 cs
->TS_MEM_CONFIG
= ts_mem_config
;
360 cs
->PE_MEM_CONFIG
= pe_mem_config
;
362 /* Single buffer setup. There is only one switch for this, not a separate
363 * one per color buffer / depth buffer. To keep the logic simple always use
364 * single buffer when this feature is available.
365 * note: the blob will use 2 in some situations, figure out why?
367 pe_logic_op
|= VIVS_PE_LOGIC_OP_SINGLE_BUFFER(screen
->specs
.single_buffer
? 3 : 0);
368 cs
->PE_LOGIC_OP
= pe_logic_op
;
370 /* keep copy of original structure */
371 util_copy_framebuffer_state(&ctx
->framebuffer_s
, fb
);
372 ctx
->dirty
|= ETNA_DIRTY_FRAMEBUFFER
| ETNA_DIRTY_DERIVE_TS
;
376 etna_set_polygon_stipple(struct pipe_context
*pctx
,
377 const struct pipe_poly_stipple
*stipple
)
383 etna_set_scissor_states(struct pipe_context
*pctx
, unsigned start_slot
,
384 unsigned num_scissors
, const struct pipe_scissor_state
*ss
)
386 struct etna_context
*ctx
= etna_context(pctx
);
387 struct compiled_scissor_state
*cs
= &ctx
->scissor
;
388 assert(ss
->minx
<= ss
->maxx
);
389 assert(ss
->miny
<= ss
->maxy
);
391 /* note that this state is only used when rasterizer_state->scissor is on */
392 ctx
->scissor_s
= *ss
;
393 cs
->SE_SCISSOR_LEFT
= (ss
->minx
<< 16);
394 cs
->SE_SCISSOR_TOP
= (ss
->miny
<< 16);
395 cs
->SE_SCISSOR_RIGHT
= (ss
->maxx
<< 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT
;
396 cs
->SE_SCISSOR_BOTTOM
= (ss
->maxy
<< 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM
;
397 cs
->SE_CLIP_RIGHT
= (ss
->maxx
<< 16) + ETNA_SE_CLIP_MARGIN_RIGHT
;
398 cs
->SE_CLIP_BOTTOM
= (ss
->maxy
<< 16) + ETNA_SE_CLIP_MARGIN_BOTTOM
;
400 ctx
->dirty
|= ETNA_DIRTY_SCISSOR
;
404 etna_set_viewport_states(struct pipe_context
*pctx
, unsigned start_slot
,
405 unsigned num_scissors
, const struct pipe_viewport_state
*vs
)
407 struct etna_context
*ctx
= etna_context(pctx
);
408 struct compiled_viewport_state
*cs
= &ctx
->viewport
;
410 ctx
->viewport_s
= *vs
;
412 * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
414 * scaling and translation to 0..1 already happened, so remove that
416 * z' = (z * 2 - 1) * scale + translate
417 * = z * (2 * scale) + (translate - scale)
420 * translate' = translate - scale
423 /* must be fixp as v4 state deltas assume it is */
424 cs
->PA_VIEWPORT_SCALE_X
= etna_f32_to_fixp16(vs
->scale
[0]);
425 cs
->PA_VIEWPORT_SCALE_Y
= etna_f32_to_fixp16(vs
->scale
[1]);
426 cs
->PA_VIEWPORT_SCALE_Z
= fui(vs
->scale
[2] * 2.0f
);
427 cs
->PA_VIEWPORT_OFFSET_X
= etna_f32_to_fixp16(vs
->translate
[0]);
428 cs
->PA_VIEWPORT_OFFSET_Y
= etna_f32_to_fixp16(vs
->translate
[1]);
429 cs
->PA_VIEWPORT_OFFSET_Z
= fui(vs
->translate
[2] - vs
->scale
[2]);
431 /* Compute scissor rectangle (fixp) from viewport.
432 * Make sure left is always < right and top always < bottom.
434 cs
->SE_SCISSOR_LEFT
= etna_f32_to_fixp16(MAX2(vs
->translate
[0] - fabsf(vs
->scale
[0]), 0.0f
));
435 cs
->SE_SCISSOR_TOP
= etna_f32_to_fixp16(MAX2(vs
->translate
[1] - fabsf(vs
->scale
[1]), 0.0f
));
436 uint32_t right_fixp
= etna_f32_to_fixp16(MAX2(vs
->translate
[0] + fabsf(vs
->scale
[0]), 0.0f
));
437 uint32_t bottom_fixp
= etna_f32_to_fixp16(MAX2(vs
->translate
[1] + fabsf(vs
->scale
[1]), 0.0f
));
438 cs
->SE_SCISSOR_RIGHT
= right_fixp
+ ETNA_SE_SCISSOR_MARGIN_RIGHT
;
439 cs
->SE_SCISSOR_BOTTOM
= bottom_fixp
+ ETNA_SE_SCISSOR_MARGIN_BOTTOM
;
440 cs
->SE_CLIP_RIGHT
= right_fixp
+ ETNA_SE_CLIP_MARGIN_RIGHT
;
441 cs
->SE_CLIP_BOTTOM
= bottom_fixp
+ ETNA_SE_CLIP_MARGIN_BOTTOM
;
443 cs
->PE_DEPTH_NEAR
= fui(0.0); /* not affected if depth mode is Z (as in GL) */
444 cs
->PE_DEPTH_FAR
= fui(1.0);
445 ctx
->dirty
|= ETNA_DIRTY_VIEWPORT
;
449 etna_set_vertex_buffers(struct pipe_context
*pctx
, unsigned start_slot
,
450 unsigned num_buffers
, const struct pipe_vertex_buffer
*vb
)
452 struct etna_context
*ctx
= etna_context(pctx
);
453 struct etna_vertexbuf_state
*so
= &ctx
->vertex_buffer
;
455 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
, start_slot
, num_buffers
);
456 so
->count
= util_last_bit(so
->enabled_mask
);
458 for (unsigned idx
= start_slot
; idx
< start_slot
+ num_buffers
; ++idx
) {
459 struct compiled_set_vertex_buffer
*cs
= &so
->cvb
[idx
];
460 struct pipe_vertex_buffer
*vbi
= &so
->vb
[idx
];
462 assert(!vbi
->is_user_buffer
); /* XXX support user_buffer using
465 if (vbi
->buffer
.resource
) { /* GPU buffer */
466 cs
->FE_VERTEX_STREAM_BASE_ADDR
.bo
= etna_resource(vbi
->buffer
.resource
)->bo
;
467 cs
->FE_VERTEX_STREAM_BASE_ADDR
.offset
= vbi
->buffer_offset
;
468 cs
->FE_VERTEX_STREAM_BASE_ADDR
.flags
= ETNA_RELOC_READ
;
469 cs
->FE_VERTEX_STREAM_CONTROL
=
470 FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi
->stride
);
472 cs
->FE_VERTEX_STREAM_BASE_ADDR
.bo
= NULL
;
473 cs
->FE_VERTEX_STREAM_CONTROL
= 0;
477 ctx
->dirty
|= ETNA_DIRTY_VERTEX_BUFFERS
;
481 etna_blend_state_bind(struct pipe_context
*pctx
, void *bs
)
483 struct etna_context
*ctx
= etna_context(pctx
);
486 ctx
->dirty
|= ETNA_DIRTY_BLEND
;
490 etna_blend_state_delete(struct pipe_context
*pctx
, void *bs
)
496 etna_rasterizer_state_bind(struct pipe_context
*pctx
, void *rs
)
498 struct etna_context
*ctx
= etna_context(pctx
);
500 ctx
->rasterizer
= rs
;
501 ctx
->dirty
|= ETNA_DIRTY_RASTERIZER
;
505 etna_rasterizer_state_delete(struct pipe_context
*pctx
, void *rs
)
511 etna_zsa_state_bind(struct pipe_context
*pctx
, void *zs
)
513 struct etna_context
*ctx
= etna_context(pctx
);
516 ctx
->dirty
|= ETNA_DIRTY_ZSA
;
520 etna_zsa_state_delete(struct pipe_context
*pctx
, void *zs
)
525 /** Create vertex element states, which define a layout for fetching
526 * vertices for rendering.
529 etna_vertex_elements_state_create(struct pipe_context
*pctx
,
530 unsigned num_elements
, const struct pipe_vertex_element
*elements
)
532 struct etna_context
*ctx
= etna_context(pctx
);
533 struct etna_screen
*screen
= ctx
->screen
;
534 struct compiled_vertex_elements_state
*cs
= CALLOC_STRUCT(compiled_vertex_elements_state
);
539 if (num_elements
> screen
->specs
.vertex_max_elements
) {
540 BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements
,
541 screen
->specs
.vertex_max_elements
);
545 /* XXX could minimize number of consecutive stretches here by sorting, and
546 * permuting the inputs in shader or does Mesa do this already? */
548 cs
->num_elements
= num_elements
;
550 unsigned start_offset
= 0; /* start of current consecutive stretch */
551 bool nonconsecutive
= true; /* previous value of nonconsecutive */
552 uint32_t buffer_mask
= 0; /* mask of buffer_idx already seen */
554 for (unsigned idx
= 0; idx
< num_elements
; ++idx
) {
555 unsigned buffer_idx
= elements
[idx
].vertex_buffer_index
;
556 unsigned element_size
= util_format_get_blocksize(elements
[idx
].src_format
);
557 unsigned end_offset
= elements
[idx
].src_offset
+ element_size
;
558 uint32_t format_type
, normalize
;
561 start_offset
= elements
[idx
].src_offset
;
563 /* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
564 assert(buffer_idx
< screen
->specs
.stream_count
);
566 /* maximum vertex size is 256 bytes */
567 assert(element_size
!= 0 && (end_offset
- start_offset
) < 256);
569 /* check whether next element is consecutive to this one */
570 nonconsecutive
= (idx
== (num_elements
- 1)) ||
571 elements
[idx
+ 1].vertex_buffer_index
!= buffer_idx
||
572 end_offset
!= elements
[idx
+ 1].src_offset
;
574 format_type
= translate_vertex_format_type(elements
[idx
].src_format
);
575 normalize
= translate_vertex_format_normalize(elements
[idx
].src_format
);
577 assert(format_type
!= ETNA_NO_MATCH
);
578 assert(normalize
!= ETNA_NO_MATCH
);
580 if (screen
->specs
.halti
< 5) {
581 cs
->FE_VERTEX_ELEMENT_CONFIG
[idx
] =
582 COND(nonconsecutive
, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE
) |
584 VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements
[idx
].src_format
)) |
585 normalize
| VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP
) |
586 VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(buffer_idx
) |
587 VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements
[idx
].src_offset
) |
588 VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset
- start_offset
);
589 } else { /* HALTI5 spread vertex attrib config over two registers */
590 cs
->NFE_GENERIC_ATTRIB_CONFIG0
[idx
] =
592 VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements
[idx
].src_format
)) |
593 normalize
| VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP
) |
594 VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(buffer_idx
) |
595 VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements
[idx
].src_offset
);
596 cs
->NFE_GENERIC_ATTRIB_CONFIG1
[idx
] =
597 COND(nonconsecutive
, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE
) |
598 VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset
- start_offset
);
601 if (util_format_is_pure_integer(elements
[idx
].src_format
))
602 cs
->NFE_GENERIC_ATTRIB_SCALE
[idx
] = 1;
604 cs
->NFE_GENERIC_ATTRIB_SCALE
[idx
] = fui(1.0f
);
606 /* instance_divisor is part of elements state but should be the same for all buffers */
607 if (buffer_mask
& 1 << buffer_idx
)
608 assert(cs
->NFE_VERTEX_STREAMS_VERTEX_DIVISOR
[buffer_idx
] == elements
[idx
].instance_divisor
);
610 cs
->NFE_VERTEX_STREAMS_VERTEX_DIVISOR
[buffer_idx
] = elements
[idx
].instance_divisor
;
612 buffer_mask
|= 1 << buffer_idx
;
613 cs
->num_buffers
= MAX2(cs
->num_buffers
, buffer_idx
+ 1);
620 etna_vertex_elements_state_delete(struct pipe_context
*pctx
, void *ve
)
626 etna_vertex_elements_state_bind(struct pipe_context
*pctx
, void *ve
)
628 struct etna_context
*ctx
= etna_context(pctx
);
630 ctx
->vertex_elements
= ve
;
631 ctx
->dirty
|= ETNA_DIRTY_VERTEX_ELEMENTS
;
635 etna_update_ts_config(struct etna_context
*ctx
)
637 uint32_t new_ts_config
= ctx
->framebuffer
.TS_MEM_CONFIG
;
639 if (ctx
->framebuffer_s
.nr_cbufs
> 0) {
640 struct etna_surface
*c_surf
= etna_surface(ctx
->framebuffer_s
.cbufs
[0]);
642 if(c_surf
->level
->ts_size
&& c_surf
->level
->ts_valid
) {
643 new_ts_config
|= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
;
645 new_ts_config
&= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR
;
649 if (ctx
->framebuffer_s
.zsbuf
) {
650 struct etna_surface
*zs_surf
= etna_surface(ctx
->framebuffer_s
.zsbuf
);
652 if(zs_surf
->level
->ts_size
&& zs_surf
->level
->ts_valid
) {
653 new_ts_config
|= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR
;
655 new_ts_config
&= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR
;
659 if (new_ts_config
!= ctx
->framebuffer
.TS_MEM_CONFIG
||
660 (ctx
->dirty
& ETNA_DIRTY_FRAMEBUFFER
)) {
661 ctx
->framebuffer
.TS_MEM_CONFIG
= new_ts_config
;
662 ctx
->dirty
|= ETNA_DIRTY_TS
;
665 ctx
->dirty
&= ~ETNA_DIRTY_DERIVE_TS
;
670 struct etna_state_updater
{
671 bool (*update
)(struct etna_context
*ctx
);
675 static const struct etna_state_updater etna_state_updates
[] = {
677 etna_shader_update_vertex
, ETNA_DIRTY_SHADER
| ETNA_DIRTY_VERTEX_ELEMENTS
,
680 etna_shader_link
, ETNA_DIRTY_SHADER
,
683 etna_update_blend
, ETNA_DIRTY_BLEND
| ETNA_DIRTY_FRAMEBUFFER
686 etna_update_blend_color
, ETNA_DIRTY_BLEND_COLOR
| ETNA_DIRTY_FRAMEBUFFER
,
689 etna_update_ts_config
, ETNA_DIRTY_DERIVE_TS
,
694 etna_state_update(struct etna_context
*ctx
)
696 for (unsigned int i
= 0; i
< ARRAY_SIZE(etna_state_updates
); i
++)
697 if (ctx
->dirty
& etna_state_updates
[i
].dirty
)
698 if (!etna_state_updates
[i
].update(ctx
))
705 etna_state_init(struct pipe_context
*pctx
)
707 pctx
->set_blend_color
= etna_set_blend_color
;
708 pctx
->set_stencil_ref
= etna_set_stencil_ref
;
709 pctx
->set_clip_state
= etna_set_clip_state
;
710 pctx
->set_sample_mask
= etna_set_sample_mask
;
711 pctx
->set_constant_buffer
= etna_set_constant_buffer
;
712 pctx
->set_framebuffer_state
= etna_set_framebuffer_state
;
713 pctx
->set_polygon_stipple
= etna_set_polygon_stipple
;
714 pctx
->set_scissor_states
= etna_set_scissor_states
;
715 pctx
->set_viewport_states
= etna_set_viewport_states
;
717 pctx
->set_vertex_buffers
= etna_set_vertex_buffers
;
719 pctx
->bind_blend_state
= etna_blend_state_bind
;
720 pctx
->delete_blend_state
= etna_blend_state_delete
;
722 pctx
->bind_rasterizer_state
= etna_rasterizer_state_bind
;
723 pctx
->delete_rasterizer_state
= etna_rasterizer_state_delete
;
725 pctx
->bind_depth_stencil_alpha_state
= etna_zsa_state_bind
;
726 pctx
->delete_depth_stencil_alpha_state
= etna_zsa_state_delete
;
728 pctx
->create_vertex_elements_state
= etna_vertex_elements_state_create
;
729 pctx
->delete_vertex_elements_state
= etna_vertex_elements_state_delete
;
730 pctx
->bind_vertex_elements_state
= etna_vertex_elements_state_bind
;