src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_upload_mgr.h"
  46
  47 static void
  48 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  49 {
  50    struct etna_context *ctx = etna_context(pctx);
  51    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  52
  53    ctx->stencil_ref_s = *sr;
  54
  55    for (unsigned i = 0; i < 2; i++) {
  56       cs->PE_STENCIL_CONFIG[i] =
  57          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  58       cs->PE_STENCIL_CONFIG_EXT[i] =
  59          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  60    }
  61    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  62 }
  63
  64 static void
  65 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  66 {
  67    /* NOOP */
  68 }
  69
  70 static void
  71 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  72 {
  73    struct etna_context *ctx = etna_context(pctx);
  74
  75    ctx->sample_mask = sample_mask;
  76    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  77 }
  78
  79 static void
  80 etna_set_constant_buffer(struct pipe_context *pctx,
  81       enum pipe_shader_type shader, uint index,
  82       const struct pipe_constant_buffer *cb)
  83 {
  84    struct etna_context *ctx = etna_context(pctx);
  85
  86    if (unlikely(index > 0)) {
  87       DBG("Unhandled buffer index %i", index);
  88       return;
  89    }
  90
  91
  92    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
  93
  94    /* Note that the state tracker can unbind constant buffers by
  95     * passing NULL here. */
  96    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  97       return;
  98
  99    /* there is no support for ARB_uniform_buffer_object */
 100    assert(cb->buffer == NULL && cb->user_buffer != NULL);
 101
 102    if (!cb->buffer) {
 103       struct pipe_constant_buffer *cb = &ctx->constant_buffer[shader];
 104       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 105    }
 106
 107    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 108 }
 109
 110 static void
 111 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 112 {
 113    struct etna_resource *res = etna_resource(pres);
 114
 115    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 116       /* The render buffer is older than the texture buffer. Copy it over. */
 117       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 118       res->seqno = etna_resource(res->texture)->seqno;
 119    }
 120 }
 121
 122 static void
 123 etna_set_framebuffer_state(struct pipe_context *pctx,
 124       const struct pipe_framebuffer_state *sv)
 125 {
 126    struct etna_context *ctx = etna_context(pctx);
 127    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 128    int nr_samples_color = -1;
 129    int nr_samples_depth = -1;
 130
 131    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 132    uint32_t ts_mem_config = 0;
 133    uint32_t pe_mem_config = 0;
 134
 135    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 136       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 137       struct etna_resource *res = etna_resource(cbuf->base.texture);
 138       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 139
 140       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 141       etna_update_render_resource(pctx, cbuf->base.texture);
 142
 143       cs->PE_COLOR_FORMAT =
 144          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 145          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 146          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 147          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 148          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 149       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 150        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 151        * but only if we set the bits above. */
 152       /* merged with depth_stencil_alpha */
 153       if ((cbuf->surf.offset & 63) ||
 154           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 155          /* XXX Must make temporary surface here.
 156           * Need the same mechanism on gc2000 when we want to do mipmap
 157           * generation by
 158           * rendering to levels > 1 due to multitiled / tiled conversion. */
 159          BUG("Alignment error, trying to render to offset %08x with tile "
 160              "stride %i",
 161              cbuf->surf.offset, cbuf->surf.stride * 4);
 162       }
 163
 164       if (ctx->specs.pixel_pipes == 1) {
 165          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 166          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 167       } else {
 168          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 169          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 170          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 171             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 172             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 173          }
 174       }
 175       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 176
 177       if (cbuf->surf.ts_size) {
 178          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 179
 180          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 181          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 182
 183          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 184          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 185
 186          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 187
 188          if (cbuf->level->ts_compress_fmt >= 0) {
 189             /* overwrite bit breaks v1/v2 compression */
 190             if (!ctx->specs.v4_compression)
 191                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 192
 193             ts_mem_config |=
 194                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 195                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 196          }
 197       }
 198
 199       nr_samples_color = cbuf->base.texture->nr_samples;
 200    } else {
 201       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 202        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 203        * color target */
 204       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 205       cs->PE_COLOR_STRIDE = 0;
 206       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 207       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 208
 209       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 210       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 211          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 212    }
 213
 214    if (sv->zsbuf != NULL) {
 215       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 216       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 217
 218       etna_update_render_resource(pctx, zsbuf->base.texture);
 219
 220       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 221
 222       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 223       unsigned depth_bits =
 224          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 225       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 226
 227       cs->PE_DEPTH_CONFIG =
 228          depth_format |
 229          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 230          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 231          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 232          ;
 233       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 234       /* merged with depth_stencil_alpha */
 235
 236       if (ctx->specs.pixel_pipes == 1) {
 237          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 238          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 239       } else {
 240          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 241             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 242             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 243          }
 244       }
 245
 246       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 247       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 248       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 249
 250       if (zsbuf->surf.ts_size) {
 251          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 252
 253          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 254          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 255
 256          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 257          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 258
 259          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 260
 261          if (zsbuf->level->ts_compress_fmt >= 0) {
 262             ts_mem_config |=
 263                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 264                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 265                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 266          }
 267       }
 268
 269       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 270
 271       nr_samples_depth = zsbuf->base.texture->nr_samples;
 272    } else {
 273       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 274       cs->PE_DEPTH_ADDR.bo = NULL;
 275       cs->PE_DEPTH_STRIDE = 0;
 276       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 277       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 278
 279       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 280          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 281    }
 282
 283    /* MSAA setup */
 284    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 285        nr_samples_depth != nr_samples_color) {
 286       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 287           nr_samples_color, nr_samples_depth);
 288    }
 289
 290    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 291    case 0:
 292    case 1: /* Are 0 and 1 samples allowed? */
 293       cs->GL_MULTI_SAMPLE_CONFIG =
 294          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 295       cs->msaa_mode = false;
 296       break;
 297    case 2:
 298       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 299       cs->msaa_mode = true; /* Add input to PS */
 300       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 301       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 302       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 303       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 304       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 305       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 306       break;
 307    case 4:
 308       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 309       cs->msaa_mode = true; /* Add input to PS */
 310       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 311       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 312       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 313       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 314       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 315       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 316       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 317       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 318       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 319       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 320       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 321       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 322       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 323       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 324       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 325       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 326       break;
 327    }
 328
 329    /* Scissor setup */
 330    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 331    cs->SE_SCISSOR_TOP = 0;
 332    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 333    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 334    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 335    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 336
 337    cs->TS_MEM_CONFIG = ts_mem_config;
 338    cs->PE_MEM_CONFIG = pe_mem_config;
 339
 340    /* Single buffer setup. There is only one switch for this, not a separate
 341     * one per color buffer / depth buffer. To keep the logic simple always use
 342     * single buffer when this feature is available.
 343     */
 344    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 345
 346    /* keep copy of original structure */
 347    util_copy_framebuffer_state(&ctx->framebuffer_s, sv);
 348    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 349 }
 350
 351 static void
 352 etna_set_polygon_stipple(struct pipe_context *pctx,
 353       const struct pipe_poly_stipple *stipple)
 354 {
 355    /* NOP */
 356 }
 357
 358 static void
 359 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 360       unsigned num_scissors, const struct pipe_scissor_state *ss)
 361 {
 362    struct etna_context *ctx = etna_context(pctx);
 363    struct compiled_scissor_state *cs = &ctx->scissor;
 364    assert(ss->minx <= ss->maxx);
 365    assert(ss->miny <= ss->maxy);
 366
 367    /* note that this state is only used when rasterizer_state->scissor is on */
 368    ctx->scissor_s = *ss;
 369    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 370    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 371    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 372    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 373    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 374    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 375
 376    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 377 }
 378
 379 static void
 380 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 381       unsigned num_scissors, const struct pipe_viewport_state *vs)
 382 {
 383    struct etna_context *ctx = etna_context(pctx);
 384    struct compiled_viewport_state *cs = &ctx->viewport;
 385
 386    ctx->viewport_s = *vs;
 387    /**
 388     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 389     * -1..1 to 0..1.
 390     * scaling and translation to 0..1 already happened, so remove that
 391     *
 392     * z' = (z * 2 - 1) * scale + translate
 393     *    = z * (2 * scale) + (translate - scale)
 394     *
 395     * scale' = 2 * scale
 396     * translate' = translate - scale
 397     */
 398
 399    /* must be fixp as v4 state deltas assume it is */
 400    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 401    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 402    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 403    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 404    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 405    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 406
 407    /* Compute scissor rectangle (fixp) from viewport.
 408     * Make sure left is always < right and top always < bottom.
 409     */
 410    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 411    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 412    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 413    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 414    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 415    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 416    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 417    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 418
 419    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 420    cs->PE_DEPTH_FAR = fui(1.0);
 421    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 422 }
 423
 424 static void
 425 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 426       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 427 {
 428    struct etna_context *ctx = etna_context(pctx);
 429    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 430
 431    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 432    so->count = util_last_bit(so->enabled_mask);
 433
 434    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 435       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 436       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 437
 438       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 439                                        etna_usermem_map */
 440
 441       if (vbi->buffer.resource) { /* GPU buffer */
 442          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 443          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 444          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 445          cs->FE_VERTEX_STREAM_CONTROL =
 446             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 447       } else {
 448          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 449          cs->FE_VERTEX_STREAM_CONTROL = 0;
 450       }
 451    }
 452
 453    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 454 }
 455
 456 static void
 457 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 458 {
 459    struct etna_context *ctx = etna_context(pctx);
 460
 461    ctx->blend = bs;
 462    ctx->dirty |= ETNA_DIRTY_BLEND;
 463 }
 464
 465 static void
 466 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 467 {
 468    FREE(bs);
 469 }
 470
 471 static void
 472 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 473 {
 474    struct etna_context *ctx = etna_context(pctx);
 475
 476    ctx->rasterizer = rs;
 477    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 478 }
 479
 480 static void
 481 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 482 {
 483    FREE(rs);
 484 }
 485
 486 static void
 487 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 488 {
 489    struct etna_context *ctx = etna_context(pctx);
 490
 491    ctx->zsa = zs;
 492    ctx->dirty |= ETNA_DIRTY_ZSA;
 493 }
 494
 495 static void
 496 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 497 {
 498    FREE(zs);
 499 }
 500
 501 /** Create vertex element states, which define a layout for fetching
 502  * vertices for rendering.
 503  */
 504 static void *
 505 etna_vertex_elements_state_create(struct pipe_context *pctx,
 506       unsigned num_elements, const struct pipe_vertex_element *elements)
 507 {
 508    struct etna_context *ctx = etna_context(pctx);
 509    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 510
 511    if (!cs)
 512       return NULL;
 513
 514    if (num_elements > ctx->specs.vertex_max_elements) {
 515       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 516           ctx->specs.vertex_max_elements);
 517       return NULL;
 518    }
 519
 520    /* XXX could minimize number of consecutive stretches here by sorting, and
 521     * permuting the inputs in shader or does Mesa do this already? */
 522
 523    /* Check that vertex element binding is compatible with hardware; thus
 524     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 525     * uses more streams than is supported, and u_vbuf should have done some
 526     * reorganization for compatibility. */
 527
 528    /* TODO: does mesa this for us? */
 529    bool incompatible = false;
 530    for (unsigned idx = 0; idx < num_elements; ++idx) {
 531       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 532          incompatible = true;
 533    }
 534
 535    cs->num_elements = num_elements;
 536    if (incompatible || num_elements == 0) {
 537       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 538       FREE(cs);
 539       return NULL;
 540    }
 541
 542    unsigned start_offset = 0; /* start of current consecutive stretch */
 543    bool nonconsecutive = true; /* previous value of nonconsecutive */
 544
 545    for (unsigned idx = 0; idx < num_elements; ++idx) {
 546       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 547       unsigned end_offset = elements[idx].src_offset + element_size;
 548       uint32_t format_type, normalize;
 549
 550       if (nonconsecutive)
 551          start_offset = elements[idx].src_offset;
 552
 553       /* maximum vertex size is 256 bytes */
 554       assert(element_size != 0 && end_offset <= 256);
 555
 556       /* check whether next element is consecutive to this one */
 557       nonconsecutive = (idx == (num_elements - 1)) ||
 558                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 559                        end_offset != elements[idx + 1].src_offset;
 560
 561       format_type = translate_vertex_format_type(elements[idx].src_format);
 562       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 563
 564       assert(format_type != ETNA_NO_MATCH);
 565       assert(normalize != ETNA_NO_MATCH);
 566
 567       if (ctx->specs.halti < 5) {
 568          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 569             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 570             format_type |
 571             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 572             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 573             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 574             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 575             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 576       } else { /* HALTI5 spread vertex attrib config over two registers */
 577          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 578             format_type |
 579             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 580             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 581             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) |
 582             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 583          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 584             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 585             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 586       }
 587       cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */
 588    }
 589
 590    return cs;
 591 }
 592
 593 static void
 594 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 595 {
 596    FREE(ve);
 597 }
 598
 599 static void
 600 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 601 {
 602    struct etna_context *ctx = etna_context(pctx);
 603
 604    ctx->vertex_elements = ve;
 605    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 606 }
 607
 608 static bool
 609 etna_update_ts_config(struct etna_context *ctx)
 610 {
 611    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 612
 613    if (ctx->framebuffer_s.nr_cbufs > 0) {
 614       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 615
 616       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 617          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 618       } else {
 619          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 620       }
 621    }
 622
 623    if (ctx->framebuffer_s.zsbuf) {
 624       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 625
 626       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 627          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 628       } else {
 629          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 630       }
 631    }
 632
 633    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 634        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 635       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 636       ctx->dirty |= ETNA_DIRTY_TS;
 637    }
 638
 639    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 640
 641    return true;
 642 }
 643
 644 struct etna_state_updater {
 645    bool (*update)(struct etna_context *ctx);
 646    uint32_t dirty;
 647 };
 648
 649 static const struct etna_state_updater etna_state_updates[] = {
 650    {
 651       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 652    },
 653    {
 654       etna_shader_link, ETNA_DIRTY_SHADER,
 655    },
 656    {
 657       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 658    },
 659    {
 660       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 661    },
 662    {
 663       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 664    }
 665 };
 666
 667 bool
 668 etna_state_update(struct etna_context *ctx)
 669 {
 670    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 671       if (ctx->dirty & etna_state_updates[i].dirty)
 672          if (!etna_state_updates[i].update(ctx))
 673             return false;
 674
 675    return true;
 676 }
 677
 678 void
 679 etna_state_init(struct pipe_context *pctx)
 680 {
 681    pctx->set_blend_color = etna_set_blend_color;
 682    pctx->set_stencil_ref = etna_set_stencil_ref;
 683    pctx->set_clip_state = etna_set_clip_state;
 684    pctx->set_sample_mask = etna_set_sample_mask;
 685    pctx->set_constant_buffer = etna_set_constant_buffer;
 686    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 687    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 688    pctx->set_scissor_states = etna_set_scissor_states;
 689    pctx->set_viewport_states = etna_set_viewport_states;
 690
 691    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 692
 693    pctx->bind_blend_state = etna_blend_state_bind;
 694    pctx->delete_blend_state = etna_blend_state_delete;
 695
 696    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 697    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 698
 699    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 700    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 701
 702    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 703    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 704    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 705 }