src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45 #include "util/u_upload_mgr.h"
  46
  47 static void
  48 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  49 {
  50    struct etna_context *ctx = etna_context(pctx);
  51    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  52
  53    ctx->stencil_ref_s = *sr;
  54
  55    for (unsigned i = 0; i < 2; i++) {
  56       cs->PE_STENCIL_CONFIG[i] =
  57          VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
  58       cs->PE_STENCIL_CONFIG_EXT[i] =
  59          VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
  60    }
  61    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  62 }
  63
  64 static void
  65 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  66 {
  67    /* NOOP */
  68 }
  69
  70 static void
  71 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  72 {
  73    struct etna_context *ctx = etna_context(pctx);
  74
  75    ctx->sample_mask = sample_mask;
  76    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  77 }
  78
  79 static void
  80 etna_set_constant_buffer(struct pipe_context *pctx,
  81       enum pipe_shader_type shader, uint index,
  82       const struct pipe_constant_buffer *cb)
  83 {
  84    struct etna_context *ctx = etna_context(pctx);
  85
  86    if (unlikely(index > 0)) {
  87       DBG("Unhandled buffer index %i", index);
  88       return;
  89    }
  90
  91
  92    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
  93
  94    /* Note that the state tracker can unbind constant buffers by
  95     * passing NULL here. */
  96    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  97       return;
  98
  99    /* there is no support for ARB_uniform_buffer_object */
 100    assert(cb->buffer == NULL && cb->user_buffer != NULL);
 101
 102    if (!cb->buffer) {
 103       struct pipe_constant_buffer *cb = &ctx->constant_buffer[shader];
 104       u_upload_data(pctx->const_uploader, 0, cb->buffer_size, 16, cb->user_buffer, &cb->buffer_offset, &cb->buffer);
 105    }
 106
 107    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 108 }
 109
 110 static void
 111 etna_update_render_resource(struct pipe_context *pctx, struct etna_resource *base)
 112 {
 113    struct etna_resource *to = base, *from = base;
 114
 115    if (base->texture && etna_resource_newer(etna_resource(base->texture), base))
 116       from = etna_resource(base->texture);
 117
 118    if (base->render)
 119       to = etna_resource(base->render);
 120
 121    if ((to != from) && etna_resource_older(to, from)) {
 122       etna_copy_resource(pctx, &to->base, &from->base, 0, base->base.last_level);
 123       to->seqno = from->seqno;
 124    }
 125 }
 126
 127 static void
 128 etna_set_framebuffer_state(struct pipe_context *pctx,
 129       const struct pipe_framebuffer_state *fb)
 130 {
 131    struct etna_context *ctx = etna_context(pctx);
 132    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 133    int nr_samples_color = -1;
 134    int nr_samples_depth = -1;
 135
 136    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 137    uint32_t ts_mem_config = 0;
 138    uint32_t pe_mem_config = 0;
 139
 140    if (fb->nr_cbufs > 0) { /* at least one color buffer? */
 141       struct etna_surface *cbuf = etna_surface(fb->cbufs[0]);
 142       struct etna_resource *res = etna_resource(cbuf->base.texture);
 143       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 144       uint32_t fmt = translate_pe_format(cbuf->base.format);
 145
 146       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 147       etna_update_render_resource(pctx, etna_resource(cbuf->prsc));
 148
 149       if (fmt >= PE_FORMAT_R16F)
 150           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT_EXT(fmt) |
 151                                 VIVS_PE_COLOR_FORMAT_FORMAT_MASK;
 152       else
 153           cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_FORMAT(fmt);
 154
 155       cs->PE_COLOR_FORMAT |=
 156          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 157          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 158          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 159          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 160       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 161        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 162        * but only if we set the bits above. */
 163       /* merged with depth_stencil_alpha */
 164       if ((cbuf->surf.offset & 63) ||
 165           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 166          /* XXX Must make temporary surface here.
 167           * Need the same mechanism on gc2000 when we want to do mipmap
 168           * generation by
 169           * rendering to levels > 1 due to multitiled / tiled conversion. */
 170          BUG("Alignment error, trying to render to offset %08x with tile "
 171              "stride %i",
 172              cbuf->surf.offset, cbuf->surf.stride * 4);
 173       }
 174
 175       if (ctx->specs.pixel_pipes == 1) {
 176          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 177          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 178       } else {
 179          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 180          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 181          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 182             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 183             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 184          }
 185       }
 186       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 187
 188       if (cbuf->surf.ts_size) {
 189          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 190          cs->TS_COLOR_CLEAR_VALUE_EXT = cbuf->level->clear_value >> 32;
 191
 192          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 193          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 194
 195          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 196          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 197
 198          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 199
 200          if (cbuf->level->ts_compress_fmt >= 0) {
 201             /* overwrite bit breaks v1/v2 compression */
 202             if (!ctx->specs.v4_compression)
 203                cs->PE_COLOR_FORMAT &= ~VIVS_PE_COLOR_FORMAT_OVERWRITE;
 204
 205             ts_mem_config |=
 206                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 207                VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(cbuf->level->ts_compress_fmt);
 208          }
 209       }
 210
 211       nr_samples_color = cbuf->base.texture->nr_samples;
 212    } else {
 213       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 214        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 215        * color target */
 216       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 217       cs->PE_COLOR_STRIDE = 0;
 218       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 219       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 220
 221       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 222       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 223          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 224    }
 225
 226    if (fb->zsbuf != NULL) {
 227       struct etna_surface *zsbuf = etna_surface(fb->zsbuf);
 228       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 229
 230       etna_update_render_resource(pctx, etna_resource(zsbuf->prsc));
 231
 232       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 233
 234       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 235       unsigned depth_bits =
 236          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 237       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 238
 239       cs->PE_DEPTH_CONFIG =
 240          depth_format |
 241          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 242          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 243          VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
 244          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 245          ;
 246       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 247       /* merged with depth_stencil_alpha */
 248
 249       if (ctx->specs.pixel_pipes == 1) {
 250          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 251          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 252       } else {
 253          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 254             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 255             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 256          }
 257       }
 258
 259       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 260       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 261       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 262
 263       if (zsbuf->surf.ts_size) {
 264          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 265
 266          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 267          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 268
 269          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 270          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 271
 272          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 273
 274          if (zsbuf->level->ts_compress_fmt >= 0) {
 275             ts_mem_config |=
 276                VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION |
 277                COND(zsbuf->level->ts_compress_fmt == COMPRESSION_FORMAT_D24S8,
 278                     VIVS_TS_MEM_CONFIG_STENCIL_ENABLE);
 279          }
 280       }
 281
 282       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 283
 284       nr_samples_depth = zsbuf->base.texture->nr_samples;
 285    } else {
 286       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 287       cs->PE_DEPTH_ADDR.bo = NULL;
 288       cs->PE_DEPTH_STRIDE = 0;
 289       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 290       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 291
 292       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 293          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 294    }
 295
 296    /* MSAA setup */
 297    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 298        nr_samples_depth != nr_samples_color) {
 299       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 300           nr_samples_color, nr_samples_depth);
 301    }
 302
 303    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 304    case 0:
 305    case 1: /* Are 0 and 1 samples allowed? */
 306       cs->GL_MULTI_SAMPLE_CONFIG =
 307          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 308       cs->msaa_mode = false;
 309       break;
 310    case 2:
 311       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 312       cs->msaa_mode = true; /* Add input to PS */
 313       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 314       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 315       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 316       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 317       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 318       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 319       break;
 320    case 4:
 321       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 322       cs->msaa_mode = true; /* Add input to PS */
 323       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 324       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 325       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 326       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 327       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 328       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 329       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 330       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 331       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 332       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 333       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 334       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 335       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 336       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 337       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 338       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 339       break;
 340    }
 341
 342    /* Scissor setup */
 343    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 344    cs->SE_SCISSOR_TOP = 0;
 345    cs->SE_SCISSOR_RIGHT = (fb->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 346    cs->SE_SCISSOR_BOTTOM = (fb->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 347    cs->SE_CLIP_RIGHT = (fb->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 348    cs->SE_CLIP_BOTTOM = (fb->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 349
 350    cs->TS_MEM_CONFIG = ts_mem_config;
 351    cs->PE_MEM_CONFIG = pe_mem_config;
 352
 353    /* Single buffer setup. There is only one switch for this, not a separate
 354     * one per color buffer / depth buffer. To keep the logic simple always use
 355     * single buffer when this feature is available.
 356     */
 357    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 358
 359    /* keep copy of original structure */
 360    util_copy_framebuffer_state(&ctx->framebuffer_s, fb);
 361    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 362 }
 363
 364 static void
 365 etna_set_polygon_stipple(struct pipe_context *pctx,
 366       const struct pipe_poly_stipple *stipple)
 367 {
 368    /* NOP */
 369 }
 370
 371 static void
 372 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 373       unsigned num_scissors, const struct pipe_scissor_state *ss)
 374 {
 375    struct etna_context *ctx = etna_context(pctx);
 376    struct compiled_scissor_state *cs = &ctx->scissor;
 377    assert(ss->minx <= ss->maxx);
 378    assert(ss->miny <= ss->maxy);
 379
 380    /* note that this state is only used when rasterizer_state->scissor is on */
 381    ctx->scissor_s = *ss;
 382    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 383    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 384    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 385    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 386    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 387    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 388
 389    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 390 }
 391
 392 static void
 393 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 394       unsigned num_scissors, const struct pipe_viewport_state *vs)
 395 {
 396    struct etna_context *ctx = etna_context(pctx);
 397    struct compiled_viewport_state *cs = &ctx->viewport;
 398
 399    ctx->viewport_s = *vs;
 400    /**
 401     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 402     * -1..1 to 0..1.
 403     * scaling and translation to 0..1 already happened, so remove that
 404     *
 405     * z' = (z * 2 - 1) * scale + translate
 406     *    = z * (2 * scale) + (translate - scale)
 407     *
 408     * scale' = 2 * scale
 409     * translate' = translate - scale
 410     */
 411
 412    /* must be fixp as v4 state deltas assume it is */
 413    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 414    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 415    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 416    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 417    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 418    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 419
 420    /* Compute scissor rectangle (fixp) from viewport.
 421     * Make sure left is always < right and top always < bottom.
 422     */
 423    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 424    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 425    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 426    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 427    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 428    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 429    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 430    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 431
 432    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 433    cs->PE_DEPTH_FAR = fui(1.0);
 434    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 435 }
 436
 437 static void
 438 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 439       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 440 {
 441    struct etna_context *ctx = etna_context(pctx);
 442    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 443
 444    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 445    so->count = util_last_bit(so->enabled_mask);
 446
 447    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 448       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 449       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 450
 451       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 452                                        etna_usermem_map */
 453
 454       if (vbi->buffer.resource) { /* GPU buffer */
 455          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 456          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 457          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 458          cs->FE_VERTEX_STREAM_CONTROL =
 459             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 460       } else {
 461          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 462          cs->FE_VERTEX_STREAM_CONTROL = 0;
 463       }
 464    }
 465
 466    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 467 }
 468
 469 static void
 470 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 471 {
 472    struct etna_context *ctx = etna_context(pctx);
 473
 474    ctx->blend = bs;
 475    ctx->dirty |= ETNA_DIRTY_BLEND;
 476 }
 477
 478 static void
 479 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 480 {
 481    FREE(bs);
 482 }
 483
 484 static void
 485 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 486 {
 487    struct etna_context *ctx = etna_context(pctx);
 488
 489    ctx->rasterizer = rs;
 490    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 491 }
 492
 493 static void
 494 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 495 {
 496    FREE(rs);
 497 }
 498
 499 static void
 500 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 501 {
 502    struct etna_context *ctx = etna_context(pctx);
 503
 504    ctx->zsa = zs;
 505    ctx->dirty |= ETNA_DIRTY_ZSA;
 506 }
 507
 508 static void
 509 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 510 {
 511    FREE(zs);
 512 }
 513
 514 /** Create vertex element states, which define a layout for fetching
 515  * vertices for rendering.
 516  */
 517 static void *
 518 etna_vertex_elements_state_create(struct pipe_context *pctx,
 519       unsigned num_elements, const struct pipe_vertex_element *elements)
 520 {
 521    struct etna_context *ctx = etna_context(pctx);
 522    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 523
 524    if (!cs)
 525       return NULL;
 526
 527    if (num_elements > ctx->specs.vertex_max_elements) {
 528       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 529           ctx->specs.vertex_max_elements);
 530       return NULL;
 531    }
 532
 533    /* XXX could minimize number of consecutive stretches here by sorting, and
 534     * permuting the inputs in shader or does Mesa do this already? */
 535
 536    /* Check that vertex element binding is compatible with hardware; thus
 537     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 538     * uses more streams than is supported, and u_vbuf should have done some
 539     * reorganization for compatibility. */
 540
 541    /* TODO: does mesa this for us? */
 542    bool incompatible = false;
 543    for (unsigned idx = 0; idx < num_elements; ++idx) {
 544       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 545          incompatible = true;
 546    }
 547
 548    cs->num_elements = num_elements;
 549    if (incompatible || num_elements == 0) {
 550       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 551       FREE(cs);
 552       return NULL;
 553    }
 554
 555    unsigned start_offset = 0; /* start of current consecutive stretch */
 556    bool nonconsecutive = true; /* previous value of nonconsecutive */
 557
 558    for (unsigned idx = 0; idx < num_elements; ++idx) {
 559       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 560       unsigned end_offset = elements[idx].src_offset + element_size;
 561       uint32_t format_type, normalize;
 562
 563       if (nonconsecutive)
 564          start_offset = elements[idx].src_offset;
 565
 566       /* maximum vertex size is 256 bytes */
 567       assert(element_size != 0 && end_offset <= 256);
 568
 569       /* check whether next element is consecutive to this one */
 570       nonconsecutive = (idx == (num_elements - 1)) ||
 571                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 572                        end_offset != elements[idx + 1].src_offset;
 573
 574       format_type = translate_vertex_format_type(elements[idx].src_format);
 575       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 576
 577       assert(format_type != ETNA_NO_MATCH);
 578       assert(normalize != ETNA_NO_MATCH);
 579
 580       if (ctx->specs.halti < 5) {
 581          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 582             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 583             format_type |
 584             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 585             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 586             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 587             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 588             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 589       } else { /* HALTI5 spread vertex attrib config over two registers */
 590          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 591             format_type |
 592             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 593             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 594             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) |
 595             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 596          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 597             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 598             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 599       }
 600
 601       if (util_format_is_pure_integer(elements[idx].src_format))
 602          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 1;
 603       else
 604          cs->NFE_GENERIC_ATTRIB_SCALE[idx] = fui(1.0f);
 605    }
 606
 607    return cs;
 608 }
 609
 610 static void
 611 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 612 {
 613    FREE(ve);
 614 }
 615
 616 static void
 617 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 618 {
 619    struct etna_context *ctx = etna_context(pctx);
 620
 621    ctx->vertex_elements = ve;
 622    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 623 }
 624
 625 static bool
 626 etna_update_ts_config(struct etna_context *ctx)
 627 {
 628    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 629
 630    if (ctx->framebuffer_s.nr_cbufs > 0) {
 631       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 632
 633       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 634          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 635       } else {
 636          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 637       }
 638    }
 639
 640    if (ctx->framebuffer_s.zsbuf) {
 641       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 642
 643       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 644          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 645       } else {
 646          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 647       }
 648    }
 649
 650    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 651        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 652       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 653       ctx->dirty |= ETNA_DIRTY_TS;
 654    }
 655
 656    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 657
 658    return true;
 659 }
 660
 661 struct etna_state_updater {
 662    bool (*update)(struct etna_context *ctx);
 663    uint32_t dirty;
 664 };
 665
 666 static const struct etna_state_updater etna_state_updates[] = {
 667    {
 668       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 669    },
 670    {
 671       etna_shader_link, ETNA_DIRTY_SHADER,
 672    },
 673    {
 674       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 675    },
 676    {
 677       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 678    },
 679    {
 680       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 681    }
 682 };
 683
 684 bool
 685 etna_state_update(struct etna_context *ctx)
 686 {
 687    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 688       if (ctx->dirty & etna_state_updates[i].dirty)
 689          if (!etna_state_updates[i].update(ctx))
 690             return false;
 691
 692    return true;
 693 }
 694
 695 void
 696 etna_state_init(struct pipe_context *pctx)
 697 {
 698    pctx->set_blend_color = etna_set_blend_color;
 699    pctx->set_stencil_ref = etna_set_stencil_ref;
 700    pctx->set_clip_state = etna_set_clip_state;
 701    pctx->set_sample_mask = etna_set_sample_mask;
 702    pctx->set_constant_buffer = etna_set_constant_buffer;
 703    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 704    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 705    pctx->set_scissor_states = etna_set_scissor_states;
 706    pctx->set_viewport_states = etna_set_viewport_states;
 707
 708    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 709
 710    pctx->bind_blend_state = etna_blend_state_bind;
 711    pctx->delete_blend_state = etna_blend_state_delete;
 712
 713    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 714    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 715
 716    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 717    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 718
 719    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 720    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 721    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 722 }