src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_clear_blit.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_format.h"
  35 #include "etnaviv_shader.h"
  36 #include "etnaviv_surface.h"
  37 #include "etnaviv_translate.h"
  38 #include "etnaviv_util.h"
  39 #include "util/u_helpers.h"
  40 #include "util/u_inlines.h"
  41 #include "util/u_math.h"
  42 #include "util/u_memory.h"
  43
  44 static void
  45 etna_set_blend_color(struct pipe_context *pctx, const struct pipe_blend_color *bc)
  46 {
  47    struct etna_context *ctx = etna_context(pctx);
  48    struct compiled_blend_color *cs = &ctx->blend_color;
  49
  50    cs->PE_ALPHA_BLEND_COLOR =
  51       VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(bc->color[0])) |
  52       VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(bc->color[1])) |
  53       VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(bc->color[2])) |
  54       VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(bc->color[3]));
  55    ctx->dirty |= ETNA_DIRTY_BLEND_COLOR;
  56 }
  57
  58 static void
  59 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  60 {
  61    struct etna_context *ctx = etna_context(pctx);
  62    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  63
  64    ctx->stencil_ref_s = *sr;
  65
  66    cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
  67    /* rest of bits weaved in from depth_stencil_alpha */
  68    cs->PE_STENCIL_CONFIG_EXT =
  69       VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
  70    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  71 }
  72
  73 static void
  74 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  75 {
  76    /* NOOP */
  77 }
  78
  79 static void
  80 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  81 {
  82    struct etna_context *ctx = etna_context(pctx);
  83
  84    ctx->sample_mask = sample_mask;
  85    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  86 }
  87
  88 static void
  89 etna_set_constant_buffer(struct pipe_context *pctx,
  90       enum pipe_shader_type shader, uint index,
  91       const struct pipe_constant_buffer *cb)
  92 {
  93    struct etna_context *ctx = etna_context(pctx);
  94
  95    if (unlikely(index > 0)) {
  96       DBG("Unhandled buffer index %i", index);
  97       return;
  98    }
  99
 100
 101    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
 102
 103    /* Note that the state tracker can unbind constant buffers by
 104     * passing NULL here. */
 105    if (unlikely(!cb))
 106       return;
 107
 108    /* there is no support for ARB_uniform_buffer_object */
 109    assert(cb->buffer == NULL && cb->user_buffer != NULL);
 110
 111    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 112 }
 113
 114 static void
 115 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 116 {
 117    struct etna_resource *res = etna_resource(pres);
 118
 119    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 120       /* The render buffer is older than the texture buffer. Copy it over. */
 121       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 122       res->seqno = etna_resource(res->texture)->seqno;
 123    }
 124 }
 125
 126 static void
 127 etna_set_framebuffer_state(struct pipe_context *pctx,
 128       const struct pipe_framebuffer_state *sv)
 129 {
 130    struct etna_context *ctx = etna_context(pctx);
 131    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 132    int nr_samples_color = -1;
 133    int nr_samples_depth = -1;
 134
 135    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 136    uint32_t ts_mem_config = 0;
 137
 138    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 139       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 140       struct etna_resource *res = etna_resource(cbuf->base.texture);
 141       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 142
 143       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 144       etna_update_render_resource(pctx, cbuf->base.texture);
 145
 146       pipe_surface_reference(&cs->cbuf, &cbuf->base);
 147       cs->PE_COLOR_FORMAT =
 148          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 149          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 150          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 151          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED);
 152       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 153        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 154        * but only if we set the bits above. */
 155       /* merged with depth_stencil_alpha */
 156       if ((cbuf->surf.offset & 63) ||
 157           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 158          /* XXX Must make temporary surface here.
 159           * Need the same mechanism on gc2000 when we want to do mipmap
 160           * generation by
 161           * rendering to levels > 1 due to multitiled / tiled conversion. */
 162          BUG("Alignment error, trying to render to offset %08x with tile "
 163              "stride %i",
 164              cbuf->surf.offset, cbuf->surf.stride * 4);
 165       }
 166
 167       if (ctx->specs.pixel_pipes == 1) {
 168          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 169          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 170       } else {
 171          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 172          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 173          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 174             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 175             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 176          }
 177       }
 178       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 179
 180       if (cbuf->surf.ts_size) {
 181          ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 182          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 183
 184          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 185          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 186
 187          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 188          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 189       }
 190
 191       /* MSAA */
 192       if (cbuf->base.texture->nr_samples > 1)
 193          ts_mem_config |=
 194             VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(cbuf->base.format);
 195
 196       nr_samples_color = cbuf->base.texture->nr_samples;
 197    } else {
 198       pipe_surface_reference(&cs->cbuf, NULL);
 199       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 200        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 201        * color target */
 202       cs->PE_COLOR_FORMAT = 0;
 203       cs->PE_COLOR_STRIDE = 0;
 204       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 205       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 206
 207       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 208          cs->PE_PIPE_COLOR_ADDR[i].bo = NULL;
 209    }
 210
 211    if (sv->zsbuf != NULL) {
 212       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 213       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 214
 215       etna_update_render_resource(pctx, zsbuf->base.texture);
 216
 217       pipe_surface_reference(&cs->zsbuf, &zsbuf->base);
 218       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 219
 220       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 221       unsigned depth_bits =
 222          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 223       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 224
 225       cs->PE_DEPTH_CONFIG =
 226          depth_format |
 227          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 228          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z;
 229       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 230       /* merged with depth_stencil_alpha */
 231
 232       if (ctx->specs.pixel_pipes == 1) {
 233          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 234          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 235       } else {
 236          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 237             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 238             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 239          }
 240       }
 241
 242       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 243       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 244       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 245
 246       if (zsbuf->surf.ts_size) {
 247          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 248          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 249
 250          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 251          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 252
 253          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 254          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 255       }
 256
 257       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 258
 259       /* MSAA */
 260       if (zsbuf->base.texture->nr_samples > 1)
 261          /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 262           * Disable without MSAA for now, as it causes corruption in glquake. */
 263          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 264
 265       nr_samples_depth = zsbuf->base.texture->nr_samples;
 266    } else {
 267       pipe_surface_reference(&cs->zsbuf, NULL);
 268       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 269       cs->PE_DEPTH_ADDR.bo = NULL;
 270       cs->PE_DEPTH_STRIDE = 0;
 271       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 272       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 273
 274       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 275          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 276    }
 277
 278    /* MSAA setup */
 279    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 280        nr_samples_depth != nr_samples_color) {
 281       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 282           nr_samples_color, nr_samples_depth);
 283    }
 284
 285    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 286    case 0:
 287    case 1: /* Are 0 and 1 samples allowed? */
 288       cs->GL_MULTI_SAMPLE_CONFIG =
 289          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 290       cs->msaa_mode = false;
 291       break;
 292    case 2:
 293       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 294       cs->msaa_mode = true; /* Add input to PS */
 295       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 296       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 297       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 298       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 299       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 300       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 301       break;
 302    case 4:
 303       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 304       cs->msaa_mode = true; /* Add input to PS */
 305       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 306       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 307       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 308       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 309       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 310       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 311       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 312       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 313       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 314       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 315       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 316       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 317       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 318       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 319       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 320       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 321       break;
 322    }
 323
 324    /* Scissor setup */
 325    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 326    cs->SE_SCISSOR_TOP = 0;
 327    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 328    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 329    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 330    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 331
 332    cs->TS_MEM_CONFIG = ts_mem_config;
 333
 334    /* Single buffer setup. There is only one switch for this, not a separate
 335     * one per color buffer / depth buffer. To keep the logic simple always use
 336     * single buffer when this feature is available.
 337     */
 338    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 2 : 0);
 339
 340    ctx->framebuffer_s = *sv; /* keep copy of original structure */
 341    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
 342 }
 343
 344 static void
 345 etna_set_polygon_stipple(struct pipe_context *pctx,
 346       const struct pipe_poly_stipple *stipple)
 347 {
 348    /* NOP */
 349 }
 350
 351 static void
 352 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 353       unsigned num_scissors, const struct pipe_scissor_state *ss)
 354 {
 355    struct etna_context *ctx = etna_context(pctx);
 356    struct compiled_scissor_state *cs = &ctx->scissor;
 357    assert(ss->minx <= ss->maxx);
 358    assert(ss->miny <= ss->maxy);
 359
 360    /* note that this state is only used when rasterizer_state->scissor is on */
 361    ctx->scissor_s = *ss;
 362    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 363    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 364    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 365    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 366    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 367    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 368
 369    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 370 }
 371
 372 static void
 373 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 374       unsigned num_scissors, const struct pipe_viewport_state *vs)
 375 {
 376    struct etna_context *ctx = etna_context(pctx);
 377    struct compiled_viewport_state *cs = &ctx->viewport;
 378
 379    ctx->viewport_s = *vs;
 380    /**
 381     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 382     * -1..1 to 0..1.
 383     * scaling and translation to 0..1 already happened, so remove that
 384     *
 385     * z' = (z * 2 - 1) * scale + translate
 386     *    = z * (2 * scale) + (translate - scale)
 387     *
 388     * scale' = 2 * scale
 389     * translate' = translate - scale
 390     */
 391
 392    /* must be fixp as v4 state deltas assume it is */
 393    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 394    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 395    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 396    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 397    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 398    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 399
 400    /* Compute scissor rectangle (fixp) from viewport.
 401     * Make sure left is always < right and top always < bottom.
 402     */
 403    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 404    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 405    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 406    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 407    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 408    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 409    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 410    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 411
 412    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 413    cs->PE_DEPTH_FAR = fui(1.0);
 414    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 415 }
 416
 417 static void
 418 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 419       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 420 {
 421    struct etna_context *ctx = etna_context(pctx);
 422    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 423
 424    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 425    so->count = util_last_bit(so->enabled_mask);
 426
 427    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 428       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 429       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 430
 431       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 432                                        etna_usermem_map */
 433
 434       if (vbi->buffer.resource) { /* GPU buffer */
 435          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 436          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 437          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 438          cs->FE_VERTEX_STREAM_CONTROL =
 439             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 440       } else {
 441          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 442          cs->FE_VERTEX_STREAM_CONTROL = 0;
 443       }
 444    }
 445
 446    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 447 }
 448
 449 static void
 450 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 451 {
 452    struct etna_context *ctx = etna_context(pctx);
 453
 454    ctx->blend = bs;
 455    ctx->dirty |= ETNA_DIRTY_BLEND;
 456 }
 457
 458 static void
 459 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 460 {
 461    FREE(bs);
 462 }
 463
 464 static void
 465 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 466 {
 467    struct etna_context *ctx = etna_context(pctx);
 468
 469    ctx->rasterizer = rs;
 470    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 471 }
 472
 473 static void
 474 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 475 {
 476    FREE(rs);
 477 }
 478
 479 static void
 480 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 481 {
 482    struct etna_context *ctx = etna_context(pctx);
 483
 484    ctx->zsa = zs;
 485    ctx->dirty |= ETNA_DIRTY_ZSA;
 486 }
 487
 488 static void
 489 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 490 {
 491    FREE(zs);
 492 }
 493
 494 /** Create vertex element states, which define a layout for fetching
 495  * vertices for rendering.
 496  */
 497 static void *
 498 etna_vertex_elements_state_create(struct pipe_context *pctx,
 499       unsigned num_elements, const struct pipe_vertex_element *elements)
 500 {
 501    struct etna_context *ctx = etna_context(pctx);
 502    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 503
 504    if (!cs)
 505       return NULL;
 506
 507    if (num_elements > ctx->specs.vertex_max_elements) {
 508       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 509           ctx->specs.vertex_max_elements);
 510       return NULL;
 511    }
 512
 513    /* XXX could minimize number of consecutive stretches here by sorting, and
 514     * permuting the inputs in shader or does Mesa do this already? */
 515
 516    /* Check that vertex element binding is compatible with hardware; thus
 517     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 518     * uses more streams than is supported, and u_vbuf should have done some
 519     * reorganization for compatibility. */
 520
 521    /* TODO: does mesa this for us? */
 522    bool incompatible = false;
 523    for (unsigned idx = 0; idx < num_elements; ++idx) {
 524       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 525          incompatible = true;
 526    }
 527
 528    cs->num_elements = num_elements;
 529    if (incompatible || num_elements == 0) {
 530       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 531       FREE(cs);
 532       return NULL;
 533    }
 534
 535    unsigned start_offset = 0; /* start of current consecutive stretch */
 536    bool nonconsecutive = true; /* previous value of nonconsecutive */
 537
 538    for (unsigned idx = 0; idx < num_elements; ++idx) {
 539       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 540       unsigned end_offset = elements[idx].src_offset + element_size;
 541       uint32_t format_type, normalize;
 542
 543       if (nonconsecutive)
 544          start_offset = elements[idx].src_offset;
 545
 546       /* maximum vertex size is 256 bytes */
 547       assert(element_size != 0 && end_offset <= 256);
 548
 549       /* check whether next element is consecutive to this one */
 550       nonconsecutive = (idx == (num_elements - 1)) ||
 551                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 552                        end_offset != elements[idx + 1].src_offset;
 553
 554       format_type = translate_vertex_format_type(elements[idx].src_format);
 555       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 556
 557       assert(format_type != ETNA_NO_MATCH);
 558       assert(normalize != ETNA_NO_MATCH);
 559
 560       cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 561          COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 562          format_type |
 563          VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 564          normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 565          VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 566          VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 567          VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 568    }
 569
 570    return cs;
 571 }
 572
 573 static void
 574 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 575 {
 576    FREE(ve);
 577 }
 578
 579 static void
 580 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 581 {
 582    struct etna_context *ctx = etna_context(pctx);
 583
 584    ctx->vertex_elements = ve;
 585    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 586 }
 587
 588 struct etna_state_updater {
 589    bool (*update)(struct etna_context *ctx);
 590    uint32_t dirty;
 591 };
 592
 593 static const struct etna_state_updater etna_state_updates[] = {
 594    {
 595       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 596    },
 597    {
 598       etna_shader_link, ETNA_DIRTY_SHADER,
 599    }
 600 };
 601
 602 bool
 603 etna_state_update(struct etna_context *ctx)
 604 {
 605    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 606       if (ctx->dirty & etna_state_updates[i].dirty)
 607          if (!etna_state_updates[i].update(ctx))
 608             return false;
 609
 610    return true;
 611 }
 612
 613 void
 614 etna_state_init(struct pipe_context *pctx)
 615 {
 616    pctx->set_blend_color = etna_set_blend_color;
 617    pctx->set_stencil_ref = etna_set_stencil_ref;
 618    pctx->set_clip_state = etna_set_clip_state;
 619    pctx->set_sample_mask = etna_set_sample_mask;
 620    pctx->set_constant_buffer = etna_set_constant_buffer;
 621    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 622    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 623    pctx->set_scissor_states = etna_set_scissor_states;
 624    pctx->set_viewport_states = etna_set_viewport_states;
 625
 626    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 627
 628    pctx->bind_blend_state = etna_blend_state_bind;
 629    pctx->delete_blend_state = etna_blend_state_delete;
 630
 631    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 632    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 633
 634    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 635    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 636
 637    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 638    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 639    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 640 }