src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_clear_blit.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_format.h"
  35 #include "etnaviv_shader.h"
  36 #include "etnaviv_surface.h"
  37 #include "etnaviv_translate.h"
  38 #include "etnaviv_util.h"
  39 #include "util/u_helpers.h"
  40 #include "util/u_inlines.h"
  41 #include "util/u_math.h"
  42 #include "util/u_memory.h"
  43
  44 static void
  45 etna_set_blend_color(struct pipe_context *pctx, const struct pipe_blend_color *bc)
  46 {
  47    struct etna_context *ctx = etna_context(pctx);
  48    struct compiled_blend_color *cs = &ctx->blend_color;
  49
  50    cs->PE_ALPHA_BLEND_COLOR =
  51       VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(bc->color[0])) |
  52       VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(bc->color[1])) |
  53       VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(bc->color[2])) |
  54       VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(bc->color[3]));
  55    ctx->dirty |= ETNA_DIRTY_BLEND_COLOR;
  56 }
  57
  58 static void
  59 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  60 {
  61    struct etna_context *ctx = etna_context(pctx);
  62    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  63
  64    ctx->stencil_ref_s = *sr;
  65
  66    cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
  67    /* rest of bits weaved in from depth_stencil_alpha */
  68    cs->PE_STENCIL_CONFIG_EXT =
  69       VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
  70    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  71 }
  72
  73 static void
  74 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  75 {
  76    /* NOOP */
  77 }
  78
  79 static void
  80 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  81 {
  82    struct etna_context *ctx = etna_context(pctx);
  83
  84    ctx->sample_mask = sample_mask;
  85    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  86 }
  87
  88 static void
  89 etna_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
  90       const struct pipe_constant_buffer *cb)
  91 {
  92    struct etna_context *ctx = etna_context(pctx);
  93
  94    if (unlikely(index > 0)) {
  95       DBG("Unhandled buffer index %i", index);
  96       return;
  97    }
  98
  99
 100    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
 101
 102    /* Note that the state tracker can unbind constant buffers by
 103     * passing NULL here. */
 104    if (unlikely(!cb))
 105       return;
 106
 107    /* there is no support for ARB_uniform_buffer_object */
 108    assert(cb->buffer == NULL && cb->user_buffer != NULL);
 109
 110    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 111 }
 112
 113 static void
 114 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 115 {
 116    struct etna_resource *res = etna_resource(pres);
 117
 118    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 119       /* The render buffer is older than the texture buffer. Copy it over. */
 120       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 121       res->seqno = etna_resource(res->texture)->seqno;
 122    }
 123 }
 124
 125 static void
 126 etna_set_framebuffer_state(struct pipe_context *pctx,
 127       const struct pipe_framebuffer_state *sv)
 128 {
 129    struct etna_context *ctx = etna_context(pctx);
 130    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 131    int nr_samples_color = -1;
 132    int nr_samples_depth = -1;
 133
 134    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 135    uint32_t ts_mem_config = 0;
 136
 137    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 138       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 139       struct etna_resource *res = etna_resource(cbuf->base.texture);
 140       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 141
 142       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 143       etna_update_render_resource(pctx, cbuf->base.texture);
 144
 145       pipe_surface_reference(&cs->cbuf, &cbuf->base);
 146       cs->PE_COLOR_FORMAT =
 147          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 148          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 149          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 150          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED);
 151       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 152        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 153        * but only if we set the bits above. */
 154       /* merged with depth_stencil_alpha */
 155       if ((cbuf->surf.offset & 63) ||
 156           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 157          /* XXX Must make temporary surface here.
 158           * Need the same mechanism on gc2000 when we want to do mipmap
 159           * generation by
 160           * rendering to levels > 1 due to multitiled / tiled conversion. */
 161          BUG("Alignment error, trying to render to offset %08x with tile "
 162              "stride %i",
 163              cbuf->surf.offset, cbuf->surf.stride * 4);
 164       }
 165
 166       if (ctx->specs.pixel_pipes == 1) {
 167          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 168          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 169       } else {
 170          /* Rendered textures must always be multi-tiled */
 171          assert(res->layout & ETNA_LAYOUT_BIT_MULTI);
 172          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 173             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 174             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 175          }
 176       }
 177       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 178
 179       if (cbuf->surf.ts_size) {
 180          ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 181          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 182
 183          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 184          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 185
 186          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 187          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 188       }
 189
 190       /* MSAA */
 191       if (cbuf->base.texture->nr_samples > 1)
 192          ts_mem_config |=
 193             VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(cbuf->base.format);
 194
 195       nr_samples_color = cbuf->base.texture->nr_samples;
 196    } else {
 197       pipe_surface_reference(&cs->cbuf, NULL);
 198       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 199        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 200        * color target */
 201       cs->PE_COLOR_FORMAT = 0;
 202       cs->PE_COLOR_STRIDE = 0;
 203       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 204       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 205
 206       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 207          cs->PE_PIPE_COLOR_ADDR[i].bo = NULL;
 208    }
 209
 210    if (sv->zsbuf != NULL) {
 211       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 212       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 213
 214       etna_update_render_resource(pctx, zsbuf->base.texture);
 215
 216       pipe_surface_reference(&cs->zsbuf, &zsbuf->base);
 217       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 218
 219       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 220       unsigned depth_bits =
 221          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 222       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 223
 224       cs->PE_DEPTH_CONFIG =
 225          depth_format |
 226          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 227          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z;
 228       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 229       /* merged with depth_stencil_alpha */
 230
 231       if (ctx->specs.pixel_pipes == 1) {
 232          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 233          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 234       } else {
 235          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 236             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 237             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 238          }
 239       }
 240
 241       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 242       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 243       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 244
 245       if (zsbuf->surf.ts_size) {
 246          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 247          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 248
 249          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 250          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 251
 252          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 253          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 254       }
 255
 256       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 257
 258       /* MSAA */
 259       if (zsbuf->base.texture->nr_samples > 1)
 260          /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 261           * Disable without MSAA for now, as it causes corruption in glquake. */
 262          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 263
 264       nr_samples_depth = zsbuf->base.texture->nr_samples;
 265    } else {
 266       pipe_surface_reference(&cs->zsbuf, NULL);
 267       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 268       cs->PE_DEPTH_ADDR.bo = NULL;
 269       cs->PE_DEPTH_STRIDE = 0;
 270       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 271       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 272
 273       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 274          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 275    }
 276
 277    /* MSAA setup */
 278    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 279        nr_samples_depth != nr_samples_color) {
 280       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 281           nr_samples_color, nr_samples_depth);
 282    }
 283
 284    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 285    case 0:
 286    case 1: /* Are 0 and 1 samples allowed? */
 287       cs->GL_MULTI_SAMPLE_CONFIG =
 288          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 289       cs->msaa_mode = false;
 290       break;
 291    case 2:
 292       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 293       cs->msaa_mode = true; /* Add input to PS */
 294       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 295       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 296       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 297       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 298       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 299       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 300       break;
 301    case 4:
 302       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 303       cs->msaa_mode = true; /* Add input to PS */
 304       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 305       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 306       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 307       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 308       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 309       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 310       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 311       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 312       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 313       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 314       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 315       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 316       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 317       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 318       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 319       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 320       break;
 321    }
 322
 323    /* Scissor setup */
 324    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 325    cs->SE_SCISSOR_TOP = 0;
 326    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 327    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 328    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 329    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 330
 331    cs->TS_MEM_CONFIG = ts_mem_config;
 332
 333    ctx->framebuffer_s = *sv; /* keep copy of original structure */
 334    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
 335 }
 336
 337 static void
 338 etna_set_polygon_stipple(struct pipe_context *pctx,
 339       const struct pipe_poly_stipple *stipple)
 340 {
 341    /* NOP */
 342 }
 343
 344 static void
 345 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 346       unsigned num_scissors, const struct pipe_scissor_state *ss)
 347 {
 348    struct etna_context *ctx = etna_context(pctx);
 349    struct compiled_scissor_state *cs = &ctx->scissor;
 350    assert(ss->minx <= ss->maxx);
 351    assert(ss->miny <= ss->maxy);
 352
 353    /* note that this state is only used when rasterizer_state->scissor is on */
 354    ctx->scissor_s = *ss;
 355    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 356    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 357    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 358    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 359    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 360    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 361
 362    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 363 }
 364
 365 static void
 366 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 367       unsigned num_scissors, const struct pipe_viewport_state *vs)
 368 {
 369    struct etna_context *ctx = etna_context(pctx);
 370    struct compiled_viewport_state *cs = &ctx->viewport;
 371
 372    ctx->viewport_s = *vs;
 373    /**
 374     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 375     * -1..1 to 0..1.
 376     * scaling and translation to 0..1 already happened, so remove that
 377     *
 378     * z' = (z * 2 - 1) * scale + translate
 379     *    = z * (2 * scale) + (translate - scale)
 380     *
 381     * scale' = 2 * scale
 382     * translate' = translate - scale
 383     */
 384
 385    /* must be fixp as v4 state deltas assume it is */
 386    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 387    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 388    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 389    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 390    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 391    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 392
 393    /* Compute scissor rectangle (fixp) from viewport.
 394     * Make sure left is always < right and top always < bottom.
 395     */
 396    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 397    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 398    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 399    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 400    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 401    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 402    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 403    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 404
 405    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 406    cs->PE_DEPTH_FAR = fui(1.0);
 407    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 408 }
 409
 410 static void
 411 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 412       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 413 {
 414    struct etna_context *ctx = etna_context(pctx);
 415    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 416
 417    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 418    so->count = util_last_bit(so->enabled_mask);
 419
 420    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 421       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 422       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 423
 424       assert(!vbi->user_buffer); /* XXX support user_buffer using
 425                                     etna_usermem_map */
 426
 427       if (vbi->buffer) { /* GPU buffer */
 428          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer)->bo;
 429          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 430          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 431          cs->FE_VERTEX_STREAM_CONTROL =
 432             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 433       } else {
 434          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 435          cs->FE_VERTEX_STREAM_CONTROL = 0;
 436       }
 437    }
 438
 439    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 440 }
 441
 442 static void
 443 etna_set_index_buffer(struct pipe_context *pctx, const struct pipe_index_buffer *ib)
 444 {
 445    struct etna_context *ctx = etna_context(pctx);
 446    uint32_t ctrl;
 447
 448    if (ib) {
 449       pipe_resource_reference(&ctx->index_buffer.ib.buffer, ib->buffer);
 450       memcpy(&ctx->index_buffer.ib, ib, sizeof(ctx->index_buffer.ib));
 451       ctrl = translate_index_size(ctx->index_buffer.ib.index_size);
 452    } else {
 453       pipe_resource_reference(&ctx->index_buffer.ib.buffer, NULL);
 454       ctrl = 0;
 455    }
 456
 457    if (ctx->index_buffer.ib.buffer && ctrl != ETNA_NO_MATCH) {
 458       ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = etna_resource(ctx->index_buffer.ib.buffer)->bo;
 459       ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.offset = ctx->index_buffer.ib.offset;
 460       ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 461       ctx->index_buffer.FE_INDEX_STREAM_CONTROL = ctrl;
 462    } else {
 463       ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = NULL;
 464       ctx->index_buffer.FE_INDEX_STREAM_CONTROL = 0;
 465    }
 466
 467    ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
 468 }
 469
 470 static void
 471 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 472 {
 473    struct etna_context *ctx = etna_context(pctx);
 474
 475    ctx->blend = bs;
 476    ctx->dirty |= ETNA_DIRTY_BLEND;
 477 }
 478
 479 static void
 480 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 481 {
 482    FREE(bs);
 483 }
 484
 485 static void
 486 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 487 {
 488    struct etna_context *ctx = etna_context(pctx);
 489
 490    ctx->rasterizer = rs;
 491    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 492 }
 493
 494 static void
 495 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 496 {
 497    FREE(rs);
 498 }
 499
 500 static void
 501 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 502 {
 503    struct etna_context *ctx = etna_context(pctx);
 504
 505    ctx->zsa = zs;
 506    ctx->dirty |= ETNA_DIRTY_ZSA;
 507 }
 508
 509 static void
 510 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 511 {
 512    FREE(zs);
 513 }
 514
 515 /** Create vertex element states, which define a layout for fetching
 516  * vertices for rendering.
 517  */
 518 static void *
 519 etna_vertex_elements_state_create(struct pipe_context *pctx,
 520       unsigned num_elements, const struct pipe_vertex_element *elements)
 521 {
 522    struct etna_context *ctx = etna_context(pctx);
 523    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 524
 525    if (!cs)
 526       return NULL;
 527
 528    if (num_elements > ctx->specs.vertex_max_elements) {
 529       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 530           ctx->specs.vertex_max_elements);
 531       return NULL;
 532    }
 533
 534    /* XXX could minimize number of consecutive stretches here by sorting, and
 535     * permuting the inputs in shader or does Mesa do this already? */
 536
 537    /* Check that vertex element binding is compatible with hardware; thus
 538     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 539     * uses more streams than is supported, and u_vbuf should have done some
 540     * reorganization for compatibility. */
 541
 542    /* TODO: does mesa this for us? */
 543    bool incompatible = false;
 544    for (unsigned idx = 0; idx < num_elements; ++idx) {
 545       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 546          incompatible = true;
 547    }
 548
 549    cs->num_elements = num_elements;
 550    if (incompatible || num_elements == 0) {
 551       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 552       FREE(cs);
 553       return NULL;
 554    }
 555
 556    unsigned start_offset = 0; /* start of current consecutive stretch */
 557    bool nonconsecutive = true; /* previous value of nonconsecutive */
 558
 559    for (unsigned idx = 0; idx < num_elements; ++idx) {
 560       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 561       unsigned end_offset = elements[idx].src_offset + element_size;
 562       uint32_t format_type, normalize;
 563
 564       if (nonconsecutive)
 565          start_offset = elements[idx].src_offset;
 566
 567       /* maximum vertex size is 256 bytes */
 568       assert(element_size != 0 && end_offset <= 256);
 569
 570       /* check whether next element is consecutive to this one */
 571       nonconsecutive = (idx == (num_elements - 1)) ||
 572                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 573                        end_offset != elements[idx + 1].src_offset;
 574
 575       format_type = translate_vertex_format_type(elements[idx].src_format);
 576       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 577
 578       assert(format_type != ETNA_NO_MATCH);
 579       assert(normalize != ETNA_NO_MATCH);
 580
 581       cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 582          COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 583          format_type |
 584          VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 585          normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 586          VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 587          VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 588          VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 589    }
 590
 591    return cs;
 592 }
 593
 594 static void
 595 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 596 {
 597    FREE(ve);
 598 }
 599
 600 static void
 601 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 602 {
 603    struct etna_context *ctx = etna_context(pctx);
 604
 605    ctx->vertex_elements = ve;
 606    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 607 }
 608
 609 struct etna_state_updater {
 610    bool (*update)(struct etna_context *ctx);
 611    uint32_t dirty;
 612 };
 613
 614 static const struct etna_state_updater etna_state_updates[] = {
 615    {
 616       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 617    },
 618    {
 619       etna_shader_link, ETNA_DIRTY_SHADER,
 620    }
 621 };
 622
 623 bool
 624 etna_state_update(struct etna_context *ctx)
 625 {
 626    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 627       if (ctx->dirty & etna_state_updates[i].dirty)
 628          if (!etna_state_updates[i].update(ctx))
 629             return false;
 630
 631    return true;
 632 }
 633
 634 void
 635 etna_state_init(struct pipe_context *pctx)
 636 {
 637    pctx->set_blend_color = etna_set_blend_color;
 638    pctx->set_stencil_ref = etna_set_stencil_ref;
 639    pctx->set_clip_state = etna_set_clip_state;
 640    pctx->set_sample_mask = etna_set_sample_mask;
 641    pctx->set_constant_buffer = etna_set_constant_buffer;
 642    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 643    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 644    pctx->set_scissor_states = etna_set_scissor_states;
 645    pctx->set_viewport_states = etna_set_viewport_states;
 646
 647    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 648    pctx->set_index_buffer = etna_set_index_buffer;
 649
 650    pctx->bind_blend_state = etna_blend_state_bind;
 651    pctx->delete_blend_state = etna_blend_state_delete;
 652
 653    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 654    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 655
 656    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 657    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 658
 659    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 660    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 661    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 662 }