src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_helpers.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44
  45 static void
  46 etna_set_blend_color(struct pipe_context *pctx, const struct pipe_blend_color *bc)
  47 {
  48    struct etna_context *ctx = etna_context(pctx);
  49    struct compiled_blend_color *cs = &ctx->blend_color;
  50
  51    cs->PE_ALPHA_BLEND_COLOR =
  52       VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(bc->color[0])) |
  53       VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(bc->color[1])) |
  54       VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(bc->color[2])) |
  55       VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(bc->color[3]));
  56    ctx->dirty |= ETNA_DIRTY_BLEND_COLOR;
  57 }
  58
  59 static void
  60 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  61 {
  62    struct etna_context *ctx = etna_context(pctx);
  63    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  64
  65    ctx->stencil_ref_s = *sr;
  66
  67    cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
  68    /* rest of bits weaved in from depth_stencil_alpha */
  69    cs->PE_STENCIL_CONFIG_EXT =
  70       VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
  71    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  72 }
  73
  74 static void
  75 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  76 {
  77    /* NOOP */
  78 }
  79
  80 static void
  81 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  82 {
  83    struct etna_context *ctx = etna_context(pctx);
  84
  85    ctx->sample_mask = sample_mask;
  86    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  87 }
  88
  89 static void
  90 etna_set_constant_buffer(struct pipe_context *pctx,
  91       enum pipe_shader_type shader, uint index,
  92       const struct pipe_constant_buffer *cb)
  93 {
  94    struct etna_context *ctx = etna_context(pctx);
  95
  96    if (unlikely(index > 0)) {
  97       DBG("Unhandled buffer index %i", index);
  98       return;
  99    }
 100
 101
 102    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
 103
 104    /* Note that the state tracker can unbind constant buffers by
 105     * passing NULL here. */
 106    if (unlikely(!cb))
 107       return;
 108
 109    /* there is no support for ARB_uniform_buffer_object */
 110    assert(cb->buffer == NULL && cb->user_buffer != NULL);
 111
 112    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 113 }
 114
 115 static void
 116 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 117 {
 118    struct etna_resource *res = etna_resource(pres);
 119
 120    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 121       /* The render buffer is older than the texture buffer. Copy it over. */
 122       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 123       res->seqno = etna_resource(res->texture)->seqno;
 124    }
 125 }
 126
 127 static void
 128 etna_set_framebuffer_state(struct pipe_context *pctx,
 129       const struct pipe_framebuffer_state *sv)
 130 {
 131    struct etna_context *ctx = etna_context(pctx);
 132    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 133    int nr_samples_color = -1;
 134    int nr_samples_depth = -1;
 135
 136    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 137    uint32_t ts_mem_config = 0;
 138
 139    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 140       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 141       struct etna_resource *res = etna_resource(cbuf->base.texture);
 142       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 143
 144       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 145       etna_update_render_resource(pctx, cbuf->base.texture);
 146
 147       pipe_surface_reference(&cs->cbuf, &cbuf->base);
 148       cs->PE_COLOR_FORMAT =
 149          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 150          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 151          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 152          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED);
 153       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 154        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 155        * but only if we set the bits above. */
 156       /* merged with depth_stencil_alpha */
 157       if ((cbuf->surf.offset & 63) ||
 158           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 159          /* XXX Must make temporary surface here.
 160           * Need the same mechanism on gc2000 when we want to do mipmap
 161           * generation by
 162           * rendering to levels > 1 due to multitiled / tiled conversion. */
 163          BUG("Alignment error, trying to render to offset %08x with tile "
 164              "stride %i",
 165              cbuf->surf.offset, cbuf->surf.stride * 4);
 166       }
 167
 168       if (ctx->specs.pixel_pipes == 1) {
 169          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 170          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 171       } else {
 172          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 173          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 174          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 175             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 176             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 177          }
 178       }
 179       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 180
 181       if (cbuf->surf.ts_size) {
 182          ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 183          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 184
 185          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 186          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 187
 188          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 189          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 190       }
 191
 192       /* MSAA */
 193       if (cbuf->base.texture->nr_samples > 1)
 194          ts_mem_config |=
 195             VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(cbuf->base.format);
 196
 197       nr_samples_color = cbuf->base.texture->nr_samples;
 198    } else {
 199       pipe_surface_reference(&cs->cbuf, NULL);
 200       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 201        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 202        * color target */
 203       cs->PE_COLOR_FORMAT = 0;
 204       cs->PE_COLOR_STRIDE = 0;
 205       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 206       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 207
 208       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 209          cs->PE_PIPE_COLOR_ADDR[i].bo = NULL;
 210    }
 211
 212    if (sv->zsbuf != NULL) {
 213       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 214       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 215
 216       etna_update_render_resource(pctx, zsbuf->base.texture);
 217
 218       pipe_surface_reference(&cs->zsbuf, &zsbuf->base);
 219       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 220
 221       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 222       unsigned depth_bits =
 223          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 224       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 225
 226       cs->PE_DEPTH_CONFIG =
 227          depth_format |
 228          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 229          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z;
 230       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 231       /* merged with depth_stencil_alpha */
 232
 233       if (ctx->specs.pixel_pipes == 1) {
 234          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 235          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 236       } else {
 237          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 238             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 239             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 240          }
 241       }
 242
 243       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 244       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 245       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 246
 247       if (zsbuf->surf.ts_size) {
 248          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 249          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 250
 251          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 252          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 253
 254          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 255          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 256       }
 257
 258       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 259
 260       /* MSAA */
 261       if (zsbuf->base.texture->nr_samples > 1)
 262          /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 263           * Disable without MSAA for now, as it causes corruption in glquake. */
 264          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 265
 266       nr_samples_depth = zsbuf->base.texture->nr_samples;
 267    } else {
 268       pipe_surface_reference(&cs->zsbuf, NULL);
 269       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 270       cs->PE_DEPTH_ADDR.bo = NULL;
 271       cs->PE_DEPTH_STRIDE = 0;
 272       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 273       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 274
 275       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 276          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 277    }
 278
 279    /* MSAA setup */
 280    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 281        nr_samples_depth != nr_samples_color) {
 282       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 283           nr_samples_color, nr_samples_depth);
 284    }
 285
 286    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 287    case 0:
 288    case 1: /* Are 0 and 1 samples allowed? */
 289       cs->GL_MULTI_SAMPLE_CONFIG =
 290          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 291       cs->msaa_mode = false;
 292       break;
 293    case 2:
 294       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 295       cs->msaa_mode = true; /* Add input to PS */
 296       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 297       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 298       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 299       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 300       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 301       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 302       break;
 303    case 4:
 304       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 305       cs->msaa_mode = true; /* Add input to PS */
 306       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 307       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 308       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 309       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 310       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 311       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 312       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 313       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 314       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 315       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 316       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 317       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 318       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 319       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 320       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 321       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 322       break;
 323    }
 324
 325    /* Scissor setup */
 326    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 327    cs->SE_SCISSOR_TOP = 0;
 328    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 329    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 330    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 331    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 332
 333    cs->TS_MEM_CONFIG = ts_mem_config;
 334
 335    /* Single buffer setup. There is only one switch for this, not a separate
 336     * one per color buffer / depth buffer. To keep the logic simple always use
 337     * single buffer when this feature is available.
 338     */
 339    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 2 : 0);
 340
 341    ctx->framebuffer_s = *sv; /* keep copy of original structure */
 342    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
 343 }
 344
 345 static void
 346 etna_set_polygon_stipple(struct pipe_context *pctx,
 347       const struct pipe_poly_stipple *stipple)
 348 {
 349    /* NOP */
 350 }
 351
 352 static void
 353 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 354       unsigned num_scissors, const struct pipe_scissor_state *ss)
 355 {
 356    struct etna_context *ctx = etna_context(pctx);
 357    struct compiled_scissor_state *cs = &ctx->scissor;
 358    assert(ss->minx <= ss->maxx);
 359    assert(ss->miny <= ss->maxy);
 360
 361    /* note that this state is only used when rasterizer_state->scissor is on */
 362    ctx->scissor_s = *ss;
 363    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 364    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 365    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 366    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 367    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 368    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 369
 370    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 371 }
 372
 373 static void
 374 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 375       unsigned num_scissors, const struct pipe_viewport_state *vs)
 376 {
 377    struct etna_context *ctx = etna_context(pctx);
 378    struct compiled_viewport_state *cs = &ctx->viewport;
 379
 380    ctx->viewport_s = *vs;
 381    /**
 382     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 383     * -1..1 to 0..1.
 384     * scaling and translation to 0..1 already happened, so remove that
 385     *
 386     * z' = (z * 2 - 1) * scale + translate
 387     *    = z * (2 * scale) + (translate - scale)
 388     *
 389     * scale' = 2 * scale
 390     * translate' = translate - scale
 391     */
 392
 393    /* must be fixp as v4 state deltas assume it is */
 394    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 395    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 396    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 397    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 398    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 399    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 400
 401    /* Compute scissor rectangle (fixp) from viewport.
 402     * Make sure left is always < right and top always < bottom.
 403     */
 404    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 405    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 406    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 407    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 408    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 409    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 410    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 411    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 412
 413    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 414    cs->PE_DEPTH_FAR = fui(1.0);
 415    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 416 }
 417
 418 static void
 419 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 420       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 421 {
 422    struct etna_context *ctx = etna_context(pctx);
 423    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 424
 425    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 426    so->count = util_last_bit(so->enabled_mask);
 427
 428    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 429       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 430       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 431
 432       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 433                                        etna_usermem_map */
 434
 435       if (vbi->buffer.resource) { /* GPU buffer */
 436          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 437          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 438          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 439          cs->FE_VERTEX_STREAM_CONTROL =
 440             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 441       } else {
 442          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 443          cs->FE_VERTEX_STREAM_CONTROL = 0;
 444       }
 445    }
 446
 447    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 448 }
 449
 450 static void
 451 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 452 {
 453    struct etna_context *ctx = etna_context(pctx);
 454
 455    ctx->blend = bs;
 456    ctx->dirty |= ETNA_DIRTY_BLEND;
 457 }
 458
 459 static void
 460 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 461 {
 462    FREE(bs);
 463 }
 464
 465 static void
 466 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 467 {
 468    struct etna_context *ctx = etna_context(pctx);
 469
 470    ctx->rasterizer = rs;
 471    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 472 }
 473
 474 static void
 475 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 476 {
 477    FREE(rs);
 478 }
 479
 480 static void
 481 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 482 {
 483    struct etna_context *ctx = etna_context(pctx);
 484
 485    ctx->zsa = zs;
 486    ctx->dirty |= ETNA_DIRTY_ZSA;
 487 }
 488
 489 static void
 490 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 491 {
 492    FREE(zs);
 493 }
 494
 495 /** Create vertex element states, which define a layout for fetching
 496  * vertices for rendering.
 497  */
 498 static void *
 499 etna_vertex_elements_state_create(struct pipe_context *pctx,
 500       unsigned num_elements, const struct pipe_vertex_element *elements)
 501 {
 502    struct etna_context *ctx = etna_context(pctx);
 503    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 504
 505    if (!cs)
 506       return NULL;
 507
 508    if (num_elements > ctx->specs.vertex_max_elements) {
 509       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 510           ctx->specs.vertex_max_elements);
 511       return NULL;
 512    }
 513
 514    /* XXX could minimize number of consecutive stretches here by sorting, and
 515     * permuting the inputs in shader or does Mesa do this already? */
 516
 517    /* Check that vertex element binding is compatible with hardware; thus
 518     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 519     * uses more streams than is supported, and u_vbuf should have done some
 520     * reorganization for compatibility. */
 521
 522    /* TODO: does mesa this for us? */
 523    bool incompatible = false;
 524    for (unsigned idx = 0; idx < num_elements; ++idx) {
 525       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 526          incompatible = true;
 527    }
 528
 529    cs->num_elements = num_elements;
 530    if (incompatible || num_elements == 0) {
 531       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 532       FREE(cs);
 533       return NULL;
 534    }
 535
 536    unsigned start_offset = 0; /* start of current consecutive stretch */
 537    bool nonconsecutive = true; /* previous value of nonconsecutive */
 538
 539    for (unsigned idx = 0; idx < num_elements; ++idx) {
 540       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 541       unsigned end_offset = elements[idx].src_offset + element_size;
 542       uint32_t format_type, normalize;
 543
 544       if (nonconsecutive)
 545          start_offset = elements[idx].src_offset;
 546
 547       /* maximum vertex size is 256 bytes */
 548       assert(element_size != 0 && end_offset <= 256);
 549
 550       /* check whether next element is consecutive to this one */
 551       nonconsecutive = (idx == (num_elements - 1)) ||
 552                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 553                        end_offset != elements[idx + 1].src_offset;
 554
 555       format_type = translate_vertex_format_type(elements[idx].src_format);
 556       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 557
 558       assert(format_type != ETNA_NO_MATCH);
 559       assert(normalize != ETNA_NO_MATCH);
 560
 561       cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 562          COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 563          format_type |
 564          VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 565          normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 566          VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 567          VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 568          VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 569    }
 570
 571    return cs;
 572 }
 573
 574 static void
 575 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 576 {
 577    FREE(ve);
 578 }
 579
 580 static void
 581 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 582 {
 583    struct etna_context *ctx = etna_context(pctx);
 584
 585    ctx->vertex_elements = ve;
 586    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 587 }
 588
 589 struct etna_state_updater {
 590    bool (*update)(struct etna_context *ctx);
 591    uint32_t dirty;
 592 };
 593
 594 static const struct etna_state_updater etna_state_updates[] = {
 595    {
 596       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 597    },
 598    {
 599       etna_shader_link, ETNA_DIRTY_SHADER,
 600    },
 601    {
 602       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 603    }
 604 };
 605
 606 bool
 607 etna_state_update(struct etna_context *ctx)
 608 {
 609    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 610       if (ctx->dirty & etna_state_updates[i].dirty)
 611          if (!etna_state_updates[i].update(ctx))
 612             return false;
 613
 614    return true;
 615 }
 616
 617 void
 618 etna_state_init(struct pipe_context *pctx)
 619 {
 620    pctx->set_blend_color = etna_set_blend_color;
 621    pctx->set_stencil_ref = etna_set_stencil_ref;
 622    pctx->set_clip_state = etna_set_clip_state;
 623    pctx->set_sample_mask = etna_set_sample_mask;
 624    pctx->set_constant_buffer = etna_set_constant_buffer;
 625    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 626    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 627    pctx->set_scissor_states = etna_set_scissor_states;
 628    pctx->set_viewport_states = etna_set_viewport_states;
 629
 630    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 631
 632    pctx->bind_blend_state = etna_blend_state_bind;
 633    pctx->delete_blend_state = etna_blend_state_delete;
 634
 635    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 636    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 637
 638    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 639    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 640
 641    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 642    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 643    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 644 }