src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45
  46 static void
  47 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  48 {
  49    struct etna_context *ctx = etna_context(pctx);
  50    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  51
  52    ctx->stencil_ref_s = *sr;
  53
  54    cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
  55    /* rest of bits weaved in from depth_stencil_alpha */
  56    cs->PE_STENCIL_CONFIG_EXT =
  57       VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
  58    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  59 }
  60
  61 static void
  62 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  63 {
  64    /* NOOP */
  65 }
  66
  67 static void
  68 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  69 {
  70    struct etna_context *ctx = etna_context(pctx);
  71
  72    ctx->sample_mask = sample_mask;
  73    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  74 }
  75
  76 static void
  77 etna_set_constant_buffer(struct pipe_context *pctx,
  78       enum pipe_shader_type shader, uint index,
  79       const struct pipe_constant_buffer *cb)
  80 {
  81    struct etna_context *ctx = etna_context(pctx);
  82
  83    if (unlikely(index > 0)) {
  84       DBG("Unhandled buffer index %i", index);
  85       return;
  86    }
  87
  88
  89    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
  90
  91    /* Note that the state tracker can unbind constant buffers by
  92     * passing NULL here. */
  93    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  94       return;
  95
  96    /* there is no support for ARB_uniform_buffer_object */
  97    assert(cb->buffer == NULL && cb->user_buffer != NULL);
  98
  99    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 100 }
 101
 102 static void
 103 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 104 {
 105    struct etna_resource *res = etna_resource(pres);
 106
 107    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 108       /* The render buffer is older than the texture buffer. Copy it over. */
 109       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 110       res->seqno = etna_resource(res->texture)->seqno;
 111    }
 112 }
 113
 114 static void
 115 etna_set_framebuffer_state(struct pipe_context *pctx,
 116       const struct pipe_framebuffer_state *sv)
 117 {
 118    struct etna_context *ctx = etna_context(pctx);
 119    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 120    int nr_samples_color = -1;
 121    int nr_samples_depth = -1;
 122
 123    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 124    uint32_t ts_mem_config = 0;
 125
 126    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 127       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 128       struct etna_resource *res = etna_resource(cbuf->base.texture);
 129       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 130
 131       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 132       etna_update_render_resource(pctx, cbuf->base.texture);
 133
 134       cs->PE_COLOR_FORMAT =
 135          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 136          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 137          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 138          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 139          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 140       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 141        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 142        * but only if we set the bits above. */
 143       /* merged with depth_stencil_alpha */
 144       if ((cbuf->surf.offset & 63) ||
 145           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 146          /* XXX Must make temporary surface here.
 147           * Need the same mechanism on gc2000 when we want to do mipmap
 148           * generation by
 149           * rendering to levels > 1 due to multitiled / tiled conversion. */
 150          BUG("Alignment error, trying to render to offset %08x with tile "
 151              "stride %i",
 152              cbuf->surf.offset, cbuf->surf.stride * 4);
 153       }
 154
 155       if (ctx->specs.pixel_pipes == 1) {
 156          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 157          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 158       } else {
 159          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 160          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 161          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 162             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 163             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 164          }
 165       }
 166       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 167
 168       if (cbuf->surf.ts_size) {
 169          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 170
 171          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 172          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 173
 174          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 175          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 176       }
 177
 178       /* MSAA */
 179       if (cbuf->base.texture->nr_samples > 1)
 180          ts_mem_config |=
 181             VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION | translate_msaa_format(cbuf->base.format);
 182
 183       nr_samples_color = cbuf->base.texture->nr_samples;
 184    } else {
 185       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 186        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 187        * color target */
 188       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 189       cs->PE_COLOR_STRIDE = 0;
 190       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 191       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 192
 193       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 194       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 195          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 196    }
 197
 198    if (sv->zsbuf != NULL) {
 199       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 200       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 201
 202       etna_update_render_resource(pctx, zsbuf->base.texture);
 203
 204       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 205
 206       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 207       unsigned depth_bits =
 208          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 209       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 210
 211       cs->PE_DEPTH_CONFIG =
 212          depth_format |
 213          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 214          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 215          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 216          ;
 217       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 218       /* merged with depth_stencil_alpha */
 219
 220       if (ctx->specs.pixel_pipes == 1) {
 221          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 222          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 223       } else {
 224          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 225             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 226             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 227          }
 228       }
 229
 230       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 231       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 232       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 233
 234       if (zsbuf->surf.ts_size) {
 235          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 236
 237          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 238          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 239
 240          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 241          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 242       }
 243
 244       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 245
 246       /* MSAA */
 247       if (zsbuf->base.texture->nr_samples > 1)
 248          /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 249           * Disable without MSAA for now, as it causes corruption in glquake. */
 250          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 251
 252       nr_samples_depth = zsbuf->base.texture->nr_samples;
 253    } else {
 254       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 255       cs->PE_DEPTH_ADDR.bo = NULL;
 256       cs->PE_DEPTH_STRIDE = 0;
 257       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 258       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 259
 260       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 261          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 262    }
 263
 264    /* MSAA setup */
 265    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 266        nr_samples_depth != nr_samples_color) {
 267       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 268           nr_samples_color, nr_samples_depth);
 269    }
 270
 271    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 272    case 0:
 273    case 1: /* Are 0 and 1 samples allowed? */
 274       cs->GL_MULTI_SAMPLE_CONFIG =
 275          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 276       cs->msaa_mode = false;
 277       break;
 278    case 2:
 279       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 280       cs->msaa_mode = true; /* Add input to PS */
 281       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 282       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 283       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 284       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 285       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 286       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 287       break;
 288    case 4:
 289       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 290       cs->msaa_mode = true; /* Add input to PS */
 291       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 292       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 293       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 294       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 295       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 296       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 297       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 298       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 299       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 300       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 301       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 302       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 303       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 304       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 305       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 306       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 307       break;
 308    }
 309
 310    /* Scissor setup */
 311    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 312    cs->SE_SCISSOR_TOP = 0;
 313    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 314    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 315    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 316    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 317
 318    cs->TS_MEM_CONFIG = ts_mem_config;
 319
 320    /* Single buffer setup. There is only one switch for this, not a separate
 321     * one per color buffer / depth buffer. To keep the logic simple always use
 322     * single buffer when this feature is available.
 323     */
 324    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 325
 326    /* keep copy of original structure */
 327    util_copy_framebuffer_state(&ctx->framebuffer_s, sv);
 328    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 329 }
 330
 331 static void
 332 etna_set_polygon_stipple(struct pipe_context *pctx,
 333       const struct pipe_poly_stipple *stipple)
 334 {
 335    /* NOP */
 336 }
 337
 338 static void
 339 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 340       unsigned num_scissors, const struct pipe_scissor_state *ss)
 341 {
 342    struct etna_context *ctx = etna_context(pctx);
 343    struct compiled_scissor_state *cs = &ctx->scissor;
 344    assert(ss->minx <= ss->maxx);
 345    assert(ss->miny <= ss->maxy);
 346
 347    /* note that this state is only used when rasterizer_state->scissor is on */
 348    ctx->scissor_s = *ss;
 349    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 350    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 351    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 352    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 353    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 354    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 355
 356    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 357 }
 358
 359 static void
 360 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 361       unsigned num_scissors, const struct pipe_viewport_state *vs)
 362 {
 363    struct etna_context *ctx = etna_context(pctx);
 364    struct compiled_viewport_state *cs = &ctx->viewport;
 365
 366    ctx->viewport_s = *vs;
 367    /**
 368     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 369     * -1..1 to 0..1.
 370     * scaling and translation to 0..1 already happened, so remove that
 371     *
 372     * z' = (z * 2 - 1) * scale + translate
 373     *    = z * (2 * scale) + (translate - scale)
 374     *
 375     * scale' = 2 * scale
 376     * translate' = translate - scale
 377     */
 378
 379    /* must be fixp as v4 state deltas assume it is */
 380    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 381    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 382    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 383    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 384    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 385    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 386
 387    /* Compute scissor rectangle (fixp) from viewport.
 388     * Make sure left is always < right and top always < bottom.
 389     */
 390    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 391    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 392    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 393    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 394    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 395    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 396    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 397    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 398
 399    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 400    cs->PE_DEPTH_FAR = fui(1.0);
 401    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 402 }
 403
 404 static void
 405 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 406       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 407 {
 408    struct etna_context *ctx = etna_context(pctx);
 409    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 410
 411    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 412    so->count = util_last_bit(so->enabled_mask);
 413
 414    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 415       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 416       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 417
 418       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 419                                        etna_usermem_map */
 420
 421       if (vbi->buffer.resource) { /* GPU buffer */
 422          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 423          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 424          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 425          cs->FE_VERTEX_STREAM_CONTROL =
 426             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 427       } else {
 428          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 429          cs->FE_VERTEX_STREAM_CONTROL = 0;
 430       }
 431    }
 432
 433    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 434 }
 435
 436 static void
 437 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 438 {
 439    struct etna_context *ctx = etna_context(pctx);
 440
 441    ctx->blend = bs;
 442    ctx->dirty |= ETNA_DIRTY_BLEND;
 443 }
 444
 445 static void
 446 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 447 {
 448    FREE(bs);
 449 }
 450
 451 static void
 452 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 453 {
 454    struct etna_context *ctx = etna_context(pctx);
 455
 456    ctx->rasterizer = rs;
 457    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 458 }
 459
 460 static void
 461 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 462 {
 463    FREE(rs);
 464 }
 465
 466 static void
 467 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 468 {
 469    struct etna_context *ctx = etna_context(pctx);
 470
 471    ctx->zsa = zs;
 472    ctx->dirty |= ETNA_DIRTY_ZSA;
 473 }
 474
 475 static void
 476 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 477 {
 478    FREE(zs);
 479 }
 480
 481 /** Create vertex element states, which define a layout for fetching
 482  * vertices for rendering.
 483  */
 484 static void *
 485 etna_vertex_elements_state_create(struct pipe_context *pctx,
 486       unsigned num_elements, const struct pipe_vertex_element *elements)
 487 {
 488    struct etna_context *ctx = etna_context(pctx);
 489    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 490
 491    if (!cs)
 492       return NULL;
 493
 494    if (num_elements > ctx->specs.vertex_max_elements) {
 495       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 496           ctx->specs.vertex_max_elements);
 497       return NULL;
 498    }
 499
 500    /* XXX could minimize number of consecutive stretches here by sorting, and
 501     * permuting the inputs in shader or does Mesa do this already? */
 502
 503    /* Check that vertex element binding is compatible with hardware; thus
 504     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 505     * uses more streams than is supported, and u_vbuf should have done some
 506     * reorganization for compatibility. */
 507
 508    /* TODO: does mesa this for us? */
 509    bool incompatible = false;
 510    for (unsigned idx = 0; idx < num_elements; ++idx) {
 511       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 512          incompatible = true;
 513    }
 514
 515    cs->num_elements = num_elements;
 516    if (incompatible || num_elements == 0) {
 517       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 518       FREE(cs);
 519       return NULL;
 520    }
 521
 522    unsigned start_offset = 0; /* start of current consecutive stretch */
 523    bool nonconsecutive = true; /* previous value of nonconsecutive */
 524
 525    for (unsigned idx = 0; idx < num_elements; ++idx) {
 526       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 527       unsigned end_offset = elements[idx].src_offset + element_size;
 528       uint32_t format_type, normalize;
 529
 530       if (nonconsecutive)
 531          start_offset = elements[idx].src_offset;
 532
 533       /* maximum vertex size is 256 bytes */
 534       assert(element_size != 0 && end_offset <= 256);
 535
 536       /* check whether next element is consecutive to this one */
 537       nonconsecutive = (idx == (num_elements - 1)) ||
 538                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 539                        end_offset != elements[idx + 1].src_offset;
 540
 541       format_type = translate_vertex_format_type(elements[idx].src_format);
 542       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 543
 544       assert(format_type != ETNA_NO_MATCH);
 545       assert(normalize != ETNA_NO_MATCH);
 546
 547       if (ctx->specs.halti < 5) {
 548          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 549             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 550             format_type |
 551             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 552             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 553             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 554             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 555             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 556       } else { /* HALTI5 spread vertex attrib config over two registers */
 557          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 558             format_type |
 559             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 560             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 561             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) |
 562             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 563          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 564             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 565             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 566       }
 567       cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */
 568    }
 569
 570    return cs;
 571 }
 572
 573 static void
 574 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 575 {
 576    FREE(ve);
 577 }
 578
 579 static void
 580 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 581 {
 582    struct etna_context *ctx = etna_context(pctx);
 583
 584    ctx->vertex_elements = ve;
 585    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 586 }
 587
 588 static bool
 589 etna_update_ts_config(struct etna_context *ctx)
 590 {
 591    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 592
 593    if (ctx->framebuffer_s.nr_cbufs > 0) {
 594       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 595
 596       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 597          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 598       } else {
 599          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 600       }
 601    }
 602
 603    if (ctx->framebuffer_s.zsbuf) {
 604       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 605
 606       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 607          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 608       } else {
 609          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 610       }
 611    }
 612
 613    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 614        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 615       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 616       ctx->dirty |= ETNA_DIRTY_TS;
 617    }
 618
 619    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 620
 621    return true;
 622 }
 623
 624 struct etna_state_updater {
 625    bool (*update)(struct etna_context *ctx);
 626    uint32_t dirty;
 627 };
 628
 629 static const struct etna_state_updater etna_state_updates[] = {
 630    {
 631       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 632    },
 633    {
 634       etna_shader_link, ETNA_DIRTY_SHADER,
 635    },
 636    {
 637       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 638    },
 639    {
 640       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 641    },
 642    {
 643       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 644    }
 645 };
 646
 647 bool
 648 etna_state_update(struct etna_context *ctx)
 649 {
 650    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 651       if (ctx->dirty & etna_state_updates[i].dirty)
 652          if (!etna_state_updates[i].update(ctx))
 653             return false;
 654
 655    return true;
 656 }
 657
 658 void
 659 etna_state_init(struct pipe_context *pctx)
 660 {
 661    pctx->set_blend_color = etna_set_blend_color;
 662    pctx->set_stencil_ref = etna_set_stencil_ref;
 663    pctx->set_clip_state = etna_set_clip_state;
 664    pctx->set_sample_mask = etna_set_sample_mask;
 665    pctx->set_constant_buffer = etna_set_constant_buffer;
 666    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 667    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 668    pctx->set_scissor_states = etna_set_scissor_states;
 669    pctx->set_viewport_states = etna_set_viewport_states;
 670
 671    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 672
 673    pctx->bind_blend_state = etna_blend_state_bind;
 674    pctx->delete_blend_state = etna_blend_state_delete;
 675
 676    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 677    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 678
 679    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 680    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 681
 682    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 683    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 684    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 685 }