88ed970d660517516e4e9a207c44e6f4752e45e5
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_texture.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_texture.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture_state.h"
36 #include "etnaviv_translate.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 static void
43 etna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader,
44 unsigned start_slot, unsigned num_samplers,
45 void **samplers)
46 {
47 /* bind fragment sampler */
48 struct etna_context *ctx = etna_context(pctx);
49 int offset;
50
51 switch (shader) {
52 case PIPE_SHADER_FRAGMENT:
53 offset = 0;
54 ctx->num_fragment_samplers = num_samplers;
55 break;
56 case PIPE_SHADER_VERTEX:
57 offset = ctx->specs.vertex_sampler_offset;
58 break;
59 default:
60 assert(!"Invalid shader");
61 return;
62 }
63
64 uint32_t mask = 1 << offset;
65 for (int idx = 0; idx < num_samplers; ++idx, mask <<= 1) {
66 ctx->sampler[offset + idx] = samplers[idx];
67 if (samplers[idx])
68 ctx->active_samplers |= mask;
69 else
70 ctx->active_samplers &= ~mask;
71 }
72
73 ctx->dirty |= ETNA_DIRTY_SAMPLERS;
74 }
75
76 static bool
77 etna_configure_sampler_ts(struct etna_sampler_ts *sts, struct pipe_sampler_view *pview, bool enable)
78 {
79 bool dirty = (sts->enable != enable);
80
81 assert(sts);
82 sts->enable = enable;
83
84 if (!enable) {
85 sts->TS_SAMPLER_CONFIG = 0;
86 sts->TS_SAMPLER_STATUS_BASE.bo = NULL;
87 return dirty;
88 }
89
90 struct etna_resource *rsc = etna_resource(pview->texture);
91 struct etna_resource_level *lev = &rsc->levels[0];
92
93 if (lev->clear_value != sts->TS_SAMPLER_CLEAR_VALUE)
94 dirty = true;
95
96 assert(rsc->ts_bo && lev->ts_valid);
97
98 sts->mode = lev->ts_mode;
99 sts->TS_SAMPLER_CONFIG =
100 VIVS_TS_SAMPLER_CONFIG_ENABLE |
101 COND(lev->ts_compress_fmt >= 0, VIVS_TS_SAMPLER_CONFIG_COMPRESSION) |
102 VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(lev->ts_compress_fmt);
103 sts->TS_SAMPLER_CLEAR_VALUE = lev->clear_value;
104 sts->TS_SAMPLER_CLEAR_VALUE2 = lev->clear_value; /* To handle 64-bit formats this needs a different value */
105 sts->TS_SAMPLER_STATUS_BASE.bo = rsc->ts_bo;
106 sts->TS_SAMPLER_STATUS_BASE.offset = lev->ts_offset;
107 sts->TS_SAMPLER_STATUS_BASE.flags = ETNA_RELOC_READ;
108
109 return dirty;
110 }
111
112 /* Return true if the GPU can use sampler TS with this sampler view.
113 * Sampler TS is an optimization used when rendering to textures, where
114 * a resolve-in-place can be avoided when rendering has left a (valid) TS.
115 */
116 static bool
117 etna_can_use_sampler_ts(struct pipe_sampler_view *view, int num)
118 {
119 /* Can use sampler TS when:
120 * - the hardware supports sampler TS.
121 * - the sampler view will be bound to sampler <VIVS_TS_SAMPLER__LEN.
122 * HALTI5 adds a mapping from sampler to sampler TS unit, but this is AFAIK
123 * absent on earlier models.
124 * - it is a texture, not a buffer.
125 * - the sampler view has a supported format for sampler TS.
126 * - the sampler will have one LOD, and it happens to be level 0.
127 * (it is not sure if the hw supports it for other levels, but available
128 * state strongly suggests only one at a time).
129 * - the resource TS is valid for level 0.
130 */
131 struct etna_resource *rsc = etna_resource(view->texture);
132 struct etna_screen *screen = etna_screen(rsc->base.screen);
133
134 return VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ) &&
135 num < VIVS_TS_SAMPLER__LEN &&
136 rsc->base.target != PIPE_BUFFER &&
137 (rsc->levels[0].ts_compress_fmt < 0 || screen->specs.v4_compression) &&
138 view->u.tex.first_level == 0 && MIN2(view->u.tex.last_level, rsc->base.last_level) == 0 &&
139 rsc->levels[0].ts_valid;
140 }
141
142 void
143 etna_update_sampler_source(struct pipe_sampler_view *view, int num)
144 {
145 struct etna_resource *base = etna_resource(view->texture);
146 struct etna_resource *to = base, *from = base;
147 struct etna_context *ctx = etna_context(view->context);
148 bool enable_sampler_ts = false;
149
150 if (base->external && etna_resource_newer(etna_resource(base->external), base))
151 from = etna_resource(base->external);
152
153 if (base->texture)
154 to = etna_resource(base->texture);
155
156 if ((to != from) && etna_resource_older(to, from)) {
157 etna_copy_resource(view->context, &to->base, &from->base, 0,
158 view->texture->last_level);
159 to->seqno = from->seqno;
160 ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
161 } else if ((to == from) && etna_resource_needs_flush(to)) {
162 if (ctx->ts_for_sampler_view && etna_can_use_sampler_ts(view, num)) {
163 enable_sampler_ts = true;
164 /* Do not set flush_seqno because the resolve-to-self was bypassed */
165 } else {
166 /* Resolve TS if needed */
167 etna_copy_resource(view->context, &to->base, &from->base, 0,
168 view->texture->last_level);
169 to->flush_seqno = from->seqno;
170 ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
171 }
172 } else if ((to == from) && (to->flush_seqno < from->seqno)) {
173 to->flush_seqno = from->seqno;
174 ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
175 }
176 if (ctx->ts_for_sampler_view &&
177 etna_configure_sampler_ts(ctx->ts_for_sampler_view(view), view, enable_sampler_ts)) {
178 ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES;
179 ctx->dirty_sampler_views |= (1 << num);
180 }
181 }
182
183 static bool
184 etna_resource_sampler_compatible(struct etna_resource *res)
185 {
186 if (util_format_is_compressed(res->base.format))
187 return true;
188
189 struct etna_screen *screen = etna_screen(res->base.screen);
190 /* This GPU supports texturing from supertiled textures? */
191 if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE))
192 return true;
193
194 /* This GPU supports texturing from linear textures? */
195 if (res->layout == ETNA_LAYOUT_LINEAR && VIV_FEATURE(screen, chipMinorFeatures1, LINEAR_TEXTURE_SUPPORT))
196 return true;
197
198 /* Otherwise, only support tiled layouts */
199 if (res->layout != ETNA_LAYOUT_TILED)
200 return false;
201
202 /* If we have HALIGN support, we can allow for the RS padding */
203 if (VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN))
204 return true;
205
206 /* Non-HALIGN GPUs only accept 4x4 tile-aligned textures */
207 if (res->halign != TEXTURE_HALIGN_FOUR)
208 return false;
209
210 return true;
211 }
212
213 struct etna_resource *
214 etna_texture_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc)
215 {
216 struct etna_resource *res = etna_resource(prsc);
217 if (!etna_resource_sampler_compatible(res)) {
218 /* The original resource is not compatible with the sampler.
219 * Allocate an appropriately tiled texture. */
220 if (!res->texture) {
221 struct pipe_resource templat = *prsc;
222
223 templat.bind &= ~(PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET |
224 PIPE_BIND_BLENDABLE);
225 res->texture =
226 etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED,
227 ETNA_ADDRESSING_MODE_TILED,
228 DRM_FORMAT_MOD_LINEAR, &templat);
229 }
230
231 if (!res->texture) {
232 return NULL;
233 }
234 res = etna_resource(res->texture);
235 }
236 return res;
237 }
238
239 static void
240 set_sampler_views(struct etna_context *ctx, unsigned start, unsigned end,
241 unsigned nr, struct pipe_sampler_view **views)
242 {
243 unsigned i, j;
244 uint32_t mask = 1 << start;
245 uint32_t prev_active_sampler_views = ctx->active_sampler_views;
246
247 for (i = start, j = 0; j < nr; i++, j++, mask <<= 1) {
248 pipe_sampler_view_reference(&ctx->sampler_view[i], views[j]);
249 if (views[j]) {
250 ctx->active_sampler_views |= mask;
251 ctx->dirty_sampler_views |= mask;
252 } else
253 ctx->active_sampler_views &= ~mask;
254 }
255
256 for (; i < end; i++, mask <<= 1) {
257 pipe_sampler_view_reference(&ctx->sampler_view[i], NULL);
258 ctx->active_sampler_views &= ~mask;
259 }
260
261 /* sampler views that changed state (even to inactive) are also dirty */
262 ctx->dirty_sampler_views |= ctx->active_sampler_views ^ prev_active_sampler_views;
263 }
264
265 static inline void
266 etna_fragtex_set_sampler_views(struct etna_context *ctx, unsigned nr,
267 struct pipe_sampler_view **views)
268 {
269 unsigned start = 0;
270 unsigned end = start + ctx->specs.fragment_sampler_count;
271
272 set_sampler_views(ctx, start, end, nr, views);
273 ctx->num_fragment_sampler_views = nr;
274 }
275
276
277 static inline void
278 etna_vertex_set_sampler_views(struct etna_context *ctx, unsigned nr,
279 struct pipe_sampler_view **views)
280 {
281 unsigned start = ctx->specs.vertex_sampler_offset;
282 unsigned end = start + ctx->specs.vertex_sampler_count;
283
284 set_sampler_views(ctx, start, end, nr, views);
285 }
286
287 static void
288 etna_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
289 unsigned start_slot, unsigned num_views,
290 struct pipe_sampler_view **views)
291 {
292 struct etna_context *ctx = etna_context(pctx);
293 assert(start_slot == 0);
294
295 ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES;
296
297 switch (shader) {
298 case PIPE_SHADER_FRAGMENT:
299 etna_fragtex_set_sampler_views(ctx, num_views, views);
300 break;
301 case PIPE_SHADER_VERTEX:
302 etna_vertex_set_sampler_views(ctx, num_views, views);
303 break;
304 default:;
305 }
306 }
307
308 static void
309 etna_texture_barrier(struct pipe_context *pctx, unsigned flags)
310 {
311 struct etna_context *ctx = etna_context(pctx);
312 /* clear color and texture cache to make sure that texture unit reads
313 * what has been written */
314 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_TEXTURE);
315 }
316
317 uint32_t
318 active_samplers_bits(struct etna_context *ctx)
319 {
320 return ctx->active_sampler_views & ctx->active_samplers;
321 }
322
323 void
324 etna_texture_init(struct pipe_context *pctx)
325 {
326 pctx->bind_sampler_states = etna_bind_sampler_states;
327 pctx->set_sampler_views = etna_set_sampler_views;
328 pctx->texture_barrier = etna_texture_barrier;
329 etna_texture_state_init(pctx);
330 }