src/gallium/drivers/etnaviv/etnaviv_texture_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_texture_state.h"
  28
  29 #include "hw/common.xml.h"
  30
  31 #include "etnaviv_clear_blit.h"
  32 #include "etnaviv_context.h"
  33 #include "etnaviv_emit.h"
  34 #include "etnaviv_format.h"
  35 #include "etnaviv_texture.h"
  36 #include "etnaviv_translate.h"
  37 #include "util/u_inlines.h"
  38 #include "util/u_memory.h"
  39
  40 #include "drm-uapi/drm_fourcc.h"
  41
  42 static void *
  43 etna_create_sampler_state_state(struct pipe_context *pipe,
  44                           const struct pipe_sampler_state *ss)
  45 {
  46    struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
  47
  48    if (!cs)
  49       return NULL;
  50
  51    cs->TE_SAMPLER_CONFIG0 =
  52       VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
  53       VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
  54       VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
  55       VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
  56       VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter));
  57
  58    /* ROUND_UV improves precision - but not compatible with NEAREST filter */
  59    if (ss->min_img_filter != PIPE_TEX_FILTER_NEAREST &&
  60        ss->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
  61       cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
  62    }
  63
  64    cs->TE_SAMPLER_CONFIG1 =
  65       COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP);
  66
  67    cs->TE_SAMPLER_LOD_CONFIG =
  68       COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
  69       VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
  70
  71    cs->TE_SAMPLER_3D_CONFIG =
  72       VIVS_TE_SAMPLER_3D_CONFIG_WRAP(translate_texture_wrapmode(ss->wrap_r));
  73
  74    if (ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
  75       cs->min_lod = etna_float_to_fixp55(ss->min_lod);
  76       cs->max_lod = etna_float_to_fixp55(ss->max_lod);
  77    } else {
  78       /* when not mipmapping, we need to set max/min lod so that always
  79        * lowest LOD is selected */
  80       cs->min_lod = cs->max_lod = etna_float_to_fixp55(ss->min_lod);
  81    }
  82
  83    /* if max_lod is 0, MIN filter will never be used (GC3000)
  84     * when min filter is different from mag filter, we need HW to compute LOD
  85     * the workaround is to set max_lod to at least 1
  86     */
  87    cs->max_lod_min = (ss->min_img_filter != ss->mag_img_filter) ? 1 : 0;
  88
  89    cs->NTE_SAMPLER_BASELOD =
  90       COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) |
  91       VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss->compare_func));
  92
  93    return cs;
  94 }
  95
  96 static void
  97 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
  98 {
  99    FREE(ss);
 100 }
 101
 102 static struct pipe_sampler_view *
 103 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
 104                          const struct pipe_sampler_view *so)
 105 {
 106    struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
 107    struct etna_context *ctx = etna_context(pctx);
 108    const uint32_t format = translate_texture_format(so->format);
 109    const bool ext = !!(format & EXT_FORMAT);
 110    const bool astc = !!(format & ASTC_FORMAT);
 111    const bool srgb = util_format_is_srgb(so->format);
 112    const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
 113                                           so->swizzle_g, so->swizzle_b,
 114                                           so->swizzle_a);
 115
 116    if (!sv)
 117       return NULL;
 118
 119    struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
 120    if (!res) {
 121       free(sv);
 122       return NULL;
 123    }
 124
 125    sv->base = *so;
 126    pipe_reference_init(&sv->base.reference, 1);
 127    sv->base.texture = NULL;
 128    pipe_resource_reference(&sv->base.texture, prsc);
 129    sv->base.context = pctx;
 130
 131    /* merged with sampler state */
 132    sv->TE_SAMPLER_CONFIG0 =
 133       VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(sv->base.target)) |
 134       COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
 135    sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
 136
 137    uint32_t base_height = res->base.height0;
 138    uint32_t base_depth = res->base.depth0;
 139    bool is_array = false;
 140
 141    switch (sv->base.target) {
 142    case PIPE_TEXTURE_1D:
 143       /* use 2D texture with T wrap to repeat for 1D texture
 144        * TODO: check if old HW supports 1D texture
 145        */
 146       sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
 147       sv->TE_SAMPLER_CONFIG0 &= ~VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK;
 148       sv->TE_SAMPLER_CONFIG0 |=
 149          VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D) |
 150          VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
 151       break;
 152    case PIPE_TEXTURE_1D_ARRAY:
 153       is_array = true;
 154       base_height = res->base.array_size;
 155       break;
 156    case PIPE_TEXTURE_2D_ARRAY:
 157       is_array = true;
 158       base_depth = res->base.array_size;
 159       break;
 160    default:
 161       break;
 162    }
 163
 164    if (res->addressing_mode == ETNA_ADDRESSING_MODE_LINEAR) {
 165       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
 166
 167       for (int lod = 0; lod <= res->base.last_level; ++lod)
 168          sv->TE_SAMPLER_LINEAR_STRIDE[lod] = res->levels[lod].stride;
 169
 170    } else {
 171       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
 172       memset(&sv->TE_SAMPLER_LINEAR_STRIDE, 0, sizeof(sv->TE_SAMPLER_LINEAR_STRIDE));
 173    }
 174
 175    sv->TE_SAMPLER_CONFIG1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
 176                              COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
 177                              COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
 178                              VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
 179    sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
 180                           COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB) |
 181                           VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
 182                           VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
 183                           VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
 184    sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
 185                          VIVS_TE_SAMPLER_SIZE_HEIGHT(base_height);
 186    sv->TE_SAMPLER_LOG_SIZE =
 187       VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
 188       VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(base_height)) |
 189       COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
 190       COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
 191    sv->TE_SAMPLER_3D_CONFIG =
 192       VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(base_depth) |
 193       VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(etna_log2_fixp55(base_depth));
 194
 195    /* Set up levels-of-detail */
 196    for (int lod = 0; lod <= res->base.last_level; ++lod) {
 197       sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
 198       sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
 199       sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
 200    }
 201    sv->min_lod = sv->base.u.tex.first_level << 5;
 202    sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
 203
 204    /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
 205     * supported when the appropriate capability is not set. */
 206    if (!ctx->specs.npot_tex_any_wrap &&
 207        (!util_is_power_of_two_or_zero(res->base.width0) ||
 208         !util_is_power_of_two_or_zero(res->base.height0))) {
 209       sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
 210                                       VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
 211       sv->TE_SAMPLER_CONFIG0 |=
 212          VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
 213          VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
 214    }
 215
 216    return &sv->base;
 217 }
 218
 219 static void
 220 etna_sampler_view_state_destroy(struct pipe_context *pctx,
 221                           struct pipe_sampler_view *view)
 222 {
 223    pipe_resource_reference(&view->texture, NULL);
 224    FREE(view);
 225 }
 226
 227 #define EMIT_STATE(state_name, src_value) \
 228    etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
 229
 230 #define EMIT_STATE_FIXP(state_name, src_value) \
 231    etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
 232
 233 #define EMIT_STATE_RELOC(state_name, src_value) \
 234    etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
 235
 236 /* Emit plain (non-descriptor) texture state */
 237 static void
 238 etna_emit_texture_state(struct etna_context *ctx)
 239 {
 240    struct etna_cmd_stream *stream = ctx->stream;
 241    uint32_t active_samplers = active_samplers_bits(ctx);
 242    uint32_t dirty = ctx->dirty;
 243    struct etna_coalesce coalesce;
 244
 245    etna_coalesce_start(stream, &coalesce);
 246
 247    if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
 248       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 249          if ((1 << x) & active_samplers) {
 250             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 251             /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
 252          }
 253       }
 254       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 255          if ((1 << x) & active_samplers) {
 256             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 257             /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
 258          }
 259       }
 260       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 261          if ((1 << x) & active_samplers) {
 262             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 263             /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
 264          }
 265       }
 266       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 267          if ((1 << x) & active_samplers) {
 268             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 269             /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
 270          }
 271       }
 272    }
 273    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
 274       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 275          uint32_t val = 0; /* 0 == sampler inactive */
 276
 277          /* set active samplers to their configuration value (determined by both
 278           * the sampler state and sampler view) */
 279          if ((1 << x) & active_samplers) {
 280             struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
 281             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 282
 283             val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
 284                   sv->TE_SAMPLER_CONFIG0;
 285          }
 286
 287          /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
 288       }
 289    }
 290    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 291       struct etna_sampler_view *sv;
 292
 293       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 294          if ((1 << x) & active_samplers) {
 295             sv = etna_sampler_view(ctx->sampler_view[x]);
 296             /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
 297          }
 298       }
 299       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 300          if ((1 << x) & active_samplers) {
 301             sv = etna_sampler_view(ctx->sampler_view[x]);
 302             /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), sv->TE_SAMPLER_LOG_SIZE);
 303          }
 304       }
 305    }
 306    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
 307       struct etna_sampler_state *ss;
 308       struct etna_sampler_view *sv;
 309
 310       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 311          if ((1 << x) & active_samplers) {
 312             ss = etna_sampler_state(ctx->sampler[x]);
 313             sv = etna_sampler_view(ctx->sampler_view[x]);
 314
 315             unsigned max_lod = MAX2(MIN2(ss->max_lod, sv->max_lod), ss->max_lod_min);
 316
 317             /* min and max lod is determined both by the sampler and the view */
 318             /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
 319                                  ss->TE_SAMPLER_LOD_CONFIG |
 320                                  VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
 321                                  VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss->min_lod, sv->min_lod)));
 322          }
 323       }
 324       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 325          if ((1 << x) & active_samplers) {
 326             ss = etna_sampler_state(ctx->sampler[x]);
 327             sv = etna_sampler_view(ctx->sampler_view[x]);
 328
 329             /*02180*/ EMIT_STATE(TE_SAMPLER_3D_CONFIG(x), ss->TE_SAMPLER_3D_CONFIG |
 330                                                           sv->TE_SAMPLER_3D_CONFIG);
 331          }
 332       }
 333       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 334          if ((1 << x) & active_samplers) {
 335             ss = etna_sampler_state(ctx->sampler[x]);
 336             sv = etna_sampler_view(ctx->sampler_view[x]);
 337
 338             /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->TE_SAMPLER_CONFIG1 |
 339                                                         sv->TE_SAMPLER_CONFIG1 |
 340                                                         COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
 341          }
 342       }
 343    }
 344    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 345       for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
 346          for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 347             if ((1 << x) & active_samplers) {
 348                struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 349                /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y),&sv->TE_SAMPLER_LOD_ADDR[y]);
 350             }
 351          }
 352       }
 353    }
 354    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 355       for (int y = 0; y < VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN; ++y) {
 356          for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 357             if ((1 << x) & active_samplers) {
 358                struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 359                /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(x, y), sv->TE_SAMPLER_LINEAR_STRIDE[y]);
 360             }
 361          }
 362       }
 363    }
 364    if (unlikely(ctx->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
 365       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 366          if ((1 << x) & active_samplers) {
 367             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 368             /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
 369          }
 370       }
 371    }
 372    if (unlikely(ctx->specs.halti >= 1 && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
 373       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 374          if ((1 << x) & active_samplers) {
 375             struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
 376             /*10700*/ EMIT_STATE(NTE_SAMPLER_BASELOD(x), ss->NTE_SAMPLER_BASELOD);
 377          }
 378       }
 379    }
 380    etna_coalesce_end(stream, &coalesce);
 381 }
 382
 383 #undef EMIT_STATE
 384 #undef EMIT_STATE_FIXP
 385 #undef EMIT_STATE_RELOC
 386
 387 static struct etna_sampler_ts*
 388 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
 389 {
 390    struct etna_sampler_view *sv = etna_sampler_view(pview);
 391    return &sv->ts;
 392 }
 393
 394 void
 395 etna_texture_state_init(struct pipe_context *pctx)
 396 {
 397    struct etna_context *ctx = etna_context(pctx);
 398    DBG("etnaviv: Using state-based texturing");
 399    ctx->base.create_sampler_state = etna_create_sampler_state_state;
 400    ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
 401    ctx->base.create_sampler_view = etna_create_sampler_view_state;
 402    ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
 403    ctx->emit_texture_state = etna_emit_texture_state;
 404    ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
 405 }