2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_texture_state.h"
29 #include "hw/common.xml.h"
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture.h"
36 #include "etnaviv_translate.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
40 #include "drm-uapi/drm_fourcc.h"
43 etna_create_sampler_state_state(struct pipe_context
*pipe
,
44 const struct pipe_sampler_state
*ss
)
46 struct etna_sampler_state
*cs
= CALLOC_STRUCT(etna_sampler_state
);
51 cs
->TE_SAMPLER_CONFIG0
=
52 VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss
->wrap_s
)) |
53 VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss
->wrap_t
)) |
54 VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss
->min_img_filter
)) |
55 VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss
->min_mip_filter
)) |
56 VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss
->mag_img_filter
));
58 /* ROUND_UV improves precision - but not compatible with NEAREST filter */
59 if (ss
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
&&
60 ss
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
) {
61 cs
->TE_SAMPLER_CONFIG0
|= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV
;
64 cs
->TE_SAMPLER_CONFIG1
=
65 COND(ss
->seamless_cube_map
, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP
);
67 cs
->TE_SAMPLER_LOD_CONFIG
=
68 COND(ss
->lod_bias
!= 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE
) |
69 VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss
->lod_bias
));
71 cs
->TE_SAMPLER_3D_CONFIG
=
72 VIVS_TE_SAMPLER_3D_CONFIG_WRAP(translate_texture_wrapmode(ss
->wrap_r
));
74 if (ss
->min_mip_filter
!= PIPE_TEX_MIPFILTER_NONE
) {
75 cs
->min_lod
= etna_float_to_fixp55(ss
->min_lod
);
76 cs
->max_lod
= etna_float_to_fixp55(ss
->max_lod
);
78 /* when not mipmapping, we need to set max/min lod so that always
79 * lowest LOD is selected */
80 cs
->min_lod
= cs
->max_lod
= etna_float_to_fixp55(ss
->min_lod
);
83 /* if max_lod is 0, MIN filter will never be used (GC3000)
84 * when min filter is different from mag filter, we need HW to compute LOD
85 * the workaround is to set max_lod to at least 1
87 cs
->max_lod_min
= (ss
->min_img_filter
!= ss
->mag_img_filter
) ? 1 : 0;
89 cs
->NTE_SAMPLER_BASELOD
=
90 COND(ss
->compare_mode
, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE
) |
91 VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss
->compare_func
));
97 etna_delete_sampler_state_state(struct pipe_context
*pctx
, void *ss
)
102 static struct pipe_sampler_view
*
103 etna_create_sampler_view_state(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
104 const struct pipe_sampler_view
*so
)
106 struct etna_sampler_view
*sv
= CALLOC_STRUCT(etna_sampler_view
);
107 struct etna_context
*ctx
= etna_context(pctx
);
108 const uint32_t format
= translate_texture_format(so
->format
);
109 const bool ext
= !!(format
& EXT_FORMAT
);
110 const bool astc
= !!(format
& ASTC_FORMAT
);
111 const bool srgb
= util_format_is_srgb(so
->format
);
112 const uint32_t swiz
= get_texture_swiz(so
->format
, so
->swizzle_r
,
113 so
->swizzle_g
, so
->swizzle_b
,
119 struct etna_resource
*res
= etna_texture_handle_incompatible(pctx
, prsc
);
126 pipe_reference_init(&sv
->base
.reference
, 1);
127 sv
->base
.texture
= NULL
;
128 pipe_resource_reference(&sv
->base
.texture
, prsc
);
129 sv
->base
.context
= pctx
;
131 /* merged with sampler state */
132 sv
->TE_SAMPLER_CONFIG0
=
133 VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(sv
->base
.target
)) |
134 COND(!ext
&& !astc
, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format
));
135 sv
->TE_SAMPLER_CONFIG0_MASK
= 0xffffffff;
137 uint32_t base_height
= res
->base
.height0
;
138 uint32_t base_depth
= res
->base
.depth0
;
139 bool is_array
= false;
141 switch (sv
->base
.target
) {
142 case PIPE_TEXTURE_1D
:
143 /* use 2D texture with T wrap to repeat for 1D texture
144 * TODO: check if old HW supports 1D texture
146 sv
->TE_SAMPLER_CONFIG0_MASK
= ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK
;
147 sv
->TE_SAMPLER_CONFIG0
&= ~VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK
;
148 sv
->TE_SAMPLER_CONFIG0
|=
149 VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D
) |
150 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT
);
152 case PIPE_TEXTURE_1D_ARRAY
:
154 base_height
= res
->base
.array_size
;
156 case PIPE_TEXTURE_2D_ARRAY
:
158 base_depth
= res
->base
.array_size
;
164 if (res
->layout
== ETNA_LAYOUT_LINEAR
&& !util_format_is_compressed(so
->format
)) {
165 sv
->TE_SAMPLER_CONFIG0
|= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR
);
167 for (int lod
= 0; lod
<= res
->base
.last_level
; ++lod
)
168 sv
->TE_SAMPLER_LINEAR_STRIDE
[lod
] = res
->levels
[lod
].stride
;
171 sv
->TE_SAMPLER_CONFIG0
|= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED
);
172 memset(&sv
->TE_SAMPLER_LINEAR_STRIDE
, 0, sizeof(sv
->TE_SAMPLER_LINEAR_STRIDE
));
175 sv
->TE_SAMPLER_CONFIG1
|= COND(ext
, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format
)) |
176 COND(astc
, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC
)) |
177 COND(is_array
, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY
) |
178 VIVS_TE_SAMPLER_CONFIG1_HALIGN(res
->halign
) | swiz
;
179 sv
->TE_SAMPLER_ASTC0
= COND(astc
, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format
)) |
180 COND(astc
&& srgb
, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB
) |
181 VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
182 VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
183 VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
184 sv
->TE_SAMPLER_SIZE
= VIVS_TE_SAMPLER_SIZE_WIDTH(res
->base
.width0
) |
185 VIVS_TE_SAMPLER_SIZE_HEIGHT(base_height
);
186 sv
->TE_SAMPLER_LOG_SIZE
=
187 VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res
->base
.width0
)) |
188 VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(base_height
)) |
189 COND(util_format_is_srgb(so
->format
) && !astc
, VIVS_TE_SAMPLER_LOG_SIZE_SRGB
) |
190 COND(astc
, VIVS_TE_SAMPLER_LOG_SIZE_ASTC
) |
191 COND(!util_format_is_float(so
->format
) && so
->target
!= PIPE_TEXTURE_3D
, VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER
);
192 sv
->TE_SAMPLER_3D_CONFIG
=
193 VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(base_depth
) |
194 VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(etna_log2_fixp55(base_depth
));
196 /* Set up levels-of-detail */
197 for (int lod
= 0; lod
<= res
->base
.last_level
; ++lod
) {
198 sv
->TE_SAMPLER_LOD_ADDR
[lod
].bo
= res
->bo
;
199 sv
->TE_SAMPLER_LOD_ADDR
[lod
].offset
= res
->levels
[lod
].offset
;
200 sv
->TE_SAMPLER_LOD_ADDR
[lod
].flags
= ETNA_RELOC_READ
;
202 sv
->min_lod
= sv
->base
.u
.tex
.first_level
<< 5;
203 sv
->max_lod
= MIN2(sv
->base
.u
.tex
.last_level
, res
->base
.last_level
) << 5;
205 /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
206 * supported when the appropriate capability is not set. */
207 if (!ctx
->specs
.npot_tex_any_wrap
&&
208 (!util_is_power_of_two_or_zero(res
->base
.width0
) ||
209 !util_is_power_of_two_or_zero(res
->base
.height0
))) {
210 sv
->TE_SAMPLER_CONFIG0_MASK
= ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK
|
211 VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK
);
212 sv
->TE_SAMPLER_CONFIG0
|=
213 VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE
) |
214 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE
);
221 etna_sampler_view_state_destroy(struct pipe_context
*pctx
,
222 struct pipe_sampler_view
*view
)
224 pipe_resource_reference(&view
->texture
, NULL
);
228 #define EMIT_STATE(state_name, src_value) \
229 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
231 #define EMIT_STATE_FIXP(state_name, src_value) \
232 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
234 #define EMIT_STATE_RELOC(state_name, src_value) \
235 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
237 /* Emit plain (non-descriptor) texture state */
239 etna_emit_texture_state(struct etna_context
*ctx
)
241 struct etna_cmd_stream
*stream
= ctx
->stream
;
242 uint32_t active_samplers
= active_samplers_bits(ctx
);
243 uint32_t dirty
= ctx
->dirty
;
244 struct etna_coalesce coalesce
;
246 etna_coalesce_start(stream
, &coalesce
);
248 if (unlikely(dirty
& ETNA_DIRTY_SAMPLER_VIEWS
)) {
249 for (int x
= 0; x
< VIVS_TS_SAMPLER__LEN
; ++x
) {
250 if ((1 << x
) & active_samplers
) {
251 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
252 /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x
), sv
->ts
.TS_SAMPLER_CONFIG
);
255 for (int x
= 0; x
< VIVS_TS_SAMPLER__LEN
; ++x
) {
256 if ((1 << x
) & active_samplers
) {
257 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
258 /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x
), &sv
->ts
.TS_SAMPLER_STATUS_BASE
);
261 for (int x
= 0; x
< VIVS_TS_SAMPLER__LEN
; ++x
) {
262 if ((1 << x
) & active_samplers
) {
263 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
264 /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x
), sv
->ts
.TS_SAMPLER_CLEAR_VALUE
);
267 for (int x
= 0; x
< VIVS_TS_SAMPLER__LEN
; ++x
) {
268 if ((1 << x
) & active_samplers
) {
269 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
270 /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x
), sv
->ts
.TS_SAMPLER_CLEAR_VALUE2
);
274 if (unlikely(dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
| ETNA_DIRTY_SAMPLERS
))) {
275 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
276 uint32_t val
= 0; /* 0 == sampler inactive */
278 /* set active samplers to their configuration value (determined by both
279 * the sampler state and sampler view) */
280 if ((1 << x
) & active_samplers
) {
281 struct etna_sampler_state
*ss
= etna_sampler_state(ctx
->sampler
[x
]);
282 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
284 val
= (ss
->TE_SAMPLER_CONFIG0
& sv
->TE_SAMPLER_CONFIG0_MASK
) |
285 sv
->TE_SAMPLER_CONFIG0
;
288 /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x
), val
);
291 if (unlikely(dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
))) {
292 struct etna_sampler_view
*sv
;
294 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
295 if ((1 << x
) & active_samplers
) {
296 sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
297 /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x
), sv
->TE_SAMPLER_SIZE
);
300 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
301 if ((1 << x
) & active_samplers
) {
302 sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
303 /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x
), sv
->TE_SAMPLER_LOG_SIZE
);
307 if (unlikely(dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
| ETNA_DIRTY_SAMPLERS
))) {
308 struct etna_sampler_state
*ss
;
309 struct etna_sampler_view
*sv
;
311 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
312 if ((1 << x
) & active_samplers
) {
313 ss
= etna_sampler_state(ctx
->sampler
[x
]);
314 sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
316 unsigned max_lod
= MAX2(MIN2(ss
->max_lod
, sv
->max_lod
), ss
->max_lod_min
);
318 /* min and max lod is determined both by the sampler and the view */
319 /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x
),
320 ss
->TE_SAMPLER_LOD_CONFIG
|
321 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod
) |
322 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss
->min_lod
, sv
->min_lod
)));
325 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
326 if ((1 << x
) & active_samplers
) {
327 ss
= etna_sampler_state(ctx
->sampler
[x
]);
328 sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
330 /*02180*/ EMIT_STATE(TE_SAMPLER_3D_CONFIG(x
), ss
->TE_SAMPLER_3D_CONFIG
|
331 sv
->TE_SAMPLER_3D_CONFIG
);
334 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
335 if ((1 << x
) & active_samplers
) {
336 ss
= etna_sampler_state(ctx
->sampler
[x
]);
337 sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
339 /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x
), ss
->TE_SAMPLER_CONFIG1
|
340 sv
->TE_SAMPLER_CONFIG1
|
341 COND(sv
->ts
.enable
, VIVS_TE_SAMPLER_CONFIG1_USE_TS
));
345 if (unlikely(dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
))) {
346 for (int y
= 0; y
< VIVS_TE_SAMPLER_LOD_ADDR__LEN
; ++y
) {
347 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
348 if ((1 << x
) & active_samplers
) {
349 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
350 /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x
, y
),&sv
->TE_SAMPLER_LOD_ADDR
[y
]);
355 if (unlikely(dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
))) {
356 for (int y
= 0; y
< VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN
; ++y
) {
357 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
358 if ((1 << x
) & active_samplers
) {
359 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
360 /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(x
, y
), sv
->TE_SAMPLER_LINEAR_STRIDE
[y
]);
365 if (unlikely(ctx
->specs
.tex_astc
&& (dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
)))) {
366 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
367 if ((1 << x
) & active_samplers
) {
368 struct etna_sampler_view
*sv
= etna_sampler_view(ctx
->sampler_view
[x
]);
369 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x
), sv
->TE_SAMPLER_ASTC0
);
373 if (unlikely(ctx
->specs
.halti
>= 1 && (dirty
& (ETNA_DIRTY_SAMPLER_VIEWS
)))) {
374 for (int x
= 0; x
< VIVS_TE_SAMPLER__LEN
; ++x
) {
375 if ((1 << x
) & active_samplers
) {
376 struct etna_sampler_state
*ss
= etna_sampler_state(ctx
->sampler
[x
]);
377 /*10700*/ EMIT_STATE(NTE_SAMPLER_BASELOD(x
), ss
->NTE_SAMPLER_BASELOD
);
381 etna_coalesce_end(stream
, &coalesce
);
385 #undef EMIT_STATE_FIXP
386 #undef EMIT_STATE_RELOC
388 static struct etna_sampler_ts
*
389 etna_ts_for_sampler_view_state(struct pipe_sampler_view
*pview
)
391 struct etna_sampler_view
*sv
= etna_sampler_view(pview
);
396 etna_texture_state_init(struct pipe_context
*pctx
)
398 struct etna_context
*ctx
= etna_context(pctx
);
399 DBG("etnaviv: Using state-based texturing");
400 ctx
->base
.create_sampler_state
= etna_create_sampler_state_state
;
401 ctx
->base
.delete_sampler_state
= etna_delete_sampler_state_state
;
402 ctx
->base
.create_sampler_view
= etna_create_sampler_view_state
;
403 ctx
->base
.sampler_view_destroy
= etna_sampler_view_state_destroy
;
404 ctx
->emit_texture_state
= etna_emit_texture_state
;
405 ctx
->ts_for_sampler_view
= etna_ts_for_sampler_view_state
;