c3c68740f971629c10ab2fc7fe25fdf3bdd4f8e4
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_texture_state.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_texture_state.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture.h"
36 #include "etnaviv_translate.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 static void *
43 etna_create_sampler_state_state(struct pipe_context *pipe,
44 const struct pipe_sampler_state *ss)
45 {
46 struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
47
48 if (!cs)
49 return NULL;
50
51 cs->TE_SAMPLER_CONFIG0 =
52 VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
53 VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
54 VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
55 VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
56 VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter));
57
58 /* ROUND_UV improves precision - but not compatible with NEAREST filter */
59 if (ss->min_img_filter != PIPE_TEX_FILTER_NEAREST &&
60 ss->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
61 cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
62 }
63
64 cs->TE_SAMPLER_CONFIG1 =
65 COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP);
66
67 cs->TE_SAMPLER_LOD_CONFIG =
68 COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
69 VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
70
71 if (ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
72 cs->min_lod = etna_float_to_fixp55(ss->min_lod);
73 cs->max_lod = etna_float_to_fixp55(ss->max_lod);
74 } else {
75 /* when not mipmapping, we need to set max/min lod so that always
76 * lowest LOD is selected */
77 cs->min_lod = cs->max_lod = etna_float_to_fixp55(ss->min_lod);
78 }
79
80 /* if max_lod is 0, MIN filter will never be used (GC3000)
81 * when min filter is different from mag filter, we need HW to compute LOD
82 * the workaround is to set max_lod to at least 1
83 */
84 cs->max_lod_min = (ss->min_img_filter != ss->mag_img_filter) ? 1 : 0;
85
86 return cs;
87 }
88
89 static void
90 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
91 {
92 FREE(ss);
93 }
94
95 static struct pipe_sampler_view *
96 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
97 const struct pipe_sampler_view *so)
98 {
99 struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
100 struct etna_context *ctx = etna_context(pctx);
101 const uint32_t format = translate_texture_format(so->format);
102 const bool ext = !!(format & EXT_FORMAT);
103 const bool astc = !!(format & ASTC_FORMAT);
104 const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
105 so->swizzle_g, so->swizzle_b,
106 so->swizzle_a);
107
108 if (!sv)
109 return NULL;
110
111 struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
112 if (!res) {
113 free(sv);
114 return NULL;
115 }
116
117 sv->base = *so;
118 pipe_reference_init(&sv->base.reference, 1);
119 sv->base.texture = NULL;
120 pipe_resource_reference(&sv->base.texture, prsc);
121 sv->base.context = pctx;
122
123 /* merged with sampler state */
124 sv->TE_SAMPLER_CONFIG0 = COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
125 sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
126
127 switch (sv->base.target) {
128 case PIPE_TEXTURE_1D:
129 /* For 1D textures, we will have a height of 1, so we can use 2D
130 * but set T wrap to repeat */
131 sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
132 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
133 /* fallthrough */
134 case PIPE_TEXTURE_2D:
135 case PIPE_TEXTURE_RECT:
136 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D);
137 break;
138 case PIPE_TEXTURE_CUBE:
139 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_CUBE_MAP);
140 break;
141 default:
142 BUG("Unhandled texture target");
143 free(sv);
144 return NULL;
145 }
146
147 if (res->addressing_mode == ETNA_ADDRESSING_MODE_LINEAR) {
148 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
149
150 for (int lod = 0; lod <= res->base.last_level; ++lod)
151 sv->TE_SAMPLER_LINEAR_STRIDE[lod] = res->levels[lod].stride;
152
153 } else {
154 sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
155 memset(&sv->TE_SAMPLER_LINEAR_STRIDE, 0, sizeof(sv->TE_SAMPLER_LINEAR_STRIDE));
156 }
157
158 sv->TE_SAMPLER_CONFIG1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
159 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
160 VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
161 sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
162 VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
163 VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
164 VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
165 sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
166 VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
167 sv->TE_SAMPLER_LOG_SIZE =
168 VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
169 VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0)) |
170 COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
171 COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
172
173 /* Set up levels-of-detail */
174 for (int lod = 0; lod <= res->base.last_level; ++lod) {
175 sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
176 sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
177 sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
178 }
179 sv->min_lod = sv->base.u.tex.first_level << 5;
180 sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
181
182 /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
183 * supported when the appropriate capability is not set. */
184 if (!ctx->specs.npot_tex_any_wrap &&
185 (!util_is_power_of_two_or_zero(res->base.width0) ||
186 !util_is_power_of_two_or_zero(res->base.height0))) {
187 sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
188 VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
189 sv->TE_SAMPLER_CONFIG0 |=
190 VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
191 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
192 }
193
194 return &sv->base;
195 }
196
197 static void
198 etna_sampler_view_state_destroy(struct pipe_context *pctx,
199 struct pipe_sampler_view *view)
200 {
201 pipe_resource_reference(&view->texture, NULL);
202 FREE(view);
203 }
204
205 #define EMIT_STATE(state_name, src_value) \
206 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
207
208 #define EMIT_STATE_FIXP(state_name, src_value) \
209 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
210
211 #define EMIT_STATE_RELOC(state_name, src_value) \
212 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
213
214 /* Emit plain (non-descriptor) texture state */
215 static void
216 etna_emit_texture_state(struct etna_context *ctx)
217 {
218 struct etna_cmd_stream *stream = ctx->stream;
219 uint32_t active_samplers = active_samplers_bits(ctx);
220 uint32_t dirty = ctx->dirty;
221 struct etna_coalesce coalesce;
222
223 etna_coalesce_start(stream, &coalesce);
224
225 if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
226 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
227 if ((1 << x) & active_samplers) {
228 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
229 /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
230 }
231 }
232 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
233 if ((1 << x) & active_samplers) {
234 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
235 /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
236 }
237 }
238 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
239 if ((1 << x) & active_samplers) {
240 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
241 /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
242 }
243 }
244 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
245 if ((1 << x) & active_samplers) {
246 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
247 /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
248 }
249 }
250 }
251 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
252 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
253 uint32_t val = 0; /* 0 == sampler inactive */
254
255 /* set active samplers to their configuration value (determined by both
256 * the sampler state and sampler view) */
257 if ((1 << x) & active_samplers) {
258 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
259 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
260
261 val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
262 sv->TE_SAMPLER_CONFIG0;
263 }
264
265 /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
266 }
267 }
268 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
269 struct etna_sampler_view *sv;
270
271 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
272 if ((1 << x) & active_samplers) {
273 sv = etna_sampler_view(ctx->sampler_view[x]);
274 /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
275 }
276 }
277 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
278 if ((1 << x) & active_samplers) {
279 sv = etna_sampler_view(ctx->sampler_view[x]);
280 /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), sv->TE_SAMPLER_LOG_SIZE);
281 }
282 }
283 }
284 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
285 struct etna_sampler_state *ss;
286 struct etna_sampler_view *sv;
287
288 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
289 if ((1 << x) & active_samplers) {
290 ss = etna_sampler_state(ctx->sampler[x]);
291 sv = etna_sampler_view(ctx->sampler_view[x]);
292
293 unsigned max_lod = MAX2(MIN2(ss->max_lod, sv->max_lod), ss->max_lod_min);
294
295 /* min and max lod is determined both by the sampler and the view */
296 /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
297 ss->TE_SAMPLER_LOD_CONFIG |
298 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
299 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss->min_lod, sv->min_lod)));
300 }
301 }
302 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
303 if ((1 << x) & active_samplers) {
304 ss = etna_sampler_state(ctx->sampler[x]);
305 sv = etna_sampler_view(ctx->sampler_view[x]);
306
307 /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->TE_SAMPLER_CONFIG1 |
308 sv->TE_SAMPLER_CONFIG1 |
309 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
310 }
311 }
312 }
313 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
314 for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
315 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
316 if ((1 << x) & active_samplers) {
317 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
318 /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y),&sv->TE_SAMPLER_LOD_ADDR[y]);
319 }
320 }
321 }
322 }
323 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
324 for (int y = 0; y < VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN; ++y) {
325 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
326 if ((1 << x) & active_samplers) {
327 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
328 /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(x, y), sv->TE_SAMPLER_LINEAR_STRIDE[y]);
329 }
330 }
331 }
332 }
333 if (unlikely(ctx->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
334 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
335 if ((1 << x) & active_samplers) {
336 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
337 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
338 }
339 }
340 }
341 etna_coalesce_end(stream, &coalesce);
342 }
343
344 #undef EMIT_STATE
345 #undef EMIT_STATE_FIXP
346 #undef EMIT_STATE_RELOC
347
348 static struct etna_sampler_ts*
349 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
350 {
351 struct etna_sampler_view *sv = etna_sampler_view(pview);
352 return &sv->ts;
353 }
354
355 void
356 etna_texture_state_init(struct pipe_context *pctx)
357 {
358 struct etna_context *ctx = etna_context(pctx);
359 DBG("etnaviv: Using state-based texturing");
360 ctx->base.create_sampler_state = etna_create_sampler_state_state;
361 ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
362 ctx->base.create_sampler_view = etna_create_sampler_view_state;
363 ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
364 ctx->emit_texture_state = etna_emit_texture_state;
365 ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
366 }