src/gallium/drivers/etnaviv/etnaviv_texture_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_texture_state.h"
  28
  29 #include "hw/common.xml.h"
  30
  31 #include "etnaviv_clear_blit.h"
  32 #include "etnaviv_context.h"
  33 #include "etnaviv_emit.h"
  34 #include "etnaviv_format.h"
  35 #include "etnaviv_texture.h"
  36 #include "etnaviv_translate.h"
  37 #include "util/u_inlines.h"
  38 #include "util/u_memory.h"
  39
  40 #include "drm-uapi/drm_fourcc.h"
  41
  42 struct etna_sampler_state {
  43    struct pipe_sampler_state base;
  44
  45    /* sampler offset +4*sampler, interleave when committing state */
  46    uint32_t TE_SAMPLER_CONFIG0;
  47    uint32_t TE_SAMPLER_CONFIG1;
  48    uint32_t TE_SAMPLER_LOD_CONFIG;
  49    uint32_t TE_SAMPLER_3D_CONFIG;
  50    uint32_t NTE_SAMPLER_BASELOD;
  51    unsigned min_lod, max_lod, max_lod_min;
  52 };
  53
  54 static inline struct etna_sampler_state *
  55 etna_sampler_state(struct pipe_sampler_state *samp)
  56 {
  57    return (struct etna_sampler_state *)samp;
  58 }
  59
  60 struct etna_sampler_view {
  61    struct pipe_sampler_view base;
  62
  63    /* sampler offset +4*sampler, interleave when committing state */
  64    uint32_t TE_SAMPLER_CONFIG0;
  65    uint32_t TE_SAMPLER_CONFIG0_MASK;
  66    uint32_t TE_SAMPLER_CONFIG1;
  67    uint32_t TE_SAMPLER_3D_CONFIG;
  68    uint32_t TE_SAMPLER_SIZE;
  69    uint32_t TE_SAMPLER_LOG_SIZE;
  70    uint32_t TE_SAMPLER_ASTC0;
  71    uint32_t TE_SAMPLER_LINEAR_STRIDE[VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN];
  72    struct etna_reloc TE_SAMPLER_LOD_ADDR[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
  73    unsigned min_lod, max_lod; /* 5.5 fixp */
  74
  75    struct etna_sampler_ts ts;
  76 };
  77
  78 static inline struct etna_sampler_view *
  79 etna_sampler_view(struct pipe_sampler_view *view)
  80 {
  81    return (struct etna_sampler_view *)view;
  82 }
  83
  84 static void *
  85 etna_create_sampler_state_state(struct pipe_context *pipe,
  86                           const struct pipe_sampler_state *ss)
  87 {
  88    struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
  89
  90    if (!cs)
  91       return NULL;
  92
  93    cs->TE_SAMPLER_CONFIG0 =
  94       VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
  95       VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
  96       VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
  97       VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
  98       VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter));
  99
 100    /* ROUND_UV improves precision - but not compatible with NEAREST filter */
 101    if (ss->min_img_filter != PIPE_TEX_FILTER_NEAREST &&
 102        ss->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
 103       cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
 104    }
 105
 106    cs->TE_SAMPLER_CONFIG1 =
 107       COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP);
 108
 109    cs->TE_SAMPLER_LOD_CONFIG =
 110       COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
 111       VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
 112
 113    cs->TE_SAMPLER_3D_CONFIG =
 114       VIVS_TE_SAMPLER_3D_CONFIG_WRAP(translate_texture_wrapmode(ss->wrap_r));
 115
 116    if (ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 117       cs->min_lod = etna_float_to_fixp55(ss->min_lod);
 118       cs->max_lod = etna_float_to_fixp55(ss->max_lod);
 119    } else {
 120       /* when not mipmapping, we need to set max/min lod so that always
 121        * lowest LOD is selected */
 122       cs->min_lod = cs->max_lod = etna_float_to_fixp55(ss->min_lod);
 123    }
 124
 125    /* if max_lod is 0, MIN filter will never be used (GC3000)
 126     * when min filter is different from mag filter, we need HW to compute LOD
 127     * the workaround is to set max_lod to at least 1
 128     */
 129    cs->max_lod_min = (ss->min_img_filter != ss->mag_img_filter) ? 1 : 0;
 130
 131    cs->NTE_SAMPLER_BASELOD =
 132       COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) |
 133       VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss->compare_func));
 134
 135    return cs;
 136 }
 137
 138 static void
 139 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
 140 {
 141    FREE(ss);
 142 }
 143
 144 static struct pipe_sampler_view *
 145 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
 146                          const struct pipe_sampler_view *so)
 147 {
 148    struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
 149    struct etna_context *ctx = etna_context(pctx);
 150    struct etna_screen *screen = ctx->screen;
 151    const uint32_t format = translate_texture_format(so->format);
 152    const bool ext = !!(format & EXT_FORMAT);
 153    const bool astc = !!(format & ASTC_FORMAT);
 154    const bool srgb = util_format_is_srgb(so->format);
 155    const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
 156                                           so->swizzle_g, so->swizzle_b,
 157                                           so->swizzle_a);
 158
 159    if (!sv)
 160       return NULL;
 161
 162    struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
 163    if (!res) {
 164       free(sv);
 165       return NULL;
 166    }
 167
 168    sv->base = *so;
 169    pipe_reference_init(&sv->base.reference, 1);
 170    sv->base.texture = NULL;
 171    pipe_resource_reference(&sv->base.texture, prsc);
 172    sv->base.context = pctx;
 173
 174    /* merged with sampler state */
 175    sv->TE_SAMPLER_CONFIG0 =
 176       VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(sv->base.target)) |
 177       COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
 178    sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
 179
 180    uint32_t base_height = res->base.height0;
 181    uint32_t base_depth = res->base.depth0;
 182    bool is_array = false;
 183
 184    switch (sv->base.target) {
 185    case PIPE_TEXTURE_1D:
 186       /* use 2D texture with T wrap to repeat for 1D texture
 187        * TODO: check if old HW supports 1D texture
 188        */
 189       sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
 190       sv->TE_SAMPLER_CONFIG0 &= ~VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK;
 191       sv->TE_SAMPLER_CONFIG0 |=
 192          VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D) |
 193          VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
 194       break;
 195    case PIPE_TEXTURE_1D_ARRAY:
 196       is_array = true;
 197       base_height = res->base.array_size;
 198       break;
 199    case PIPE_TEXTURE_2D_ARRAY:
 200       is_array = true;
 201       base_depth = res->base.array_size;
 202       break;
 203    default:
 204       break;
 205    }
 206
 207    if (res->layout == ETNA_LAYOUT_LINEAR && !util_format_is_compressed(so->format)) {
 208       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
 209
 210       for (int lod = 0; lod <= res->base.last_level; ++lod)
 211          sv->TE_SAMPLER_LINEAR_STRIDE[lod] = res->levels[lod].stride;
 212
 213    } else {
 214       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
 215       memset(&sv->TE_SAMPLER_LINEAR_STRIDE, 0, sizeof(sv->TE_SAMPLER_LINEAR_STRIDE));
 216    }
 217
 218    sv->TE_SAMPLER_CONFIG1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
 219                              COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
 220                              COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
 221                              VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
 222    sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
 223                           COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB) |
 224                           VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
 225                           VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
 226                           VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
 227    sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
 228                          VIVS_TE_SAMPLER_SIZE_HEIGHT(base_height);
 229    sv->TE_SAMPLER_LOG_SIZE =
 230       VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
 231       VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(base_height)) |
 232       COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
 233       COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC) |
 234       COND(texture_use_int_filter(so, false), VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER);
 235    sv->TE_SAMPLER_3D_CONFIG =
 236       VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(base_depth) |
 237       VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(etna_log2_fixp55(base_depth));
 238
 239    /* Set up levels-of-detail */
 240    for (int lod = 0; lod <= res->base.last_level; ++lod) {
 241       sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
 242       sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
 243       sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
 244    }
 245    sv->min_lod = sv->base.u.tex.first_level << 5;
 246    sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
 247
 248    /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
 249     * supported when the appropriate capability is not set. */
 250    if (!screen->specs.npot_tex_any_wrap &&
 251        (!util_is_power_of_two_or_zero(res->base.width0) ||
 252         !util_is_power_of_two_or_zero(res->base.height0))) {
 253       sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
 254                                       VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
 255       sv->TE_SAMPLER_CONFIG0 |=
 256          VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
 257          VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
 258    }
 259
 260    return &sv->base;
 261 }
 262
 263 static void
 264 etna_sampler_view_state_destroy(struct pipe_context *pctx,
 265                           struct pipe_sampler_view *view)
 266 {
 267    pipe_resource_reference(&view->texture, NULL);
 268    FREE(view);
 269 }
 270
 271 #define EMIT_STATE(state_name, src_value) \
 272    etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
 273
 274 #define EMIT_STATE_FIXP(state_name, src_value) \
 275    etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
 276
 277 #define EMIT_STATE_RELOC(state_name, src_value) \
 278    etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
 279
 280 /* Emit plain (non-descriptor) texture state */
 281 static void
 282 etna_emit_texture_state(struct etna_context *ctx)
 283 {
 284    struct etna_cmd_stream *stream = ctx->stream;
 285    struct etna_screen *screen = ctx->screen;
 286    uint32_t active_samplers = active_samplers_bits(ctx);
 287    uint32_t dirty = ctx->dirty;
 288    struct etna_coalesce coalesce;
 289
 290    etna_coalesce_start(stream, &coalesce);
 291
 292    if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
 293       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 294          if ((1 << x) & active_samplers) {
 295             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 296             /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
 297          }
 298       }
 299       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 300          if ((1 << x) & active_samplers) {
 301             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 302             /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
 303          }
 304       }
 305       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 306          if ((1 << x) & active_samplers) {
 307             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 308             /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
 309          }
 310       }
 311       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 312          if ((1 << x) & active_samplers) {
 313             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 314             /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
 315          }
 316       }
 317    }
 318    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
 319       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 320          uint32_t val = 0; /* 0 == sampler inactive */
 321
 322          /* set active samplers to their configuration value (determined by both
 323           * the sampler state and sampler view) */
 324          if ((1 << x) & active_samplers) {
 325             struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
 326             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 327
 328             val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
 329                   sv->TE_SAMPLER_CONFIG0;
 330          }
 331
 332          /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
 333       }
 334    }
 335    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 336       struct etna_sampler_view *sv;
 337
 338       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 339          if ((1 << x) & active_samplers) {
 340             sv = etna_sampler_view(ctx->sampler_view[x]);
 341             /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
 342          }
 343       }
 344       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 345          if ((1 << x) & active_samplers) {
 346             sv = etna_sampler_view(ctx->sampler_view[x]);
 347             /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), sv->TE_SAMPLER_LOG_SIZE);
 348          }
 349       }
 350    }
 351    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
 352       struct etna_sampler_state *ss;
 353       struct etna_sampler_view *sv;
 354
 355       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 356          if ((1 << x) & active_samplers) {
 357             ss = etna_sampler_state(ctx->sampler[x]);
 358             sv = etna_sampler_view(ctx->sampler_view[x]);
 359
 360             unsigned max_lod = MAX2(MIN2(ss->max_lod, sv->max_lod), ss->max_lod_min);
 361
 362             /* min and max lod is determined both by the sampler and the view */
 363             /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
 364                                  ss->TE_SAMPLER_LOD_CONFIG |
 365                                  VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
 366                                  VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss->min_lod, sv->min_lod)));
 367          }
 368       }
 369       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 370          if ((1 << x) & active_samplers) {
 371             ss = etna_sampler_state(ctx->sampler[x]);
 372             sv = etna_sampler_view(ctx->sampler_view[x]);
 373
 374             /*02180*/ EMIT_STATE(TE_SAMPLER_3D_CONFIG(x), ss->TE_SAMPLER_3D_CONFIG |
 375                                                           sv->TE_SAMPLER_3D_CONFIG);
 376          }
 377       }
 378       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 379          if ((1 << x) & active_samplers) {
 380             ss = etna_sampler_state(ctx->sampler[x]);
 381             sv = etna_sampler_view(ctx->sampler_view[x]);
 382
 383             /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->TE_SAMPLER_CONFIG1 |
 384                                                         sv->TE_SAMPLER_CONFIG1 |
 385                                                         COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
 386          }
 387       }
 388    }
 389    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 390       for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
 391          for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 392             if ((1 << x) & active_samplers) {
 393                struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 394                /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y),&sv->TE_SAMPLER_LOD_ADDR[y]);
 395             }
 396          }
 397       }
 398    }
 399    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 400       for (int y = 0; y < VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN; ++y) {
 401          for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 402             if ((1 << x) & active_samplers) {
 403                struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 404                /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(x, y), sv->TE_SAMPLER_LINEAR_STRIDE[y]);
 405             }
 406          }
 407       }
 408    }
 409    if (unlikely(screen->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
 410       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 411          if ((1 << x) & active_samplers) {
 412             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 413             /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
 414          }
 415       }
 416    }
 417    if (unlikely(screen->specs.halti >= 1 && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
 418       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 419          if ((1 << x) & active_samplers) {
 420             struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
 421             /*10700*/ EMIT_STATE(NTE_SAMPLER_BASELOD(x), ss->NTE_SAMPLER_BASELOD);
 422          }
 423       }
 424    }
 425    etna_coalesce_end(stream, &coalesce);
 426 }
 427
 428 #undef EMIT_STATE
 429 #undef EMIT_STATE_FIXP
 430 #undef EMIT_STATE_RELOC
 431
 432 static struct etna_sampler_ts*
 433 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
 434 {
 435    struct etna_sampler_view *sv = etna_sampler_view(pview);
 436    return &sv->ts;
 437 }
 438
 439 void
 440 etna_texture_state_init(struct pipe_context *pctx)
 441 {
 442    struct etna_context *ctx = etna_context(pctx);
 443    DBG("etnaviv: Using state-based texturing");
 444    ctx->base.create_sampler_state = etna_create_sampler_state_state;
 445    ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
 446    ctx->base.create_sampler_view = etna_create_sampler_view_state;
 447    ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
 448    ctx->emit_texture_state = etna_emit_texture_state;
 449    ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
 450 }