2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_zsa.h"
29 #include "etnaviv_context.h"
30 #include "etnaviv_screen.h"
31 #include "etnaviv_translate.h"
32 #include "util/u_memory.h"
34 #include "hw/common.xml.h"
37 etna_zsa_state_create(struct pipe_context
*pctx
,
38 const struct pipe_depth_stencil_alpha_state
*so
)
40 struct etna_context
*ctx
= etna_context(pctx
);
41 struct etna_zsa_state
*cs
= CALLOC_STRUCT(etna_zsa_state
);
48 /* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */
49 bool early_z
= !VIV_FEATURE(ctx
->screen
, chipFeatures
, NO_EARLY_Z
);
51 (!so
->depth
.enabled
|| so
->depth
.func
== PIPE_FUNC_ALWAYS
) &&
54 /* Set operations to KEEP if write mask is 0.
55 * When we don't do this, the depth buffer is written for the entire primitive
56 * instead of just where the stencil condition holds (GC600 rev 0x0019, without
57 * feature CORRECT_STENCIL).
58 * Not sure if this is a hardware bug or just a strange edge case. */
59 #if 0 /* TODO: It looks like a hardware bug */
60 for(int i
=0; i
<2; ++i
)
62 if(so
->stencil
[i
].writemask
== 0)
64 so
->stencil
[i
].fail_op
= so
->stencil
[i
].zfail_op
= so
->stencil
[i
].zpass_op
= PIPE_STENCIL_OP_KEEP
;
69 /* Determine whether to enable early z reject. Don't enable it when any of
70 * the stencil-modifying functions is used. */
71 if (so
->stencil
[0].enabled
) {
72 if (so
->stencil
[0].func
!= PIPE_FUNC_ALWAYS
||
73 (so
->stencil
[1].enabled
&& so
->stencil
[1].func
!= PIPE_FUNC_ALWAYS
))
76 if (so
->stencil
[0].fail_op
!= PIPE_STENCIL_OP_KEEP
||
77 so
->stencil
[0].zfail_op
!= PIPE_STENCIL_OP_KEEP
||
78 so
->stencil
[0].zpass_op
!= PIPE_STENCIL_OP_KEEP
) {
79 disable_zs
= early_z
= false;
80 } else if (so
->stencil
[1].enabled
) {
81 if (so
->stencil
[1].fail_op
!= PIPE_STENCIL_OP_KEEP
||
82 so
->stencil
[1].zfail_op
!= PIPE_STENCIL_OP_KEEP
||
83 so
->stencil
[1].zpass_op
!= PIPE_STENCIL_OP_KEEP
) {
84 disable_zs
= early_z
= false;
89 /* Disable early z reject when no depth test is enabled.
90 * This avoids having to sample depth even though we know it's going to
92 if (so
->depth
.enabled
== false || so
->depth
.func
== PIPE_FUNC_ALWAYS
)
95 /* compare funcs have 1 to 1 mapping */
97 VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(so
->depth
.enabled
? so
->depth
.func
99 COND(so
->depth
.writemask
, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE
) |
100 COND(early_z
, VIVS_PE_DEPTH_CONFIG_EARLY_Z
) |
101 /* this bit changed meaning with HALTI5: */
102 COND(disable_zs
&& ctx
->specs
.halti
< 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS
);
104 COND(so
->alpha
.enabled
, VIVS_PE_ALPHA_OP_ALPHA_TEST
) |
105 VIVS_PE_ALPHA_OP_ALPHA_FUNC(so
->alpha
.func
) |
106 VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so
->alpha
.ref_value
));
108 for (unsigned i
= 0; i
< 2; i
++) {
109 cs
->PE_STENCIL_OP
[i
] =
110 VIVS_PE_STENCIL_OP_FUNC_FRONT(so
->stencil
[i
].func
) |
111 VIVS_PE_STENCIL_OP_FUNC_BACK(so
->stencil
[!i
].func
) |
112 VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so
->stencil
[i
].fail_op
)) |
113 VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so
->stencil
[!i
].fail_op
)) |
114 VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so
->stencil
[i
].zfail_op
)) |
115 VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so
->stencil
[!i
].zfail_op
)) |
116 VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so
->stencil
[i
].zpass_op
)) |
117 VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so
->stencil
[!i
].zpass_op
));
118 cs
->PE_STENCIL_CONFIG
[i
] =
119 translate_stencil_mode(so
->stencil
[i
].enabled
, so
->stencil
[!i
].enabled
) |
120 VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so
->stencil
[i
].valuemask
) |
121 VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so
->stencil
[i
].writemask
);
122 cs
->PE_STENCIL_CONFIG_EXT2
[i
] =
123 VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(so
->stencil
[!i
].valuemask
) |
124 VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(so
->stencil
[!i
].writemask
);
127 /* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */