etnaviv: Update includes from rnndb
[mesa.git] / src / gallium / drivers / etnaviv / hw / isa.xml.h
1 #ifndef ISA_XML
2 #define ISA_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9
10 The rules-ng-ng source files this header was generated from are:
11 - isa.xml ( 34392 bytes, from 2017-04-13 12:44:36)
12 - copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
13
14 Copyright (C) 2012-2017 by the following authors:
15 - Wladimir J. van der Laan <laanwj@gmail.com>
16 - Christian Gmeiner <christian.gmeiner@gmail.com>
17 - Lucas Stach <l.stach@pengutronix.de>
18 - Russell King <rmk@arm.linux.org.uk>
19
20 Permission is hereby granted, free of charge, to any person obtaining a
21 copy of this software and associated documentation files (the "Software"),
22 to deal in the Software without restriction, including without limitation
23 the rights to use, copy, modify, merge, publish, distribute, sub license,
24 and/or sell copies of the Software, and to permit persons to whom the
25 Software is furnished to do so, subject to the following conditions:
26
27 The above copyright notice and this permission notice (including the
28 next paragraph) shall be included in all copies or substantial portions
29 of the Software.
30
31 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
32 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
34 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
35 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
36 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
37 DEALINGS IN THE SOFTWARE.
38 */
39
40
41 #define INST_OPCODE_NOP 0x00000000
42 #define INST_OPCODE_ADD 0x00000001
43 #define INST_OPCODE_MAD 0x00000002
44 #define INST_OPCODE_MUL 0x00000003
45 #define INST_OPCODE_DST 0x00000004
46 #define INST_OPCODE_DP3 0x00000005
47 #define INST_OPCODE_DP4 0x00000006
48 #define INST_OPCODE_DSX 0x00000007
49 #define INST_OPCODE_DSY 0x00000008
50 #define INST_OPCODE_MOV 0x00000009
51 #define INST_OPCODE_MOVAR 0x0000000a
52 #define INST_OPCODE_MOVAF 0x0000000b
53 #define INST_OPCODE_RCP 0x0000000c
54 #define INST_OPCODE_RSQ 0x0000000d
55 #define INST_OPCODE_LITP 0x0000000e
56 #define INST_OPCODE_SELECT 0x0000000f
57 #define INST_OPCODE_SET 0x00000010
58 #define INST_OPCODE_EXP 0x00000011
59 #define INST_OPCODE_LOG 0x00000012
60 #define INST_OPCODE_FRC 0x00000013
61 #define INST_OPCODE_CALL 0x00000014
62 #define INST_OPCODE_RET 0x00000015
63 #define INST_OPCODE_BRANCH 0x00000016
64 #define INST_OPCODE_TEXKILL 0x00000017
65 #define INST_OPCODE_TEXLD 0x00000018
66 #define INST_OPCODE_TEXLDB 0x00000019
67 #define INST_OPCODE_TEXLDD 0x0000001a
68 #define INST_OPCODE_TEXLDL 0x0000001b
69 #define INST_OPCODE_TEXLDPCF 0x0000001c
70 #define INST_OPCODE_REP 0x0000001d
71 #define INST_OPCODE_ENDREP 0x0000001e
72 #define INST_OPCODE_LOOP 0x0000001f
73 #define INST_OPCODE_ENDLOOP 0x00000020
74 #define INST_OPCODE_SQRT 0x00000021
75 #define INST_OPCODE_SIN 0x00000022
76 #define INST_OPCODE_COS 0x00000023
77 #define INST_OPCODE_FLOOR 0x00000025
78 #define INST_OPCODE_CEIL 0x00000026
79 #define INST_OPCODE_SIGN 0x00000027
80 #define INST_OPCODE_ADDLO 0x00000028
81 #define INST_OPCODE_MULLO 0x00000029
82 #define INST_OPCODE_BARRIER 0x0000002a
83 #define INST_OPCODE_SWIZZLE 0x0000002b
84 #define INST_OPCODE_I2I 0x0000002c
85 #define INST_OPCODE_I2F 0x0000002d
86 #define INST_OPCODE_F2I 0x0000002e
87 #define INST_OPCODE_F2IRND 0x0000002f
88 #define INST_OPCODE_F2I7 0x00000030
89 #define INST_OPCODE_CMP 0x00000031
90 #define INST_OPCODE_LOAD 0x00000032
91 #define INST_OPCODE_STORE 0x00000033
92 #define INST_OPCODE_COPYSIGN 0x00000034
93 #define INST_OPCODE_GETEXP 0x00000035
94 #define INST_OPCODE_GETMANT 0x00000036
95 #define INST_OPCODE_NAN 0x00000037
96 #define INST_OPCODE_NEXTAFTER 0x00000038
97 #define INST_OPCODE_ROUNDEVEN 0x00000039
98 #define INST_OPCODE_ROUNDAWAY 0x0000003a
99 #define INST_OPCODE_IADDSAT 0x0000003b
100 #define INST_OPCODE_IMULLO0 0x0000003c
101 #define INST_OPCODE_IMULLO1 0x0000003d
102 #define INST_OPCODE_IMULLOSAT0 0x0000003e
103 #define INST_OPCODE_IMULLOSAT1 0x0000003f
104 #define INST_OPCODE_IMULHI0 0x00000040
105 #define INST_OPCODE_IMULHI1 0x00000041
106 #define INST_OPCODE_IMUL0 0x00000042
107 #define INST_OPCODE_IMUL1 0x00000043
108 #define INST_OPCODE_IDIV0 0x00000044
109 #define INST_OPCODE_IDIV1 0x00000045
110 #define INST_OPCODE_IDIV2 0x00000046
111 #define INST_OPCODE_IDIV3 0x00000047
112 #define INST_OPCODE_IMOD0 0x00000048
113 #define INST_OPCODE_IMOD1 0x00000049
114 #define INST_OPCODE_IMOD2 0x0000004a
115 #define INST_OPCODE_IMOD3 0x0000004b
116 #define INST_OPCODE_IMADLO0 0x0000004c
117 #define INST_OPCODE_IMADLO1 0x0000004d
118 #define INST_OPCODE_IMADLOSAT0 0x0000004e
119 #define INST_OPCODE_IMADLOSAT1 0x0000004f
120 #define INST_OPCODE_IMADHI0 0x00000050
121 #define INST_OPCODE_IMADHI1 0x00000051
122 #define INST_OPCODE_IMADHISAT0 0x00000052
123 #define INST_OPCODE_IMADHISAT1 0x00000053
124 #define INST_OPCODE_HALFADD 0x00000054
125 #define INST_OPCODE_HALFADDINC 0x00000055
126 #define INST_OPCODE_MOVAI 0x00000056
127 #define INST_OPCODE_IABS 0x00000057
128 #define INST_OPCODE_LEADZERO 0x00000058
129 #define INST_OPCODE_LSHIFT 0x00000059
130 #define INST_OPCODE_RSHIFT 0x0000005a
131 #define INST_OPCODE_ROTATE 0x0000005b
132 #define INST_OPCODE_OR 0x0000005c
133 #define INST_OPCODE_AND 0x0000005d
134 #define INST_OPCODE_XOR 0x0000005e
135 #define INST_OPCODE_NOT 0x0000005f
136 #define INST_OPCODE_BITSELECT 0x00000060
137 #define INST_OPCODE_POPCOUNT 0x00000061
138 #define INST_OPCODE_STOREB 0x00000062
139 #define INST_OPCODE_RGB2YUV 0x00000063
140 #define INST_OPCODE_DIV 0x00000064
141 #define INST_OPCODE_ATOM_ADD 0x00000065
142 #define INST_OPCODE_ATOM_XCHG 0x00000066
143 #define INST_OPCODE_ATOM_CMP_XCHG 0x00000067
144 #define INST_OPCODE_ATOM_MIN 0x00000068
145 #define INST_OPCODE_ATOM_MAX 0x00000069
146 #define INST_OPCODE_ATOM_OR 0x0000006a
147 #define INST_OPCODE_ATOM_AND 0x0000006b
148 #define INST_OPCODE_ATOM_XOR 0x0000006c
149 #define INST_OPCODE_BIT_REV 0x0000006d
150 #define INST_OPCODE_BYTE_REV 0x0000006e
151 #define INST_OPCODE_TEXLDLPCF 0x0000006f
152 #define INST_OPCODE_TEXLDGPCF 0x00000070
153 #define INST_OPCODE_PACK 0x00000071
154 #define INST_OPCODE_CONV 0x00000072
155 #define INST_OPCODE_DP2 0x00000073
156 #define INST_OPCODE_NORM_DP2 0x00000074
157 #define INST_OPCODE_NORM_DP3 0x00000075
158 #define INST_OPCODE_NORM_DP4 0x00000076
159 #define INST_OPCODE_NORM_MUL 0x00000077
160 #define INST_OPCODE_STORE_ATTR 0x00000078
161 #define INST_OPCODE_LOAD_ATTR 0x00000079
162 #define INST_OPCODE_EMIT 0x0000007a
163 #define INST_OPCODE_RESTART 0x0000007b
164 #define INST_OPCODE_NOP7C 0x0000007c
165 #define INST_OPCODE_NOP7D 0x0000007d
166 #define INST_OPCODE_NOP7E 0x0000007e
167 #define INST_OPCODE_NOP7F 0x0000007f
168 #define INST_CONDITION_TRUE 0x00000000
169 #define INST_CONDITION_GT 0x00000001
170 #define INST_CONDITION_LT 0x00000002
171 #define INST_CONDITION_GE 0x00000003
172 #define INST_CONDITION_LE 0x00000004
173 #define INST_CONDITION_EQ 0x00000005
174 #define INST_CONDITION_NE 0x00000006
175 #define INST_CONDITION_AND 0x00000007
176 #define INST_CONDITION_OR 0x00000008
177 #define INST_CONDITION_XOR 0x00000009
178 #define INST_CONDITION_NOT 0x0000000a
179 #define INST_CONDITION_NZ 0x0000000b
180 #define INST_CONDITION_GEZ 0x0000000c
181 #define INST_CONDITION_GZ 0x0000000d
182 #define INST_CONDITION_LEZ 0x0000000e
183 #define INST_CONDITION_LZ 0x0000000f
184 #define INST_RGROUP_TEMP 0x00000000
185 #define INST_RGROUP_INTERNAL 0x00000001
186 #define INST_RGROUP_UNIFORM_0 0x00000002
187 #define INST_RGROUP_UNIFORM_1 0x00000003
188 #define INST_AMODE_DIRECT 0x00000000
189 #define INST_AMODE_ADD_A_X 0x00000001
190 #define INST_AMODE_ADD_A_Y 0x00000002
191 #define INST_AMODE_ADD_A_Z 0x00000003
192 #define INST_AMODE_ADD_A_W 0x00000004
193 #define INST_SWIZ_COMP_X 0x00000000
194 #define INST_SWIZ_COMP_Y 0x00000001
195 #define INST_SWIZ_COMP_Z 0x00000002
196 #define INST_SWIZ_COMP_W 0x00000003
197 #define INST_TYPE_F32 0x00000000
198 #define INST_TYPE_S32 0x00000001
199 #define INST_TYPE_S8 0x00000002
200 #define INST_TYPE_U16 0x00000003
201 #define INST_TYPE_F16 0x00000004
202 #define INST_TYPE_S16 0x00000005
203 #define INST_TYPE_U32 0x00000006
204 #define INST_TYPE_U8 0x00000007
205 #define INST_COMPS_X 0x00000001
206 #define INST_COMPS_Y 0x00000002
207 #define INST_COMPS_Z 0x00000004
208 #define INST_COMPS_W 0x00000008
209 #define INST_SWIZ_X__MASK 0x00000003
210 #define INST_SWIZ_X__SHIFT 0
211 #define INST_SWIZ_X(x) (((x) << INST_SWIZ_X__SHIFT) & INST_SWIZ_X__MASK)
212 #define INST_SWIZ_Y__MASK 0x0000000c
213 #define INST_SWIZ_Y__SHIFT 2
214 #define INST_SWIZ_Y(x) (((x) << INST_SWIZ_Y__SHIFT) & INST_SWIZ_Y__MASK)
215 #define INST_SWIZ_Z__MASK 0x00000030
216 #define INST_SWIZ_Z__SHIFT 4
217 #define INST_SWIZ_Z(x) (((x) << INST_SWIZ_Z__SHIFT) & INST_SWIZ_Z__MASK)
218 #define INST_SWIZ_W__MASK 0x000000c0
219 #define INST_SWIZ_W__SHIFT 6
220 #define INST_SWIZ_W(x) (((x) << INST_SWIZ_W__SHIFT) & INST_SWIZ_W__MASK)
221 #define VIV_ISA_WORD_0 0x00000000
222 #define VIV_ISA_WORD_0_OPCODE__MASK 0x0000003f
223 #define VIV_ISA_WORD_0_OPCODE__SHIFT 0
224 #define VIV_ISA_WORD_0_OPCODE(x) (((x) << VIV_ISA_WORD_0_OPCODE__SHIFT) & VIV_ISA_WORD_0_OPCODE__MASK)
225 #define VIV_ISA_WORD_0_COND__MASK 0x000007c0
226 #define VIV_ISA_WORD_0_COND__SHIFT 6
227 #define VIV_ISA_WORD_0_COND(x) (((x) << VIV_ISA_WORD_0_COND__SHIFT) & VIV_ISA_WORD_0_COND__MASK)
228 #define VIV_ISA_WORD_0_SAT 0x00000800
229 #define VIV_ISA_WORD_0_DST_USE 0x00001000
230 #define VIV_ISA_WORD_0_DST_AMODE__MASK 0x0000e000
231 #define VIV_ISA_WORD_0_DST_AMODE__SHIFT 13
232 #define VIV_ISA_WORD_0_DST_AMODE(x) (((x) << VIV_ISA_WORD_0_DST_AMODE__SHIFT) & VIV_ISA_WORD_0_DST_AMODE__MASK)
233 #define VIV_ISA_WORD_0_DST_REG__MASK 0x007f0000
234 #define VIV_ISA_WORD_0_DST_REG__SHIFT 16
235 #define VIV_ISA_WORD_0_DST_REG(x) (((x) << VIV_ISA_WORD_0_DST_REG__SHIFT) & VIV_ISA_WORD_0_DST_REG__MASK)
236 #define VIV_ISA_WORD_0_DST_COMPS__MASK 0x07800000
237 #define VIV_ISA_WORD_0_DST_COMPS__SHIFT 23
238 #define VIV_ISA_WORD_0_DST_COMPS(x) (((x) << VIV_ISA_WORD_0_DST_COMPS__SHIFT) & VIV_ISA_WORD_0_DST_COMPS__MASK)
239 #define VIV_ISA_WORD_0_TEX_ID__MASK 0xf8000000
240 #define VIV_ISA_WORD_0_TEX_ID__SHIFT 27
241 #define VIV_ISA_WORD_0_TEX_ID(x) (((x) << VIV_ISA_WORD_0_TEX_ID__SHIFT) & VIV_ISA_WORD_0_TEX_ID__MASK)
242
243 #define VIV_ISA_WORD_1 0x00000004
244 #define VIV_ISA_WORD_1_TEX_AMODE__MASK 0x00000007
245 #define VIV_ISA_WORD_1_TEX_AMODE__SHIFT 0
246 #define VIV_ISA_WORD_1_TEX_AMODE(x) (((x) << VIV_ISA_WORD_1_TEX_AMODE__SHIFT) & VIV_ISA_WORD_1_TEX_AMODE__MASK)
247 #define VIV_ISA_WORD_1_TEX_SWIZ__MASK 0x000007f8
248 #define VIV_ISA_WORD_1_TEX_SWIZ__SHIFT 3
249 #define VIV_ISA_WORD_1_TEX_SWIZ(x) (((x) << VIV_ISA_WORD_1_TEX_SWIZ__SHIFT) & VIV_ISA_WORD_1_TEX_SWIZ__MASK)
250 #define VIV_ISA_WORD_1_SRC0_USE 0x00000800
251 #define VIV_ISA_WORD_1_SRC0_REG__MASK 0x001ff000
252 #define VIV_ISA_WORD_1_SRC0_REG__SHIFT 12
253 #define VIV_ISA_WORD_1_SRC0_REG(x) (((x) << VIV_ISA_WORD_1_SRC0_REG__SHIFT) & VIV_ISA_WORD_1_SRC0_REG__MASK)
254 #define VIV_ISA_WORD_1_TYPE_BIT2 0x00200000
255 #define VIV_ISA_WORD_1_SRC0_SWIZ__MASK 0x3fc00000
256 #define VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT 22
257 #define VIV_ISA_WORD_1_SRC0_SWIZ(x) (((x) << VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT) & VIV_ISA_WORD_1_SRC0_SWIZ__MASK)
258 #define VIV_ISA_WORD_1_SRC0_NEG 0x40000000
259 #define VIV_ISA_WORD_1_SRC0_ABS 0x80000000
260
261 #define VIV_ISA_WORD_2 0x00000008
262 #define VIV_ISA_WORD_2_SRC0_AMODE__MASK 0x00000007
263 #define VIV_ISA_WORD_2_SRC0_AMODE__SHIFT 0
264 #define VIV_ISA_WORD_2_SRC0_AMODE(x) (((x) << VIV_ISA_WORD_2_SRC0_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC0_AMODE__MASK)
265 #define VIV_ISA_WORD_2_SRC0_RGROUP__MASK 0x00000038
266 #define VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT 3
267 #define VIV_ISA_WORD_2_SRC0_RGROUP(x) (((x) << VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT) & VIV_ISA_WORD_2_SRC0_RGROUP__MASK)
268 #define VIV_ISA_WORD_2_SRC1_USE 0x00000040
269 #define VIV_ISA_WORD_2_SRC1_REG__MASK 0x0000ff80
270 #define VIV_ISA_WORD_2_SRC1_REG__SHIFT 7
271 #define VIV_ISA_WORD_2_SRC1_REG(x) (((x) << VIV_ISA_WORD_2_SRC1_REG__SHIFT) & VIV_ISA_WORD_2_SRC1_REG__MASK)
272 #define VIV_ISA_WORD_2_OPCODE_BIT6 0x00010000
273 #define VIV_ISA_WORD_2_SRC1_SWIZ__MASK 0x01fe0000
274 #define VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT 17
275 #define VIV_ISA_WORD_2_SRC1_SWIZ(x) (((x) << VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT) & VIV_ISA_WORD_2_SRC1_SWIZ__MASK)
276 #define VIV_ISA_WORD_2_SRC1_NEG 0x02000000
277 #define VIV_ISA_WORD_2_SRC1_ABS 0x04000000
278 #define VIV_ISA_WORD_2_SRC1_AMODE__MASK 0x38000000
279 #define VIV_ISA_WORD_2_SRC1_AMODE__SHIFT 27
280 #define VIV_ISA_WORD_2_SRC1_AMODE(x) (((x) << VIV_ISA_WORD_2_SRC1_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC1_AMODE__MASK)
281 #define VIV_ISA_WORD_2_TYPE_BIT01__MASK 0xc0000000
282 #define VIV_ISA_WORD_2_TYPE_BIT01__SHIFT 30
283 #define VIV_ISA_WORD_2_TYPE_BIT01(x) (((x) << VIV_ISA_WORD_2_TYPE_BIT01__SHIFT) & VIV_ISA_WORD_2_TYPE_BIT01__MASK)
284
285 #define VIV_ISA_WORD_3 0x0000000c
286 #define VIV_ISA_WORD_3_SRC1_RGROUP__MASK 0x00000007
287 #define VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT 0
288 #define VIV_ISA_WORD_3_SRC1_RGROUP(x) (((x) << VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC1_RGROUP__MASK)
289 #define VIV_ISA_WORD_3_SRC2_IMM__MASK 0x003fff80
290 #define VIV_ISA_WORD_3_SRC2_IMM__SHIFT 7
291 #define VIV_ISA_WORD_3_SRC2_IMM(x) (((x) << VIV_ISA_WORD_3_SRC2_IMM__SHIFT) & VIV_ISA_WORD_3_SRC2_IMM__MASK)
292 #define VIV_ISA_WORD_3_SRC2_USE 0x00000008
293 #define VIV_ISA_WORD_3_SRC2_REG__MASK 0x00001ff0
294 #define VIV_ISA_WORD_3_SRC2_REG__SHIFT 4
295 #define VIV_ISA_WORD_3_SRC2_REG(x) (((x) << VIV_ISA_WORD_3_SRC2_REG__SHIFT) & VIV_ISA_WORD_3_SRC2_REG__MASK)
296 #define VIV_ISA_WORD_3_UNK3_13 0x00002000
297 #define VIV_ISA_WORD_3_SRC2_SWIZ__MASK 0x003fc000
298 #define VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT 14
299 #define VIV_ISA_WORD_3_SRC2_SWIZ(x) (((x) << VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT) & VIV_ISA_WORD_3_SRC2_SWIZ__MASK)
300 #define VIV_ISA_WORD_3_SRC2_NEG 0x00400000
301 #define VIV_ISA_WORD_3_SRC2_ABS 0x00800000
302 #define VIV_ISA_WORD_3_UNK3_24 0x01000000
303 #define VIV_ISA_WORD_3_SRC2_AMODE__MASK 0x0e000000
304 #define VIV_ISA_WORD_3_SRC2_AMODE__SHIFT 25
305 #define VIV_ISA_WORD_3_SRC2_AMODE(x) (((x) << VIV_ISA_WORD_3_SRC2_AMODE__SHIFT) & VIV_ISA_WORD_3_SRC2_AMODE__MASK)
306 #define VIV_ISA_WORD_3_SRC2_RGROUP__MASK 0x70000000
307 #define VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT 28
308 #define VIV_ISA_WORD_3_SRC2_RGROUP(x) (((x) << VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC2_RGROUP__MASK)
309 #define VIV_ISA_WORD_3_UNK3_31 0x80000000
310
311
312 #endif /* ISA_XML */