4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/a2xx.xml ( 30127 bytes, from 2013-05-05 18:29:35)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
16 Copyright (C) 2013 by the following authors:
17 - Rob Clark <robdclark@gmail.com> (robclark)
19 Permission is hereby granted, free of charge, to any person obtaining
20 a copy of this software and associated documentation files (the
21 "Software"), to deal in the Software without restriction, including
22 without limitation the rights to use, copy, modify, merge, publish,
23 distribute, sublicense, and/or sell copies of the Software, and to
24 permit persons to whom the Software is furnished to do so, subject to
25 the following conditions:
27 The above copyright notice and this permission notice (including the
28 next paragraph) shall be included in all copies or substantial
29 portions of the Software.
31 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
34 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
35 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
36 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 enum a2xx_rb_dither_type
{
46 enum a2xx_colorformatx
{
55 COLORX_16_16_FLOAT
= 8,
56 COLORX_16_16_16_16_FLOAT
= 9,
58 COLORX_32_32_FLOAT
= 11,
59 COLORX_32_32_32_32_FLOAT
= 12,
64 enum a2xx_sq_surfaceformat
{
92 FMT_16_16_EXPAND
= 28,
93 FMT_16_16_16_16_EXPAND
= 29,
96 FMT_16_16_16_16_FLOAT
= 32,
101 FMT_32_32_FLOAT
= 37,
102 FMT_32_32_32_32_FLOAT
= 38,
107 FMT_8_INTERLACED
= 43,
108 FMT_32_AS_8_INTERLACED
= 44,
109 FMT_32_AS_8_8_INTERLACED
= 45,
110 FMT_16_INTERLACED
= 46,
111 FMT_16_MPEG_INTERLACED
= 47,
112 FMT_16_16_MPEG_INTERLACED
= 48,
114 FMT_8_8_8_8_AS_16_16_16_16
= 50,
115 FMT_DXT1_AS_16_16_16_16
= 51,
116 FMT_DXT2_3_AS_16_16_16_16
= 52,
117 FMT_DXT4_5_AS_16_16_16_16
= 53,
118 FMT_2_10_10_10_AS_16_16_16_16
= 54,
119 FMT_10_11_11_AS_16_16_16_16
= 55,
120 FMT_11_11_10_AS_16_16_16_16
= 56,
121 FMT_32_32_32_FLOAT
= 57,
125 FMT_DXT3A_AS_1_1_1_1
= 61,
128 enum a2xx_sq_ps_vtx_mode
{
129 POSITION_1_VECTOR
= 0,
130 POSITION_2_VECTORS_UNUSED
= 1,
131 POSITION_2_VECTORS_SPRITE
= 2,
132 POSITION_2_VECTORS_EDGE
= 3,
133 POSITION_2_VECTORS_KILL
= 4,
134 POSITION_2_VECTORS_SPRITE_KILL
= 5,
135 POSITION_2_VECTORS_EDGE_KILL
= 6,
139 enum a2xx_sq_sample_cntl
{
142 CENTROIDS_AND_CENTERS
= 2,
145 enum a2xx_dx_clip_space
{
150 enum a2xx_pa_su_sc_polymode
{
155 enum a2xx_rb_edram_mode
{
162 enum a2xx_pa_sc_pattern_bit_order
{
167 enum a2xx_pa_sc_auto_reset_cntl
{
173 enum a2xx_pa_pixcenter
{
178 enum a2xx_pa_roundmode
{
185 enum a2xx_pa_quantmode
{
193 enum a2xx_rb_copy_sample_select
{
206 SQ_TEX_CLAMP_LAST_TEXEL
= 2,
207 SQ_TEX_MIRROR_ONCE_LAST_TEXEL
= 3,
208 SQ_TEX_CLAMP_HALF_BORDER
= 4,
209 SQ_TEX_MIRROR_ONCE_HALF_BORDER
= 5,
210 SQ_TEX_CLAMP_BORDER
= 6,
211 SQ_TEX_MIRROR_ONCE_BORDER
= 7,
224 SQ_TEX_FILTER_POINT
= 0,
225 SQ_TEX_FILTER_BILINEAR
= 1,
226 SQ_TEX_FILTER_BICUBIC
= 2,
229 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001
231 #define REG_A2XX_RBBM_CNTL 0x0000003b
233 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c
235 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0
237 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1
239 #define REG_A2XX_CP_RB_BASE 0x000001c0
241 #define REG_A2XX_CP_RB_CNTL 0x000001c1
243 #define REG_A2XX_CP_RB_RPTR_ADDR 0x000001c3
245 #define REG_A2XX_CP_RB_RPTR 0x000001c4
247 #define REG_A2XX_CP_RB_WPTR 0x000001c5
249 #define REG_A2XX_CP_RB_WPTR_DELAY 0x000001c6
251 #define REG_A2XX_CP_RB_RPTR_WR 0x000001c7
253 #define REG_A2XX_CP_RB_WPTR_BASE 0x000001c8
255 #define REG_A2XX_CP_QUEUE_THRESHOLDS 0x000001d5
257 #define REG_A2XX_SCRATCH_UMSK 0x000001dc
259 #define REG_A2XX_SCRATCH_ADDR 0x000001dd
261 #define REG_A2XX_CP_STATE_DEBUG_INDEX 0x000001ec
263 #define REG_A2XX_CP_STATE_DEBUG_DATA 0x000001ed
265 #define REG_A2XX_CP_INT_CNTL 0x000001f2
267 #define REG_A2XX_CP_INT_STATUS 0x000001f3
269 #define REG_A2XX_CP_INT_ACK 0x000001f4
271 #define REG_A2XX_CP_ME_CNTL 0x000001f6
273 #define REG_A2XX_CP_ME_STATUS 0x000001f7
275 #define REG_A2XX_CP_ME_RAM_WADDR 0x000001f8
277 #define REG_A2XX_CP_ME_RAM_RADDR 0x000001f9
279 #define REG_A2XX_CP_ME_RAM_DATA 0x000001fa
281 #define REG_A2XX_CP_DEBUG 0x000001fc
283 #define REG_A2XX_CP_CSQ_RB_STAT 0x000001fd
285 #define REG_A2XX_CP_CSQ_IB1_STAT 0x000001fe
287 #define REG_A2XX_CP_CSQ_IB2_STAT 0x000001ff
289 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
291 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
293 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398
295 #define REG_A2XX_RBBM_DEBUG 0x0000039b
297 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c
299 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d
301 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0
303 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1
305 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3
307 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4
309 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5
311 #define REG_A2XX_RBBM_INT_ACK 0x000003b6
313 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7
315 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9
317 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa
319 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444
321 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445
323 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446
325 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
327 #define REG_A2XX_CP_ST_BASE 0x0000044d
329 #define REG_A2XX_CP_ST_BUFSZ 0x0000044e
331 #define REG_A2XX_CP_IB1_BASE 0x00000458
333 #define REG_A2XX_CP_IB1_BUFSZ 0x00000459
335 #define REG_A2XX_CP_IB2_BASE 0x0000045a
337 #define REG_A2XX_CP_IB2_BUFSZ 0x0000045b
339 #define REG_A2XX_CP_STAT 0x0000047f
341 #define REG_A2XX_SCRATCH_REG0 0x00000578
343 #define REG_A2XX_SCRATCH_REG2 0x0000057a
345 #define REG_A2XX_RBBM_STATUS 0x000005d0
347 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
348 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
349 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
350 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val
)
352 return ((val
>> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT
) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK
;
354 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
355 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5
356 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val
)
358 return ((val
>> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT
) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK
;
361 #define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
363 #define REG_A2XX_VSC_PIPE_CONFIG(i0) (0x00000c06 + 0x3*(i0))
365 #define REG_A2XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c07 + 0x3*(i0))
367 #define REG_A2XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c08 + 0x3*(i0))
369 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38
371 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39
373 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44
375 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80
377 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80
379 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81
381 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81
383 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86
385 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00
387 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01
389 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02
391 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05
393 #define REG_A2XX_SQ_INT_CNTL 0x00000d34
395 #define REG_A2XX_SQ_INT_STATUS 0x00000d35
397 #define REG_A2XX_SQ_INT_ACK 0x00000d36
399 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae
401 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf
403 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0
405 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1
407 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2
409 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3
411 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4
413 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5
415 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6
417 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7
419 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8
421 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9
423 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba
425 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb
427 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc
429 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd
431 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe
433 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf
435 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0
437 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1
439 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00
440 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001
442 #define REG_A2XX_TP0_CHICKEN 0x00000e1e
444 #define REG_A2XX_RB_BC_CONTROL 0x00000f01
445 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001
446 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006
447 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1
448 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val
)
450 return ((val
) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT
) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK
;
452 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008
453 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010
454 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020
455 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040
456 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080
457 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00
458 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8
459 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val
)
461 return ((val
) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT
) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK
;
463 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000
464 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000
465 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000
466 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000
467 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000
468 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18
469 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val
)
471 return ((val
) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT
) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK
;
473 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000
474 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000
475 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23
476 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val
)
478 return ((val
) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT
) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK
;
480 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000
481 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27
482 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val
)
484 return ((val
) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT
) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK
;
486 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000
487 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000
488 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000
490 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02
492 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26
494 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27
496 #define REG_A2XX_RB_SURFACE_INFO 0x00002000
498 #define REG_A2XX_RB_COLOR_INFO 0x00002001
499 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f
500 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0
501 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val
)
503 return ((val
) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT
) & A2XX_RB_COLOR_INFO_FORMAT__MASK
;
505 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030
506 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4
507 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val
)
509 return ((val
) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT
) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK
;
511 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040
512 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180
513 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7
514 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val
)
516 return ((val
) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT
) & A2XX_RB_COLOR_INFO_ENDIAN__MASK
;
518 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600
519 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9
520 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val
)
522 return ((val
) << A2XX_RB_COLOR_INFO_SWAP__SHIFT
) & A2XX_RB_COLOR_INFO_SWAP__MASK
;
524 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000
525 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
526 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val
)
528 return ((val
>> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT
) & A2XX_RB_COLOR_INFO_BASE__MASK
;
531 #define REG_A2XX_RB_DEPTH_INFO 0x00002002
532 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
533 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
534 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val
)
536 return ((val
) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
;
538 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
539 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
540 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val
)
542 return ((val
>> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
545 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
547 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006
549 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e
550 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
551 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
552 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
553 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val
)
555 return ((val
) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT
) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK
;
557 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
558 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
559 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val
)
561 return ((val
) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT
) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK
;
564 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f
565 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
566 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
567 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
568 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val
)
570 return ((val
) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT
) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK
;
572 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
573 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
574 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val
)
576 return ((val
) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT
) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK
;
579 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080
580 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff
581 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0
582 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val
)
584 return ((val
) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT
) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK
;
586 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000
587 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16
588 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val
)
590 return ((val
) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT
) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK
;
592 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000
594 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081
595 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
596 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
597 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
598 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
600 return ((val
) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK
;
602 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
603 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
604 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
606 return ((val
) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK
;
609 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082
610 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
611 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
612 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
613 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
615 return ((val
) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK
;
617 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
618 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
619 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
621 return ((val
) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK
;
624 #define REG_A2XX_UNKNOWN_2010 0x00002010
626 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100
628 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101
630 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102
632 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103
634 #define REG_A2XX_RB_COLOR_MASK 0x00002104
635 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001
636 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002
637 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004
638 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008
640 #define REG_A2XX_RB_BLEND_RED 0x00002105
642 #define REG_A2XX_RB_BLEND_GREEN 0x00002106
644 #define REG_A2XX_RB_BLEND_BLUE 0x00002107
646 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108
648 #define REG_A2XX_RB_FOG_COLOR 0x00002109
650 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c
651 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
652 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
653 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val
)
655 return ((val
) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
;
657 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
658 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
659 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val
)
661 return ((val
) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
;
663 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
664 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
665 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val
)
667 return ((val
) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
;
670 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d
671 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
672 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
673 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
675 return ((val
) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK
;
677 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
678 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
679 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
681 return ((val
) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
683 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
684 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
685 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
687 return ((val
) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
690 #define REG_A2XX_RB_ALPHA_REF 0x0000210e
692 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f
693 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff
694 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0
695 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val
)
697 return ((fui(val
)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT
) & A2XX_PA_CL_VPORT_XSCALE__MASK
;
700 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110
701 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff
702 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0
703 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val
)
705 return ((fui(val
)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT
) & A2XX_PA_CL_VPORT_XOFFSET__MASK
;
708 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111
709 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff
710 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0
711 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val
)
713 return ((fui(val
)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT
) & A2XX_PA_CL_VPORT_YSCALE__MASK
;
716 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112
717 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff
718 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0
719 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val
)
721 return ((fui(val
)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT
) & A2XX_PA_CL_VPORT_YOFFSET__MASK
;
724 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113
725 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff
726 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0
727 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val
)
729 return ((fui(val
)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT
) & A2XX_PA_CL_VPORT_ZSCALE__MASK
;
732 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114
733 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff
734 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0
735 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val
)
737 return ((fui(val
)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT
) & A2XX_PA_CL_VPORT_ZOFFSET__MASK
;
740 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180
741 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff
742 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0
743 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val
)
745 return ((val
) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT
) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK
;
747 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00
748 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8
749 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val
)
751 return ((val
) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT
) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK
;
753 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000
754 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000
755 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000
756 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000
757 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000
758 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20
759 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val
)
761 return ((val
) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT
) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK
;
763 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000
764 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24
765 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val
)
767 return ((val
) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT
) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK
;
769 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000
770 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27
771 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val
)
773 return ((val
) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT
) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK
;
775 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000
777 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181
778 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001
779 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002
780 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c
781 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2
782 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val
)
784 return ((val
) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT
) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK
;
786 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00
787 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8
788 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val
)
790 return ((val
) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT
) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK
;
792 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000
793 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000
794 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000
796 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182
798 #define REG_A2XX_SQ_WRAPPING_0 0x00002183
800 #define REG_A2XX_SQ_WRAPPING_1 0x00002184
802 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6
804 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
806 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200
807 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001
808 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002
809 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004
810 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008
811 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070
812 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4
813 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val
)
815 return ((val
) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT
) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK
;
817 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080
818 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700
819 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8
820 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val
)
822 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK
;
824 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800
825 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11
826 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val
)
828 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK
;
830 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000
831 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14
832 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val
)
834 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK
;
836 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000
837 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17
838 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val
)
840 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK
;
842 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000
843 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20
844 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val
)
846 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK
;
848 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000
849 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23
850 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val
)
852 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK
;
854 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000
855 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26
856 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val
)
858 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK
;
860 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000
861 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29
862 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val
)
864 return ((val
) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT
) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK
;
867 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201
868 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f
869 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0
870 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val
)
872 return ((val
) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT
) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK
;
874 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0
875 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5
876 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val
)
878 return ((val
) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT
) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK
;
880 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00
881 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8
882 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val
)
884 return ((val
) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT
) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK
;
886 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000
887 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16
888 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val
)
890 return ((val
) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT
) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK
;
892 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000
893 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21
894 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val
)
896 return ((val
) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT
) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK
;
898 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000
899 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24
900 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val
)
902 return ((val
) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT
) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK
;
904 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000
905 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000
907 #define REG_A2XX_RB_COLORCONTROL 0x00002202
908 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007
909 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0
910 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val
)
912 return ((val
) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT
) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK
;
914 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008
915 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010
916 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020
917 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040
918 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080
919 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00
920 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8
921 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val
)
923 return ((val
) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT
) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK
;
925 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000
926 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12
927 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val
)
929 return ((val
) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT
) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK
;
931 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000
932 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14
933 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val
)
935 return ((val
) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT
) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK
;
937 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000
938 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000
939 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24
940 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val
)
942 return ((val
) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT
) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK
;
944 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000
945 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26
946 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val
)
948 return ((val
) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT
) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK
;
950 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000
951 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28
952 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val
)
954 return ((val
) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT
) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK
;
956 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000
957 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30
958 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val
)
960 return ((val
) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT
) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK
;
963 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203
964 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007
965 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0
966 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val
)
968 return ((val
) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT
) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK
;
970 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038
971 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3
972 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val
)
974 return ((val
) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT
) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK
;
976 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0
977 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6
978 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val
)
980 return ((val
) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT
) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK
;
983 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204
984 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
985 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000
986 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000
987 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19
988 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val
)
990 return ((val
) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT
) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK
;
992 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000
993 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000
994 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000
995 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000
996 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000
998 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205
999 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001
1000 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002
1001 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004
1002 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018
1003 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3
1004 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val
)
1006 return ((val
) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT
) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK
;
1008 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0
1009 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5
1010 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val
)
1012 return ((val
) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT
) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK
;
1014 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700
1015 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8
1016 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val
)
1018 return ((val
) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT
) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK
;
1020 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800
1021 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000
1022 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000
1023 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000
1024 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000
1025 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000
1026 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000
1027 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000
1028 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000
1029 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000
1030 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000
1031 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000
1032 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000
1033 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000
1034 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000
1035 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000
1037 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206
1038 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001
1039 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002
1040 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004
1041 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008
1042 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010
1043 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020
1044 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100
1045 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200
1046 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400
1047 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800
1049 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207
1050 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007
1051 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0
1052 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val
)
1054 return ((val
) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT
) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK
;
1056 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038
1057 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3
1058 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val
)
1060 return ((val
) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT
) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK
;
1062 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0
1063 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6
1064 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val
)
1066 return ((val
) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT
) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK
;
1069 #define REG_A2XX_RB_MODECONTROL 0x00002208
1070 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007
1071 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0
1072 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val
)
1074 return ((val
) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT
) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK
;
1077 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209
1079 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a
1081 #define REG_A2XX_CLEAR_COLOR 0x0000220b
1082 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff
1083 #define A2XX_CLEAR_COLOR_RED__SHIFT 0
1084 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val
)
1086 return ((val
) << A2XX_CLEAR_COLOR_RED__SHIFT
) & A2XX_CLEAR_COLOR_RED__MASK
;
1088 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00
1089 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8
1090 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val
)
1092 return ((val
) << A2XX_CLEAR_COLOR_GREEN__SHIFT
) & A2XX_CLEAR_COLOR_GREEN__MASK
;
1094 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000
1095 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16
1096 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val
)
1098 return ((val
) << A2XX_CLEAR_COLOR_BLUE__SHIFT
) & A2XX_CLEAR_COLOR_BLUE__MASK
;
1100 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000
1101 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24
1102 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val
)
1104 return ((val
) << A2XX_CLEAR_COLOR_ALPHA__SHIFT
) & A2XX_CLEAR_COLOR_ALPHA__MASK
;
1107 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210
1109 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280
1110 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff
1111 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0
1112 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val
)
1114 return ((((uint32_t)(val
* 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT
) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK
;
1116 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000
1117 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16
1118 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val
)
1120 return ((((uint32_t)(val
* 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT
) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK
;
1123 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281
1124 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
1125 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0
1126 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val
)
1128 return ((((uint32_t)(val
* 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT
) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK
;
1130 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000
1131 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16
1132 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val
)
1134 return ((((uint32_t)(val
* 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT
) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK
;
1137 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282
1138 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff
1139 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0
1140 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val
)
1142 return ((((uint32_t)(val
* 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT
) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK
;
1145 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283
1146 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff
1147 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0
1148 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val
)
1150 return ((val
) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT
) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK
;
1152 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000
1153 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16
1154 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val
)
1156 return ((val
) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT
) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK
;
1158 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000
1159 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28
1160 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val
)
1162 return ((val
) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT
) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK
;
1164 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000
1165 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29
1166 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val
)
1168 return ((val
) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT
) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK
;
1171 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293
1173 #define REG_A2XX_VGT_ENHANCE 0x00002294
1175 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300
1176 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff
1177 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0
1178 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val
)
1180 return ((val
) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT
) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK
;
1182 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100
1183 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200
1184 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400
1186 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301
1188 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302
1189 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001
1190 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0
1191 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val
)
1193 return ((val
) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT
) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK
;
1195 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006
1196 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1
1197 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val
)
1199 return ((val
) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT
) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK
;
1201 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380
1202 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7
1203 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val
)
1205 return ((val
) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT
) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK
;
1208 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303
1209 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff
1210 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0
1211 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val
)
1213 return ((fui(val
)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT
) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK
;
1216 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304
1217 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff
1218 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0
1219 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val
)
1221 return ((fui(val
)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT
) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK
;
1224 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305
1225 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff
1226 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0
1227 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val
)
1229 return ((fui(val
)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT
) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK
;
1232 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306
1233 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff
1234 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0
1235 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val
)
1237 return ((fui(val
)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT
) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK
;
1240 #define REG_A2XX_SQ_VS_CONST 0x00002307
1241 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff
1242 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0
1243 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val
)
1245 return ((val
) << A2XX_SQ_VS_CONST_BASE__SHIFT
) & A2XX_SQ_VS_CONST_BASE__MASK
;
1247 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000
1248 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12
1249 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val
)
1251 return ((val
) << A2XX_SQ_VS_CONST_SIZE__SHIFT
) & A2XX_SQ_VS_CONST_SIZE__MASK
;
1254 #define REG_A2XX_SQ_PS_CONST 0x00002308
1255 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff
1256 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0
1257 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val
)
1259 return ((val
) << A2XX_SQ_PS_CONST_BASE__SHIFT
) & A2XX_SQ_PS_CONST_BASE__MASK
;
1261 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000
1262 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12
1263 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val
)
1265 return ((val
) << A2XX_SQ_PS_CONST_SIZE__SHIFT
) & A2XX_SQ_PS_CONST_SIZE__MASK
;
1268 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309
1270 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a
1272 #define REG_A2XX_PA_SC_AA_MASK 0x00002312
1274 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316
1276 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317
1278 #define REG_A2XX_RB_COPY_CONTROL 0x00002318
1279 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007
1280 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0
1281 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val
)
1283 return ((val
) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT
) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK
;
1285 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008
1286 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0
1287 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4
1288 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val
)
1290 return ((val
) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT
) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK
;
1293 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319
1295 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a
1296 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff
1297 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0
1298 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val
)
1300 return ((val
>> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT
) & A2XX_RB_COPY_DEST_PITCH__MASK
;
1303 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b
1304 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007
1305 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0
1306 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val
)
1308 return ((val
) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT
) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK
;
1310 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008
1311 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0
1312 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4
1313 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val
)
1315 return ((val
) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK
;
1317 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1318 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1319 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val
)
1321 return ((val
) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT
) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK
;
1323 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1324 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1325 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val
)
1327 return ((val
) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT
) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK
;
1329 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000
1330 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12
1331 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val
)
1333 return ((val
) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT
) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK
;
1335 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000
1336 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000
1337 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000
1338 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000
1340 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c
1341 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff
1342 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0
1343 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val
)
1345 return ((val
) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT
) & A2XX_RB_COPY_DEST_OFFSET_X__MASK
;
1347 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000
1348 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13
1349 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val
)
1351 return ((val
) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT
) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK
;
1354 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d
1356 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324
1358 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326
1360 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340
1362 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357
1364 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360
1366 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380
1368 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383
1370 #define REG_A2XX_SQ_CONSTANT_0 0x00004000
1372 #define REG_A2XX_SQ_FETCH_0 0x00004800
1374 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900
1376 #define REG_A2XX_SQ_CF_LOOP 0x00004908
1378 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29
1380 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a
1382 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
1384 #define REG_A2XX_SQ_TEX_0 0x00000000
1385 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00
1386 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10
1387 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val
)
1389 return ((val
) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT
) & A2XX_SQ_TEX_0_CLAMP_X__MASK
;
1391 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000
1392 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13
1393 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val
)
1395 return ((val
) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT
) & A2XX_SQ_TEX_0_CLAMP_Y__MASK
;
1397 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000
1398 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16
1399 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val
)
1401 return ((val
) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT
) & A2XX_SQ_TEX_0_CLAMP_Z__MASK
;
1403 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000
1404 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22
1405 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val
)
1407 return ((val
>> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT
) & A2XX_SQ_TEX_0_PITCH__MASK
;
1410 #define REG_A2XX_SQ_TEX_1 0x00000001
1412 #define REG_A2XX_SQ_TEX_2 0x00000002
1413 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff
1414 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0
1415 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val
)
1417 return ((val
) << A2XX_SQ_TEX_2_WIDTH__SHIFT
) & A2XX_SQ_TEX_2_WIDTH__MASK
;
1419 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000
1420 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13
1421 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val
)
1423 return ((val
) << A2XX_SQ_TEX_2_HEIGHT__SHIFT
) & A2XX_SQ_TEX_2_HEIGHT__MASK
;
1426 #define REG_A2XX_SQ_TEX_3 0x00000003
1427 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e
1428 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1
1429 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val
)
1431 return ((val
) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT
) & A2XX_SQ_TEX_3_SWIZ_X__MASK
;
1433 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070
1434 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4
1435 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val
)
1437 return ((val
) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT
) & A2XX_SQ_TEX_3_SWIZ_Y__MASK
;
1439 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380
1440 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7
1441 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val
)
1443 return ((val
) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT
) & A2XX_SQ_TEX_3_SWIZ_Z__MASK
;
1445 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00
1446 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10
1447 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val
)
1449 return ((val
) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT
) & A2XX_SQ_TEX_3_SWIZ_W__MASK
;
1451 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000
1452 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19
1453 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val
)
1455 return ((val
) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT
) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK
;
1457 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000
1458 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21
1459 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val
)
1461 return ((val
) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT
) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK
;
1465 #endif /* A2XX_XML */