src/gallium/drivers/freedreno/a2xx/fd2_draw.c

   1 /*
   2  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_prim.h"
  31
  32 #include "freedreno_state.h"
  33 #include "freedreno_resource.h"
  34
  35 #include "fd2_draw.h"
  36 #include "fd2_context.h"
  37 #include "fd2_emit.h"
  38 #include "fd2_program.h"
  39 #include "fd2_util.h"
  40 #include "fd2_zsa.h"
  41
  42
  43 static void
  44 emit_cacheflush(struct fd_ringbuffer *ring)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < 12; i++) {
  49                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
  50                 OUT_RING(ring, CACHE_FLUSH);
  51         }
  52 }
  53
  54 static void
  55 emit_vertexbufs(struct fd_context *ctx)
  56 {
  57         struct fd_vertex_stateobj *vtx = ctx->vtx.vtx;
  58         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vtx.vertexbuf;
  59         struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  60         unsigned i;
  61
  62         if (!vtx->num_elements)
  63                 return;
  64
  65         for (i = 0; i < vtx->num_elements; i++) {
  66                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  67                 struct pipe_vertex_buffer *vb =
  68                                 &vertexbuf->vb[elem->vertex_buffer_index];
  69                 bufs[i].offset = vb->buffer_offset;
  70                 bufs[i].size = fd_bo_size(fd_resource(vb->buffer.resource)->bo);
  71                 bufs[i].prsc = vb->buffer.resource;
  72         }
  73
  74         // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
  75         // CONST(20,0) (or CONST(26,0) in soliv_vp)
  76
  77         fd2_emit_vertex_bufs(ctx->batch->draw, 0x78, bufs, vtx->num_elements);
  78         fd2_emit_vertex_bufs(ctx->batch->binning, 0x78, bufs, vtx->num_elements);
  79 }
  80
  81 static void
  82 draw_impl(struct fd_context *ctx, const struct pipe_draw_info *info,
  83                    struct fd_ringbuffer *ring, unsigned index_offset, bool binning)
  84 {
  85         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  86         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  87         OUT_RING(ring, info->index_size ? 0 : info->start);
  88
  89         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
  90         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
  91
  92         if (is_a20x(ctx->screen)) {
  93                 /* wait for DMA to finish and
  94                  * dummy draw one triangle with indexes 0,0,0.
  95                  * with PRE_FETCH_CULL_ENABLE | GRP_CULL_ENABLE.
  96                  *
  97                  * this workaround is for a HW bug related to DMA alignment:
  98                  * it is necessary for indexed draws and possibly also
  99                  * draws that read binning data
 100                  */
 101                 OUT_PKT3(ring, CP_WAIT_REG_EQ, 4);
 102                 OUT_RING(ring, 0x000005d0); /* RBBM_STATUS */
 103                 OUT_RING(ring, 0x00000000);
 104                 OUT_RING(ring, 0x00001000); /* bit: 12: VGT_BUSY_NO_DMA */
 105                 OUT_RING(ring, 0x00000001);
 106
 107                 OUT_PKT3(ring, CP_DRAW_INDX_BIN, 6);
 108                 OUT_RING(ring, 0x00000000);
 109                 OUT_RING(ring, 0x0003c004);
 110                 OUT_RING(ring, 0x00000000);
 111                 OUT_RING(ring, 0x00000003);
 112                 OUT_RELOC(ring, fd_resource(fd2_context(ctx)->solid_vertexbuf)->bo, 0x80, 0, 0);
 113                 OUT_RING(ring, 0x00000006);
 114         } else {
 115                 OUT_WFI (ring);
 116
 117                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 118                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 119                 OUT_RING(ring, info->max_index);        /* VGT_MAX_VTX_INDX */
 120                 OUT_RING(ring, info->min_index);        /* VGT_MIN_VTX_INDX */
 121         }
 122
 123         /* binning shader will take offset from C64 */
 124         if (binning && is_a20x(ctx->screen)) {
 125                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 126                 OUT_RING(ring, 0x00000180);
 127                 OUT_RING(ring, fui(ctx->batch->num_vertices));
 128                 OUT_RING(ring, fui(0.0f));
 129                 OUT_RING(ring, fui(0.0f));
 130                 OUT_RING(ring, fui(0.0f));
 131         }
 132
 133         enum pc_di_vis_cull_mode vismode = USE_VISIBILITY;
 134         if (binning || info->mode == PIPE_PRIM_POINTS)
 135                 vismode = IGNORE_VISIBILITY;
 136
 137         fd_draw_emit(ctx->batch, ring, ctx->primtypes[info->mode],
 138                                  vismode, info, index_offset);
 139
 140         if (is_a20x(ctx->screen)) {
 141                 /* not sure why this is required, but it fixes some hangs */
 142                 OUT_WFI(ring);
 143         } else {
 144                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 145                 OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
 146                 OUT_RING(ring, 0x00000000);
 147         }
 148
 149         emit_cacheflush(ring);
 150 }
 151
 152
 153 static bool
 154 fd2_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *pinfo,
 155                          unsigned index_offset)
 156 {
 157         if (!ctx->prog.fp || !ctx->prog.vp)
 158                 return false;
 159
 160         if (ctx->dirty & FD_DIRTY_VTXBUF)
 161                 emit_vertexbufs(ctx);
 162
 163         if (fd_binning_enabled)
 164                 fd2_emit_state_binning(ctx, ctx->dirty);
 165
 166         fd2_emit_state(ctx, ctx->dirty);
 167
 168         /* a2xx can draw only 65535 vertices at once
 169          * on a22x the field in the draw command is 32bits but seems limited too
 170          * using a limit of 32k because it fixes an unexplained hang
 171          * 32766 works for all primitives (multiple of 2 and 3)
 172          */
 173         if (pinfo->count > 32766) {
 174                 static const uint16_t step_tbl[PIPE_PRIM_MAX] = {
 175                         [0 ... PIPE_PRIM_MAX - 1]  = 32766,
 176                         [PIPE_PRIM_LINE_STRIP]     = 32765,
 177                         [PIPE_PRIM_TRIANGLE_STRIP] = 32764,
 178
 179                         /* needs more work */
 180                         [PIPE_PRIM_TRIANGLE_FAN]   = 0,
 181                         [PIPE_PRIM_LINE_LOOP]      = 0,
 182                 };
 183
 184                 struct pipe_draw_info info = *pinfo;
 185                 unsigned count = info.count;
 186                 unsigned step = step_tbl[info.mode];
 187                 unsigned num_vertices = ctx->batch->num_vertices;
 188
 189                 if (!step)
 190                         return false;
 191
 192                 for (; count + step > 32766; count -= step) {
 193                         info.count = MIN2(count, 32766);
 194                         draw_impl(ctx, &info, ctx->batch->draw, index_offset, false);
 195                         draw_impl(ctx, &info, ctx->batch->binning, index_offset, true);
 196                         info.start += step;
 197                         ctx->batch->num_vertices += step;
 198                 }
 199                 /* changing this value is a hack, restore it */
 200                 ctx->batch->num_vertices = num_vertices;
 201         } else {
 202                 draw_impl(ctx, pinfo, ctx->batch->draw, index_offset, false);
 203                 draw_impl(ctx, pinfo, ctx->batch->binning, index_offset, true);
 204         }
 205
 206         fd_context_all_clean(ctx);
 207
 208         return true;
 209 }
 210
 211
 212 static bool
 213 fd2_clear(struct fd_context *ctx, unsigned buffers,
 214                 const union pipe_color_union *color, double depth, unsigned stencil)
 215 {
 216         struct fd2_context *fd2_ctx = fd2_context(ctx);
 217         struct fd_ringbuffer *ring = ctx->batch->draw;
 218         struct pipe_framebuffer_state *fb = &ctx->batch->framebuffer;
 219         uint32_t reg, colr = 0;
 220
 221         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
 222                 colr = pack_rgba(PIPE_FORMAT_R8G8B8A8_UNORM, color->f);
 223
 224         /* emit generic state now: */
 225         fd2_emit_state(ctx, ctx->dirty &
 226                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
 227                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
 228
 229         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 230                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 36 },
 231                 }, 1);
 232
 233         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 234         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 235         OUT_RING(ring, 0);
 236
 237         if (!is_a20x(ctx->screen)) {
 238                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 239                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 240                 OUT_RING(ring, 0x0000028f);
 241         }
 242
 243         fd2_program_emit(ctx, ring, &ctx->solid_prog);
 244
 245         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 246         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 247
 248         if (is_a20x(ctx->screen)) {
 249                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 250                 OUT_RING(ring, 0x00000480);
 251                 OUT_RING(ring, color->ui[0]);
 252                 OUT_RING(ring, color->ui[1]);
 253                 OUT_RING(ring, color->ui[2]);
 254                 OUT_RING(ring, color->ui[3]);
 255         } else {
 256                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 257                 OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
 258                 OUT_RING(ring, colr);
 259         }
 260
 261         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 262         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 263         OUT_RING(ring, 0x00000084);
 264
 265         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 266         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 267         reg = 0;
 268         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 269                 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
 270                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 271                 case DEPTHX_24_8:
 272                         if (buffers & PIPE_CLEAR_DEPTH)
 273                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
 274                         if (buffers & PIPE_CLEAR_STENCIL)
 275                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
 276                         break;
 277                 case DEPTHX_16:
 278                         if (buffers & PIPE_CLEAR_DEPTH)
 279                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
 280                         break;
 281                 default:
 282                         debug_assert(0);
 283                         break;
 284                 }
 285         }
 286         OUT_RING(ring, reg);
 287
 288         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 289         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
 290         reg = 0;
 291         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 292                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 293                 case DEPTHX_24_8:
 294                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
 295                                 (stencil & 0xff);
 296                         break;
 297                 case DEPTHX_16:
 298                         reg = (uint32_t)(0xffffffff * depth);
 299                         break;
 300                 default:
 301                         debug_assert(0);
 302                         break;
 303                 }
 304         }
 305         OUT_RING(ring, reg);
 306
 307         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 308         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 309         reg = 0;
 310         if (buffers & PIPE_CLEAR_DEPTH) {
 311                 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
 312                                 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
 313                                 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
 314                                 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
 315         }
 316         if (buffers & PIPE_CLEAR_STENCIL) {
 317                 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
 318                                 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
 319                                 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
 320         }
 321         OUT_RING(ring, reg);
 322
 323         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 324         OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 325         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 326         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 327
 328         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 329         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 330         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
 331                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 332                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 333                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 334                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 335
 336         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 337         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 338         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
 339         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 340                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 341                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 342
 343         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 344         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 345         OUT_RING(ring, 0x0000ffff);
 346
 347         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 348         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 349         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
 350         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
 351                         fb->height));
 352
 353         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 354         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 355         if (buffers & PIPE_CLEAR_COLOR) {
 356                 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 357                                 A2XX_RB_COLOR_MASK_WRITE_GREEN |
 358                                 A2XX_RB_COLOR_MASK_WRITE_BLUE |
 359                                 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 360         } else {
 361                 OUT_RING(ring, 0x0);
 362         }
 363
 364         if (!is_a20x(ctx->screen)) {
 365                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 366                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 367                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 368                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 369         }
 370
 371         fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 372                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 373
 374         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 375         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 376         OUT_RING(ring, 0x00000000);
 377
 378         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 379         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 380         OUT_RING(ring, 0x00000000);
 381
 382         if (!is_a20x(ctx->screen)) {
 383                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 384                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 385                 OUT_RING(ring, 0x0000003b);
 386         }
 387
 388         ctx->dirty |= FD_DIRTY_ZSA |
 389                         FD_DIRTY_VIEWPORT |
 390                         FD_DIRTY_RASTERIZER |
 391                         FD_DIRTY_SAMPLE_MASK |
 392                         FD_DIRTY_PROG |
 393                         FD_DIRTY_CONST |
 394                         FD_DIRTY_BLEND |
 395                         FD_DIRTY_FRAMEBUFFER;
 396
 397         ctx->dirty_shader[PIPE_SHADER_VERTEX]   |= FD_DIRTY_SHADER_PROG;
 398         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST;
 399
 400         return true;
 401 }
 402
 403 void
 404 fd2_draw_init(struct pipe_context *pctx)
 405 {
 406         struct fd_context *ctx = fd_context(pctx);
 407         ctx->draw_vbo = fd2_draw_vbo;
 408         ctx->clear = fd2_clear;
 409 }