src/gallium/drivers/freedreno/a2xx/fd2_draw.c

   1 /*
   2  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_prim.h"
  31
  32 #include "freedreno_state.h"
  33 #include "freedreno_resource.h"
  34
  35 #include "fd2_draw.h"
  36 #include "fd2_context.h"
  37 #include "fd2_emit.h"
  38 #include "fd2_program.h"
  39 #include "fd2_util.h"
  40 #include "fd2_zsa.h"
  41
  42
  43 static void
  44 emit_cacheflush(struct fd_ringbuffer *ring)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < 12; i++) {
  49                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
  50                 OUT_RING(ring, CACHE_FLUSH);
  51         }
  52 }
  53
  54 static void
  55 emit_vertexbufs(struct fd_context *ctx)
  56 {
  57         struct fd_vertex_stateobj *vtx = ctx->vtx.vtx;
  58         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vtx.vertexbuf;
  59         struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  60         unsigned i;
  61
  62         if (!vtx->num_elements)
  63                 return;
  64
  65         for (i = 0; i < vtx->num_elements; i++) {
  66                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  67                 struct pipe_vertex_buffer *vb =
  68                                 &vertexbuf->vb[elem->vertex_buffer_index];
  69                 bufs[i].offset = vb->buffer_offset;
  70                 bufs[i].size = fd_bo_size(fd_resource(vb->buffer.resource)->bo);
  71                 bufs[i].prsc = vb->buffer.resource;
  72         }
  73
  74         // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
  75         // CONST(20,0) (or CONST(26,0) in soliv_vp)
  76
  77         fd2_emit_vertex_bufs(ctx->batch->draw, 0x78, bufs, vtx->num_elements);
  78 }
  79
  80 static bool
  81 fd2_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
  82              unsigned index_offset)
  83 {
  84         struct fd_ringbuffer *ring = ctx->batch->draw;
  85
  86         if (ctx->dirty & FD_DIRTY_VTXBUF)
  87                 emit_vertexbufs(ctx);
  88
  89         fd2_emit_state(ctx, ctx->dirty);
  90
  91         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  92         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  93         OUT_RING(ring, info->start);
  94
  95         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  96         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
  97         OUT_RING(ring, 0x0000003b);
  98
  99         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 100         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 101
 102         if (!is_a20x(ctx->screen)) {
 103                 OUT_WFI (ring);
 104
 105                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 106                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 107                 OUT_RING(ring, info->max_index);        /* VGT_MAX_VTX_INDX */
 108                 OUT_RING(ring, info->min_index);        /* VGT_MIN_VTX_INDX */
 109         }
 110
 111         fd_draw_emit(ctx->batch, ring, ctx->primtypes[info->mode],
 112                                  IGNORE_VISIBILITY, info, index_offset);
 113
 114         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 115         OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
 116         OUT_RING(ring, 0x00000000);
 117
 118         emit_cacheflush(ring);
 119
 120         fd_context_all_clean(ctx);
 121
 122         return true;
 123 }
 124
 125
 126 static bool
 127 fd2_clear(struct fd_context *ctx, unsigned buffers,
 128                 const union pipe_color_union *color, double depth, unsigned stencil)
 129 {
 130         struct fd2_context *fd2_ctx = fd2_context(ctx);
 131         struct fd_ringbuffer *ring = ctx->batch->draw;
 132         struct pipe_framebuffer_state *fb = &ctx->batch->framebuffer;
 133         uint32_t reg, colr = 0;
 134
 135         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
 136                 colr = pack_rgba(PIPE_FORMAT_R8G8B8A8_UNORM, color->f);
 137
 138         /* emit generic state now: */
 139         fd2_emit_state(ctx, ctx->dirty &
 140                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
 141                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
 142
 143         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 144                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 145                 }, 1);
 146
 147         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 148         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 149         OUT_RING(ring, 0);
 150
 151         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 152         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 153         OUT_RING(ring, 0x0000028f);
 154
 155         fd2_program_emit(ring, &ctx->solid_prog);
 156
 157         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 158         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 159
 160         if (is_a20x(ctx->screen)) {
 161                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 162                 OUT_RING(ring, 0x00000480);
 163                 OUT_RING(ring, color->ui[0]);
 164                 OUT_RING(ring, color->ui[1]);
 165                 OUT_RING(ring, color->ui[2]);
 166                 OUT_RING(ring, color->ui[3]);
 167         } else {
 168                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 169                 OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
 170                 OUT_RING(ring, colr);
 171         }
 172
 173         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 174         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 175         OUT_RING(ring, 0x00000084);
 176
 177         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 178         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 179         reg = 0;
 180         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 181                 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
 182                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 183                 case DEPTHX_24_8:
 184                         if (buffers & PIPE_CLEAR_DEPTH)
 185                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
 186                         if (buffers & PIPE_CLEAR_STENCIL)
 187                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
 188                         break;
 189                 case DEPTHX_16:
 190                         if (buffers & PIPE_CLEAR_DEPTH)
 191                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
 192                         break;
 193                 default:
 194                         debug_assert(0);
 195                         break;
 196                 }
 197         }
 198         OUT_RING(ring, reg);
 199
 200         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 201         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
 202         reg = 0;
 203         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 204                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 205                 case DEPTHX_24_8:
 206                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
 207                                 (stencil & 0xff);
 208                         break;
 209                 case DEPTHX_16:
 210                         reg = (uint32_t)(0xffffffff * depth);
 211                         break;
 212                 default:
 213                         debug_assert(0);
 214                         break;
 215                 }
 216         }
 217         OUT_RING(ring, reg);
 218
 219         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 220         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 221         reg = 0;
 222         if (buffers & PIPE_CLEAR_DEPTH) {
 223                 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
 224                                 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
 225                                 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
 226                                 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
 227         }
 228         if (buffers & PIPE_CLEAR_STENCIL) {
 229                 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
 230                                 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
 231                                 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
 232         }
 233         OUT_RING(ring, reg);
 234
 235         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 236         OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 237         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 238         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 239
 240         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 241         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 242         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
 243                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 244                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 245                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 246                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 247
 248         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 249         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 250         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
 251         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 252                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 253                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 254
 255         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 256         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 257         OUT_RING(ring, 0x0000ffff);
 258
 259         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 260         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 261         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
 262         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
 263                         fb->height));
 264
 265         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 266         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 267         if (buffers & PIPE_CLEAR_COLOR) {
 268                 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 269                                 A2XX_RB_COLOR_MASK_WRITE_GREEN |
 270                                 A2XX_RB_COLOR_MASK_WRITE_BLUE |
 271                                 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 272         } else {
 273                 OUT_RING(ring, 0x0);
 274         }
 275
 276         if (!is_a20x(ctx->screen)) {
 277                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 278                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 279                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 280                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 281         }
 282
 283         fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 284                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 285
 286         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 287         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 288         OUT_RING(ring, 0x00000000);
 289
 290         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 291         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 292         OUT_RING(ring, 0x00000000);
 293
 294         ctx->dirty |= FD_DIRTY_ZSA |
 295                         FD_DIRTY_VIEWPORT |
 296                         FD_DIRTY_RASTERIZER |
 297                         FD_DIRTY_SAMPLE_MASK |
 298                         FD_DIRTY_PROG |
 299                         FD_DIRTY_CONST |
 300                         FD_DIRTY_BLEND |
 301                         FD_DIRTY_FRAMEBUFFER;
 302
 303         ctx->dirty_shader[PIPE_SHADER_VERTEX]   |= FD_DIRTY_SHADER_PROG;
 304         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST;
 305
 306         return true;
 307 }
 308
 309 void
 310 fd2_draw_init(struct pipe_context *pctx)
 311 {
 312         struct fd_context *ctx = fd_context(pctx);
 313         ctx->draw_vbo = fd2_draw_vbo;
 314         ctx->clear = fd2_clear;
 315 }