src/gallium/drivers/freedreno/a2xx/fd2_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd2_draw.h"
  38 #include "fd2_context.h"
  39 #include "fd2_emit.h"
  40 #include "fd2_program.h"
  41 #include "fd2_util.h"
  42 #include "fd2_zsa.h"
  43
  44
  45 static void
  46 emit_cacheflush(struct fd_ringbuffer *ring)
  47 {
  48         unsigned i;
  49
  50         for (i = 0; i < 12; i++) {
  51                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
  52                 OUT_RING(ring, CACHE_FLUSH);
  53         }
  54 }
  55
  56 static void
  57 emit_vertexbufs(struct fd_context *ctx)
  58 {
  59         struct fd_vertex_stateobj *vtx = ctx->vtx.vtx;
  60         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vtx.vertexbuf;
  61         struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  62         unsigned i;
  63
  64         if (!vtx->num_elements)
  65                 return;
  66
  67         for (i = 0; i < vtx->num_elements; i++) {
  68                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  69                 struct pipe_vertex_buffer *vb =
  70                                 &vertexbuf->vb[elem->vertex_buffer_index];
  71                 bufs[i].offset = vb->buffer_offset;
  72                 bufs[i].size = fd_bo_size(fd_resource(vb->buffer)->bo);
  73                 bufs[i].prsc = vb->buffer;
  74         }
  75
  76         // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
  77         // CONST(20,0) (or CONST(26,0) in soliv_vp)
  78
  79         fd2_emit_vertex_bufs(ctx->ring, 0x78, bufs, vtx->num_elements);
  80 }
  81
  82 static void
  83 fd2_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
  84 {
  85         struct fd_ringbuffer *ring = ctx->ring;
  86
  87         if (ctx->dirty & FD_DIRTY_VTXBUF)
  88                 emit_vertexbufs(ctx);
  89
  90         fd2_emit_state(ctx, ctx->dirty);
  91
  92         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  93         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  94         OUT_RING(ring, info->start);
  95
  96         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  97         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
  98         OUT_RING(ring, 0x0000003b);
  99
 100         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 101         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 102
 103         OUT_WFI (ring);
 104
 105         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 106         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 107         OUT_RING(ring, info->max_index);        /* VGT_MAX_VTX_INDX */
 108         OUT_RING(ring, info->min_index);        /* VGT_MIN_VTX_INDX */
 109
 110         fd_draw_emit(ctx, ring, ctx->primtypes[info->mode],
 111                                  IGNORE_VISIBILITY, info);
 112
 113         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 114         OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
 115         OUT_RING(ring, 0x00000000);
 116
 117         emit_cacheflush(ring);
 118 }
 119
 120
 121 static void
 122 fd2_clear(struct fd_context *ctx, unsigned buffers,
 123                 const union pipe_color_union *color, double depth, unsigned stencil)
 124 {
 125         struct fd2_context *fd2_ctx = fd2_context(ctx);
 126         struct fd_ringbuffer *ring = ctx->ring;
 127         struct pipe_framebuffer_state *fb = &ctx->framebuffer;
 128         uint32_t reg, colr = 0;
 129
 130         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
 131                 colr  = pack_rgba(fb->cbufs[0]->format, color->f);
 132
 133         /* emit generic state now: */
 134         fd2_emit_state(ctx, ctx->dirty &
 135                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
 136                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
 137
 138         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 139                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 140                 }, 1);
 141
 142         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 143         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 144         OUT_RING(ring, 0);
 145
 146         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 147         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 148         OUT_RING(ring, 0x0000028f);
 149
 150         fd2_program_emit(ring, &ctx->solid_prog);
 151
 152         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 153         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 154
 155         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 156         OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
 157         OUT_RING(ring, colr);
 158
 159         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 160         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 161         OUT_RING(ring, 0x00000084);
 162
 163         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 164         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 165         reg = 0;
 166         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 167                 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
 168                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 169                 case DEPTHX_24_8:
 170                         if (buffers & PIPE_CLEAR_DEPTH)
 171                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
 172                         if (buffers & PIPE_CLEAR_STENCIL)
 173                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
 174                         break;
 175                 case DEPTHX_16:
 176                         if (buffers & PIPE_CLEAR_DEPTH)
 177                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
 178                         break;
 179                 default:
 180                         debug_assert(0);
 181                         break;
 182                 }
 183         }
 184         OUT_RING(ring, reg);
 185
 186         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 187         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
 188         reg = 0;
 189         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 190                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 191                 case DEPTHX_24_8:
 192                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
 193                                 (stencil & 0xff);
 194                         break;
 195                 case DEPTHX_16:
 196                         reg = (uint32_t)(0xffffffff * depth);
 197                         break;
 198                 default:
 199                         debug_assert(0);
 200                         break;
 201                 }
 202         }
 203         OUT_RING(ring, reg);
 204
 205         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 206         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 207         reg = 0;
 208         if (buffers & PIPE_CLEAR_DEPTH) {
 209                 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
 210                                 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
 211                                 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
 212                                 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
 213         }
 214         if (buffers & PIPE_CLEAR_STENCIL) {
 215                 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
 216                                 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
 217                                 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
 218         }
 219         OUT_RING(ring, reg);
 220
 221         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 222         OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 223         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 224         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 225
 226         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 227         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 228         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
 229                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 230                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 231                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 232                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 233
 234         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 235         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 236         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
 237         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 238                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 239                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 240
 241         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 242         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 243         OUT_RING(ring, 0x0000ffff);
 244
 245         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 246         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 247         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
 248         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
 249                         fb->height));
 250
 251         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 252         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 253         if (buffers & PIPE_CLEAR_COLOR) {
 254                 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 255                                 A2XX_RB_COLOR_MASK_WRITE_GREEN |
 256                                 A2XX_RB_COLOR_MASK_WRITE_BLUE |
 257                                 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 258         } else {
 259                 OUT_RING(ring, 0x0);
 260         }
 261
 262         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 263         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 264         OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 265         OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 266
 267         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 268                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 269
 270         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 271         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 272         OUT_RING(ring, 0x00000000);
 273
 274         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 275         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 276         OUT_RING(ring, 0x00000000);
 277 }
 278
 279 void
 280 fd2_draw_init(struct pipe_context *pctx)
 281 {
 282         struct fd_context *ctx = fd_context(pctx);
 283         ctx->draw_vbo = fd2_draw_vbo;
 284         ctx->clear = fd2_clear;
 285 }