src/gallium/drivers/freedreno/a2xx/fd2_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd2_draw.h"
  38 #include "fd2_context.h"
  39 #include "fd2_emit.h"
  40 #include "fd2_program.h"
  41 #include "fd2_util.h"
  42 #include "fd2_zsa.h"
  43
  44
  45 static void
  46 emit_cacheflush(struct fd_ringbuffer *ring)
  47 {
  48         unsigned i;
  49
  50         for (i = 0; i < 12; i++) {
  51                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
  52                 OUT_RING(ring, CACHE_FLUSH);
  53         }
  54 }
  55
  56 static void
  57 emit_vertexbufs(struct fd_context *ctx)
  58 {
  59         struct fd_vertex_stateobj *vtx = ctx->vtx.vtx;
  60         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vtx.vertexbuf;
  61         struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  62         unsigned i;
  63
  64         if (!vtx->num_elements)
  65                 return;
  66
  67         for (i = 0; i < vtx->num_elements; i++) {
  68                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  69                 struct pipe_vertex_buffer *vb =
  70                                 &vertexbuf->vb[elem->vertex_buffer_index];
  71                 bufs[i].offset = vb->buffer_offset;
  72                 bufs[i].size = fd_bo_size(fd_resource(vb->buffer.resource)->bo);
  73                 bufs[i].prsc = vb->buffer.resource;
  74         }
  75
  76         // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
  77         // CONST(20,0) (or CONST(26,0) in soliv_vp)
  78
  79         fd2_emit_vertex_bufs(ctx->batch->draw, 0x78, bufs, vtx->num_elements);
  80 }
  81
  82 static bool
  83 fd2_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
  84              unsigned index_offset)
  85 {
  86         struct fd_ringbuffer *ring = ctx->batch->draw;
  87
  88         if (ctx->dirty & FD_DIRTY_VTXBUF)
  89                 emit_vertexbufs(ctx);
  90
  91         fd2_emit_state(ctx, ctx->dirty);
  92
  93         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  94         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  95         OUT_RING(ring, info->start);
  96
  97         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  98         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
  99         OUT_RING(ring, 0x0000003b);
 100
 101         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 102         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 103
 104         if (!is_a20x(ctx->screen)) {
 105                 OUT_WFI (ring);
 106
 107                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 108                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 109                 OUT_RING(ring, info->max_index);        /* VGT_MAX_VTX_INDX */
 110                 OUT_RING(ring, info->min_index);        /* VGT_MIN_VTX_INDX */
 111         }
 112
 113         fd_draw_emit(ctx->batch, ring, ctx->primtypes[info->mode],
 114                                  IGNORE_VISIBILITY, info, index_offset);
 115
 116         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 117         OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
 118         OUT_RING(ring, 0x00000000);
 119
 120         emit_cacheflush(ring);
 121
 122         fd_context_all_clean(ctx);
 123
 124         return true;
 125 }
 126
 127
 128 static bool
 129 fd2_clear(struct fd_context *ctx, unsigned buffers,
 130                 const union pipe_color_union *color, double depth, unsigned stencil)
 131 {
 132         struct fd2_context *fd2_ctx = fd2_context(ctx);
 133         struct fd_ringbuffer *ring = ctx->batch->draw;
 134         struct pipe_framebuffer_state *fb = &ctx->batch->framebuffer;
 135         uint32_t reg, colr = 0;
 136
 137         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
 138                 colr  = pack_rgba(fb->cbufs[0]->format, color->f);
 139
 140         /* emit generic state now: */
 141         fd2_emit_state(ctx, ctx->dirty &
 142                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
 143                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
 144
 145         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 146                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 147                 }, 1);
 148
 149         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 150         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 151         OUT_RING(ring, 0);
 152
 153         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 154         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 155         OUT_RING(ring, 0x0000028f);
 156
 157         fd2_program_emit(ring, &ctx->solid_prog);
 158
 159         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 160         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 161
 162         if (is_a20x(ctx->screen)) {
 163                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 164                 OUT_RING(ring, 0x00000480);
 165                 OUT_RING(ring, color->ui[0]);
 166                 OUT_RING(ring, color->ui[1]);
 167                 OUT_RING(ring, color->ui[2]);
 168                 OUT_RING(ring, color->ui[3]);
 169         } else {
 170                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 171                 OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
 172                 OUT_RING(ring, colr);
 173         }
 174
 175         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 176         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 177         OUT_RING(ring, 0x00000084);
 178
 179         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 180         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 181         reg = 0;
 182         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 183                 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
 184                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 185                 case DEPTHX_24_8:
 186                         if (buffers & PIPE_CLEAR_DEPTH)
 187                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
 188                         if (buffers & PIPE_CLEAR_STENCIL)
 189                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
 190                         break;
 191                 case DEPTHX_16:
 192                         if (buffers & PIPE_CLEAR_DEPTH)
 193                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
 194                         break;
 195                 default:
 196                         debug_assert(0);
 197                         break;
 198                 }
 199         }
 200         OUT_RING(ring, reg);
 201
 202         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 203         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
 204         reg = 0;
 205         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 206                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 207                 case DEPTHX_24_8:
 208                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
 209                                 (stencil & 0xff);
 210                         break;
 211                 case DEPTHX_16:
 212                         reg = (uint32_t)(0xffffffff * depth);
 213                         break;
 214                 default:
 215                         debug_assert(0);
 216                         break;
 217                 }
 218         }
 219         OUT_RING(ring, reg);
 220
 221         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 222         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 223         reg = 0;
 224         if (buffers & PIPE_CLEAR_DEPTH) {
 225                 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
 226                                 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
 227                                 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
 228                                 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
 229         }
 230         if (buffers & PIPE_CLEAR_STENCIL) {
 231                 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
 232                                 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
 233                                 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
 234         }
 235         OUT_RING(ring, reg);
 236
 237         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 238         OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 239         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 240         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 241
 242         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 243         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 244         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
 245                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 246                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 247                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 248                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 249
 250         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 251         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 252         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
 253         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 254                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 255                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 256
 257         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 258         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 259         OUT_RING(ring, 0x0000ffff);
 260
 261         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 262         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 263         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
 264         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
 265                         fb->height));
 266
 267         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 268         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 269         if (buffers & PIPE_CLEAR_COLOR) {
 270                 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 271                                 A2XX_RB_COLOR_MASK_WRITE_GREEN |
 272                                 A2XX_RB_COLOR_MASK_WRITE_BLUE |
 273                                 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 274         } else {
 275                 OUT_RING(ring, 0x0);
 276         }
 277
 278         if (!is_a20x(ctx->screen)) {
 279                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 280                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 281                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 282                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 283         }
 284
 285         fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 286                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 287
 288         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 289         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
 290         OUT_RING(ring, 0x00000000);
 291
 292         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 293         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
 294         OUT_RING(ring, 0x00000000);
 295
 296         ctx->dirty |= FD_DIRTY_ZSA |
 297                         FD_DIRTY_VIEWPORT |
 298                         FD_DIRTY_RASTERIZER |
 299                         FD_DIRTY_SAMPLE_MASK |
 300                         FD_DIRTY_PROG |
 301                         FD_DIRTY_CONST |
 302                         FD_DIRTY_BLEND |
 303                         FD_DIRTY_FRAMEBUFFER;
 304
 305         ctx->dirty_shader[PIPE_SHADER_VERTEX]   |= FD_DIRTY_SHADER_PROG;
 306         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST;
 307
 308         return true;
 309 }
 310
 311 void
 312 fd2_draw_init(struct pipe_context *pctx)
 313 {
 314         struct fd_context *ctx = fd_context(pctx);
 315         ctx->draw_vbo = fd2_draw_vbo;
 316         ctx->clear = fd2_clear;
 317 }