1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
33 #include "util/u_pack_color.h"
35 #include "freedreno_state.h"
36 #include "freedreno_resource.h"
39 #include "fd2_context.h"
41 #include "fd2_program.h"
47 emit_cacheflush(struct fd_ringbuffer
*ring
)
51 for (i
= 0; i
< 12; i
++) {
52 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
53 OUT_RING(ring
, CACHE_FLUSH
);
58 emit_vertexbufs(struct fd_context
*ctx
)
60 struct fd_vertex_stateobj
*vtx
= ctx
->vtx
;
61 struct fd_vertexbuf_stateobj
*vertexbuf
= &ctx
->vertexbuf
;
62 struct fd2_vertex_buf bufs
[PIPE_MAX_ATTRIBS
];
65 if (!vtx
->num_elements
)
68 for (i
= 0; i
< vtx
->num_elements
; i
++) {
69 struct pipe_vertex_element
*elem
= &vtx
->pipe
[i
];
70 struct pipe_vertex_buffer
*vb
=
71 &vertexbuf
->vb
[elem
->vertex_buffer_index
];
72 bufs
[i
].offset
= vb
->buffer_offset
;
73 bufs
[i
].size
= fd_bo_size(fd_resource(vb
->buffer
)->bo
);
74 bufs
[i
].prsc
= vb
->buffer
;
77 // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
78 // CONST(20,0) (or CONST(26,0) in soliv_vp)
80 fd2_emit_vertex_bufs(ctx
->ring
, 0x78, bufs
, vtx
->num_elements
);
84 fd2_draw(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
86 struct fd_ringbuffer
*ring
= ctx
->ring
;
88 if (ctx
->dirty
& FD_DIRTY_VTXBUF
)
91 fd2_emit_state(ctx
, ctx
->dirty
);
93 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
94 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
95 OUT_RING(ring
, info
->start
);
97 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
98 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
99 OUT_RING(ring
, 0x0000003b);
101 OUT_PKT0(ring
, REG_A2XX_TC_CNTL_STATUS
, 1);
102 OUT_RING(ring
, A2XX_TC_CNTL_STATUS_L2_INVALIDATE
);
106 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
107 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX
));
108 OUT_RING(ring
, info
->max_index
); /* VGT_MAX_VTX_INDX */
109 OUT_RING(ring
, info
->min_index
); /* VGT_MIN_VTX_INDX */
111 fd_draw_emit(ctx
, ring
, IGNORE_VISIBILITY
, info
);
113 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
114 OUT_RING(ring
, CP_REG(REG_A2XX_UNKNOWN_2010
));
115 OUT_RING(ring
, 0x00000000);
117 emit_cacheflush(ring
);
122 pack_rgba(enum pipe_format format
, const float *rgba
)
125 util_pack_color(rgba
, format
, &uc
);
130 fd2_clear(struct fd_context
*ctx
, unsigned buffers
,
131 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
133 struct fd2_context
*fd2_ctx
= fd2_context(ctx
);
134 struct fd_ringbuffer
*ring
= ctx
->ring
;
135 struct pipe_framebuffer_state
*fb
= &ctx
->framebuffer
;
136 uint32_t reg
, colr
= 0;
138 if ((buffers
& PIPE_CLEAR_COLOR
) && fb
->nr_cbufs
)
139 colr
= pack_rgba(fb
->cbufs
[0]->format
, color
->f
);
141 /* emit generic state now: */
142 fd2_emit_state(ctx
, ctx
->dirty
&
143 (FD_DIRTY_BLEND
| FD_DIRTY_VIEWPORT
|
144 FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
));
146 fd2_emit_vertex_bufs(ring
, 0x9c, (struct fd2_vertex_buf
[]) {
147 { .prsc
= fd2_ctx
->solid_vertexbuf
, .size
= 48 },
150 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
151 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
154 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
155 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
156 OUT_RING(ring
, 0x0000028f);
158 fd2_program_emit(ring
, &ctx
->solid_prog
);
160 OUT_PKT0(ring
, REG_A2XX_TC_CNTL_STATUS
, 1);
161 OUT_RING(ring
, A2XX_TC_CNTL_STATUS_L2_INVALIDATE
);
163 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
164 OUT_RING(ring
, CP_REG(REG_A2XX_CLEAR_COLOR
));
165 OUT_RING(ring
, colr
);
167 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
168 OUT_RING(ring
, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL
));
169 OUT_RING(ring
, 0x00000084);
171 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
172 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_CONTROL
));
174 if (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
175 reg
|= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE
;
176 switch (fd_pipe2depth(fb
->zsbuf
->format
)) {
178 if (buffers
& PIPE_CLEAR_DEPTH
)
179 reg
|= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
180 if (buffers
& PIPE_CLEAR_STENCIL
)
181 reg
|= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
184 if (buffers
& PIPE_CLEAR_DEPTH
)
185 reg
|= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
194 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
195 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTH_CLEAR
));
197 if (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
198 switch (fd_pipe2depth(fb
->zsbuf
->format
)) {
200 reg
= (((uint32_t)(0xffffff * depth
)) << 8) |
204 reg
= (uint32_t)(0xffffffff * depth
);
210 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
211 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
213 if (buffers
& PIPE_CLEAR_DEPTH
) {
214 reg
|= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS
) |
215 A2XX_RB_DEPTHCONTROL_Z_ENABLE
|
216 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE
|
217 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE
;
219 if (buffers
& PIPE_CLEAR_STENCIL
) {
220 reg
|= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS
) |
221 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE
|
222 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE
);
226 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
227 OUT_RING(ring
, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF
));
228 OUT_RING(ring
, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
229 OUT_RING(ring
, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
231 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
232 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLORCONTROL
));
233 OUT_RING(ring
, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS
) |
234 A2XX_RB_COLORCONTROL_BLEND_DISABLE
|
235 A2XX_RB_COLORCONTROL_ROP_CODE(12) |
236 A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE
) |
237 A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL
));
239 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
240 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
241 OUT_RING(ring
, 0x00000000); /* PA_CL_CLIP_CNTL */
242 OUT_RING(ring
, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST
| /* PA_SU_SC_MODE_CNTL */
243 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
244 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES
));
246 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
247 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
248 OUT_RING(ring
, 0x0000ffff);
250 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
251 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
252 OUT_RING(ring
, xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
253 OUT_RING(ring
, xy2d(fb
->width
, /* PA_SC_WINDOW_SCISSOR_BR */
256 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
257 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
258 if (buffers
& PIPE_CLEAR_COLOR
) {
259 OUT_RING(ring
, A2XX_RB_COLOR_MASK_WRITE_RED
|
260 A2XX_RB_COLOR_MASK_WRITE_GREEN
|
261 A2XX_RB_COLOR_MASK_WRITE_BLUE
|
262 A2XX_RB_COLOR_MASK_WRITE_ALPHA
);
267 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
268 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX
));
269 OUT_RING(ring
, 3); /* VGT_MAX_VTX_INDX */
270 OUT_RING(ring
, 0); /* VGT_MIN_VTX_INDX */
272 fd_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
273 DI_SRC_SEL_AUTO_INDEX
, 3, INDEX_SIZE_IGN
, 0, 0, NULL
);
275 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
276 OUT_RING(ring
, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL
));
277 OUT_RING(ring
, 0x00000000);
279 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
280 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_CONTROL
));
281 OUT_RING(ring
, 0x00000000);
285 fd2_draw_init(struct pipe_context
*pctx
)
287 struct fd_context
*ctx
= fd_context(pctx
);
288 ctx
->draw
= fd2_draw
;
289 ctx
->clear
= fd2_clear
;