freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a2xx / fd2_emit.c
1 /*
2 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31
32 #include "freedreno_resource.h"
33
34 #include "fd2_emit.h"
35 #include "fd2_blend.h"
36 #include "fd2_context.h"
37 #include "fd2_program.h"
38 #include "fd2_rasterizer.h"
39 #include "fd2_texture.h"
40 #include "fd2_util.h"
41 #include "fd2_zsa.h"
42
43 /* NOTE: just define the position for const regs statically.. the blob
44 * driver doesn't seem to change these dynamically, and I can't really
45 * think of a good reason to so..
46 */
47 #define VS_CONST_BASE 0x20
48 #define PS_CONST_BASE 0x120
49
50 static void
51 emit_constants(struct fd_ringbuffer *ring, uint32_t base,
52 struct fd_constbuf_stateobj *constbuf,
53 struct fd2_shader_stateobj *shader)
54 {
55 uint32_t enabled_mask = constbuf->enabled_mask;
56 uint32_t start_base = base;
57 unsigned i;
58
59 /* emit user constants: */
60 while (enabled_mask) {
61 unsigned index = ffs(enabled_mask) - 1;
62 struct pipe_constant_buffer *cb = &constbuf->cb[index];
63 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
64
65 // I expect that size should be a multiple of vec4's:
66 assert(size == align(size, 4));
67
68 /* hmm, sometimes we still seem to end up with consts bound,
69 * even if shader isn't using them, which ends up overwriting
70 * const reg's used for immediates.. this is a hack to work
71 * around that:
72 */
73 if (shader && ((base - start_base) >= (shader->first_immediate * 4)))
74 break;
75
76 const uint32_t *dwords;
77
78 if (cb->user_buffer) {
79 dwords = cb->user_buffer;
80 } else {
81 struct fd_resource *rsc = fd_resource(cb->buffer);
82 dwords = fd_bo_map(rsc->bo);
83 }
84
85 dwords = (uint32_t *)(((uint8_t *)dwords) + cb->buffer_offset);
86
87 OUT_PKT3(ring, CP_SET_CONSTANT, size + 1);
88 OUT_RING(ring, base);
89 for (i = 0; i < size; i++)
90 OUT_RING(ring, *(dwords++));
91
92 base += size;
93 enabled_mask &= ~(1 << index);
94 }
95
96 /* emit shader immediates: */
97 if (shader) {
98 for (i = 0; i < shader->num_immediates; i++) {
99 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
100 OUT_RING(ring, start_base + (4 * (shader->first_immediate + i)));
101 OUT_RING(ring, shader->immediates[i].val[0]);
102 OUT_RING(ring, shader->immediates[i].val[1]);
103 OUT_RING(ring, shader->immediates[i].val[2]);
104 OUT_RING(ring, shader->immediates[i].val[3]);
105 base += 4;
106 }
107 }
108 }
109
110 typedef uint32_t texmask;
111
112 static texmask
113 emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx,
114 struct fd_texture_stateobj *tex, unsigned samp_id, texmask emitted)
115 {
116 unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id);
117 static const struct fd2_sampler_stateobj dummy_sampler = {};
118 static const struct fd2_pipe_sampler_view dummy_view = {};
119 const struct fd2_sampler_stateobj *sampler;
120 const struct fd2_pipe_sampler_view *view;
121
122 if (emitted & (1 << const_idx))
123 return 0;
124
125 sampler = tex->samplers[samp_id] ?
126 fd2_sampler_stateobj(tex->samplers[samp_id]) :
127 &dummy_sampler;
128 view = tex->textures[samp_id] ?
129 fd2_pipe_sampler_view(tex->textures[samp_id]) :
130 &dummy_view;
131
132 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
133 OUT_RING(ring, 0x00010000 + (0x6 * const_idx));
134
135 OUT_RING(ring, sampler->tex0 | view->tex0);
136 if (view->base.texture)
137 OUT_RELOC(ring, fd_resource(view->base.texture)->bo, 0, view->fmt, 0);
138 else
139 OUT_RING(ring, 0);
140
141 OUT_RING(ring, view->tex2);
142 OUT_RING(ring, sampler->tex3 | view->tex3);
143 OUT_RING(ring, sampler->tex4);
144 OUT_RING(ring, sampler->tex5);
145
146 return (1 << const_idx);
147 }
148
149 static void
150 emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx)
151 {
152 struct fd_texture_stateobj *fragtex = &ctx->tex[PIPE_SHADER_FRAGMENT];
153 struct fd_texture_stateobj *verttex = &ctx->tex[PIPE_SHADER_VERTEX];
154 texmask emitted = 0;
155 unsigned i;
156
157 for (i = 0; i < verttex->num_samplers; i++)
158 if (verttex->samplers[i])
159 emitted |= emit_texture(ring, ctx, verttex, i, emitted);
160
161 for (i = 0; i < fragtex->num_samplers; i++)
162 if (fragtex->samplers[i])
163 emitted |= emit_texture(ring, ctx, fragtex, i, emitted);
164 }
165
166 void
167 fd2_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val,
168 struct fd2_vertex_buf *vbufs, uint32_t n)
169 {
170 unsigned i;
171
172 OUT_PKT3(ring, CP_SET_CONSTANT, 1 + (2 * n));
173 OUT_RING(ring, (0x1 << 16) | (val & 0xffff));
174 for (i = 0; i < n; i++) {
175 struct fd_resource *rsc = fd_resource(vbufs[i].prsc);
176 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3, 0);
177 OUT_RING (ring, vbufs[i].size);
178 }
179 }
180
181 void
182 fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
183 {
184 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend);
185 struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa);
186 struct fd_ringbuffer *ring = ctx->batch->draw;
187
188 /* NOTE: we probably want to eventually refactor this so each state
189 * object handles emitting it's own state.. although the mapping of
190 * state to registers is not always orthogonal, sometimes a single
191 * register contains bitfields coming from multiple state objects,
192 * so not sure the best way to deal with that yet.
193 */
194
195 if (dirty & FD_DIRTY_SAMPLE_MASK) {
196 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
197 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
198 OUT_RING(ring, ctx->sample_mask);
199 }
200
201 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
202 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
203
204 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
205 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
206 OUT_RING(ring, zsa->rb_depthcontrol);
207
208 OUT_PKT3(ring, CP_SET_CONSTANT, 4);
209 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
210 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
211 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
212 OUT_RING(ring, zsa->rb_stencilrefmask |
213 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
214 OUT_RING(ring, zsa->rb_alpha_ref);
215 }
216
217 if (ctx->rasterizer && dirty & FD_DIRTY_RASTERIZER) {
218 struct fd2_rasterizer_stateobj *rasterizer =
219 fd2_rasterizer_stateobj(ctx->rasterizer);
220 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
221 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
222 OUT_RING(ring, rasterizer->pa_cl_clip_cntl);
223 OUT_RING(ring, rasterizer->pa_su_sc_mode_cntl |
224 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
225
226 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
227 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE));
228 OUT_RING(ring, rasterizer->pa_su_point_size);
229 OUT_RING(ring, rasterizer->pa_su_point_minmax);
230 OUT_RING(ring, rasterizer->pa_su_line_cntl);
231 OUT_RING(ring, rasterizer->pa_sc_line_stipple);
232
233 OUT_PKT3(ring, CP_SET_CONSTANT, 6);
234 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
235 OUT_RING(ring, rasterizer->pa_su_vtx_cntl);
236 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
237 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
238 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
239 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
240 }
241
242 /* NOTE: scissor enabled bit is part of rasterizer state: */
243 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
244 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
245
246 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
247 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
248 OUT_RING(ring, xy2d(scissor->minx, /* PA_SC_WINDOW_SCISSOR_TL */
249 scissor->miny));
250 OUT_RING(ring, xy2d(scissor->maxx, /* PA_SC_WINDOW_SCISSOR_BR */
251 scissor->maxy));
252
253 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
254 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
255 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
256 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
257 }
258
259 if (dirty & FD_DIRTY_VIEWPORT) {
260 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
261 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
262 OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */
263 OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */
264 OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */
265 OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */
266 OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */
267 OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */
268
269 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
270 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
271 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
272 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
273 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
274 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
275 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
276 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
277 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
278 }
279
280 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE)) {
281 fd2_program_validate(ctx);
282 fd2_program_emit(ring, &ctx->prog);
283 }
284
285 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) {
286 emit_constants(ring, VS_CONST_BASE * 4,
287 &ctx->constbuf[PIPE_SHADER_VERTEX],
288 (dirty & FD_DIRTY_PROG) ? ctx->prog.vp : NULL);
289 emit_constants(ring, PS_CONST_BASE * 4,
290 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
291 (dirty & FD_DIRTY_PROG) ? ctx->prog.fp : NULL);
292 }
293
294 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
295 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
296 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
297 OUT_RING(ring, blend ? zsa->rb_colorcontrol | blend->rb_colorcontrol : 0);
298 }
299
300 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
301 enum pipe_format format =
302 pipe_surface_format(ctx->batch->framebuffer.cbufs[0]);
303 bool has_alpha = util_format_has_alpha(format);
304
305 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
306 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
307 OUT_RING(ring, blend ? blend->rb_blendcontrol_alpha |
308 COND(has_alpha, blend->rb_blendcontrol_rgb) |
309 COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb) : 0);
310
311 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
312 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
313 OUT_RING(ring, blend ? blend->rb_colormask : 0xf);
314 }
315
316 if (dirty & FD_DIRTY_BLEND_COLOR) {
317 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
318 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
319 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[0]));
320 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[1]));
321 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[2]));
322 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[3]));
323 }
324
325 if (dirty & (FD_DIRTY_TEX | FD_DIRTY_PROG))
326 emit_textures(ring, ctx);
327 }
328
329 /* emit per-context initialization:
330 */
331 void
332 fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
333 {
334 if (is_a20x(ctx->screen)) {
335 OUT_PKT0(ring, REG_A2XX_RB_BC_CONTROL, 1);
336 OUT_RING(ring,
337 A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(3) |
338 A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP |
339 A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE |
340 A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(8) |
341 A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(3));
342 }
343
344 OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1);
345 OUT_RING(ring, 0x00000002);
346
347 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
348 OUT_RING(ring, 0x00007fff);
349
350 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
351 OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST));
352 OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) |
353 A2XX_SQ_VS_CONST_SIZE(0x100));
354
355 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
356 OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST));
357 OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) |
358 A2XX_SQ_PS_CONST_SIZE(0xe0));
359
360 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
361 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
362 OUT_RING(ring, 0xffffffff); /* VGT_MAX_VTX_INDX */
363 OUT_RING(ring, 0x00000000); /* VGT_MIN_VTX_INDX */
364
365 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
366 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
367 OUT_RING(ring, 0x00000000);
368
369 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
370 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
371 OUT_RING(ring, 0x0000003b);
372
373 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
374 OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC));
375 OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY));
376
377 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
378 OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL));
379 OUT_RING(ring, 0xffffffff);
380
381 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
382 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG));
383 OUT_RING(ring, 0x00000000);
384
385 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
386 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL));
387 OUT_RING(ring, 0x00000000);
388
389 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
390 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
391 OUT_RING(ring, 0x00000000);
392
393 // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
394 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
395 OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
396 OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
397
398 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
399 OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS));
400 OUT_RING(ring, 0x88888888);
401
402 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
403 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK));
404 OUT_RING(ring, 0xffffffff);
405
406 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
407 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO));
408 OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) |
409 A2XX_RB_COPY_DEST_INFO_WRITE_RED |
410 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
411 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
412 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
413
414 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
415 OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0));
416 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_0 */
417 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_1 */
418
419 OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1);
420 OUT_RING(ring, 0x00000000);
421
422 OUT_PKT3(ring, CP_WAIT_REG_EQ, 4);
423 OUT_RING(ring, 0x000005d0);
424 OUT_RING(ring, 0x00000000);
425 OUT_RING(ring, 0x5f601000);
426 OUT_RING(ring, 0x00000001);
427
428 OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1);
429 OUT_RING(ring, 0x00000180);
430
431 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
432 OUT_RING(ring, 0x00000300);
433
434 OUT_PKT3(ring, CP_SET_SHADER_BASES, 1);
435 OUT_RING(ring, 0x80000180);
436
437 /* not sure what this form of CP_SET_CONSTANT is.. */
438 OUT_PKT3(ring, CP_SET_CONSTANT, 13);
439 OUT_RING(ring, 0x00000000);
440 OUT_RING(ring, 0x00000000);
441 OUT_RING(ring, 0x00000000);
442 OUT_RING(ring, 0x00000000);
443 OUT_RING(ring, 0x00000000);
444 OUT_RING(ring, 0x469c4000);
445 OUT_RING(ring, 0x3f800000);
446 OUT_RING(ring, 0x3f000000);
447 OUT_RING(ring, 0x00000000);
448 OUT_RING(ring, 0x40000000);
449 OUT_RING(ring, 0x3f400000);
450 OUT_RING(ring, 0x3ec00000);
451 OUT_RING(ring, 0x3e800000);
452
453 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
454 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
455 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
456 A2XX_RB_COLOR_MASK_WRITE_GREEN |
457 A2XX_RB_COLOR_MASK_WRITE_BLUE |
458 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
459
460 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
461 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
462 OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */
463 OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */
464 OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */
465 OUT_RING(ring, 0x000000ff); /* RB_BLEND_ALPHA */
466 }
467
468 static void
469 fd2_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
470 {
471 __OUT_IB(ring, false, target);
472 }
473
474 void
475 fd2_emit_init(struct pipe_context *pctx)
476 {
477 struct fd_context *ctx = fd_context(pctx);
478 ctx->emit_ib = fd2_emit_ib;
479 }