src/gallium/drivers/freedreno/a2xx/fd2_emit.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_helpers.h"
  33
  34 #include "freedreno_resource.h"
  35
  36 #include "fd2_emit.h"
  37 #include "fd2_blend.h"
  38 #include "fd2_context.h"
  39 #include "fd2_program.h"
  40 #include "fd2_rasterizer.h"
  41 #include "fd2_texture.h"
  42 #include "fd2_util.h"
  43 #include "fd2_zsa.h"
  44
  45 /* NOTE: just define the position for const regs statically.. the blob
  46  * driver doesn't seem to change these dynamically, and I can't really
  47  * think of a good reason to so..
  48  */
  49 #define VS_CONST_BASE 0x20
  50 #define PS_CONST_BASE 0x120
  51
  52 static void
  53 emit_constants(struct fd_ringbuffer *ring, uint32_t base,
  54                 struct fd_constbuf_stateobj *constbuf,
  55                 struct fd2_shader_stateobj *shader)
  56 {
  57         uint32_t enabled_mask = constbuf->enabled_mask;
  58         uint32_t start_base = base;
  59         unsigned i;
  60
  61         // XXX TODO only emit dirty consts.. but we need to keep track if
  62         // they are clobbered by a clear, gmem2mem, or mem2gmem..
  63         constbuf->dirty_mask = enabled_mask;
  64
  65         /* emit user constants: */
  66         while (enabled_mask) {
  67                 unsigned index = ffs(enabled_mask) - 1;
  68                 struct pipe_constant_buffer *cb = &constbuf->cb[index];
  69                 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
  70
  71                 // I expect that size should be a multiple of vec4's:
  72                 assert(size == align(size, 4));
  73
  74                 /* hmm, sometimes we still seem to end up with consts bound,
  75                  * even if shader isn't using them, which ends up overwriting
  76                  * const reg's used for immediates.. this is a hack to work
  77                  * around that:
  78                  */
  79                 if (shader && ((base - start_base) >= (shader->first_immediate * 4)))
  80                         break;
  81
  82                 if (constbuf->dirty_mask & (1 << index)) {
  83                         const uint32_t *dwords;
  84
  85                         if (cb->user_buffer) {
  86                                 dwords = cb->user_buffer;
  87                         } else {
  88                                 struct fd_resource *rsc = fd_resource(cb->buffer);
  89                                 dwords = fd_bo_map(rsc->bo);
  90                         }
  91
  92                         dwords = (uint32_t *)(((uint8_t *)dwords) + cb->buffer_offset);
  93
  94                         OUT_PKT3(ring, CP_SET_CONSTANT, size + 1);
  95                         OUT_RING(ring, base);
  96                         for (i = 0; i < size; i++)
  97                                 OUT_RING(ring, *(dwords++));
  98
  99                         constbuf->dirty_mask &= ~(1 << index);
 100                 }
 101
 102                 base += size;
 103                 enabled_mask &= ~(1 << index);
 104         }
 105
 106         /* emit shader immediates: */
 107         if (shader) {
 108                 for (i = 0; i < shader->num_immediates; i++) {
 109                         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 110                         OUT_RING(ring, start_base + (4 * (shader->first_immediate + i)));
 111                         OUT_RING(ring, shader->immediates[i].val[0]);
 112                         OUT_RING(ring, shader->immediates[i].val[1]);
 113                         OUT_RING(ring, shader->immediates[i].val[2]);
 114                         OUT_RING(ring, shader->immediates[i].val[3]);
 115                         base += 4;
 116                 }
 117         }
 118 }
 119
 120 typedef uint32_t texmask;
 121
 122 static texmask
 123 emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx,
 124                 struct fd_texture_stateobj *tex, unsigned samp_id, texmask emitted)
 125 {
 126         unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id);
 127         static const struct fd2_sampler_stateobj dummy_sampler = {};
 128         const struct fd2_sampler_stateobj *sampler;
 129         struct fd2_pipe_sampler_view *view;
 130
 131         if (emitted & (1 << const_idx))
 132                 return 0;
 133
 134         sampler = tex->samplers[samp_id] ?
 135                         fd2_sampler_stateobj(tex->samplers[samp_id]) :
 136                         &dummy_sampler;
 137         view = fd2_pipe_sampler_view(tex->textures[samp_id]);
 138
 139         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 140         OUT_RING(ring, 0x00010000 + (0x6 * const_idx));
 141
 142         OUT_RING(ring, sampler->tex0 | view->tex0);
 143         OUT_RELOC(ring, fd_resource(view->base.texture)->bo, 0, view->fmt, 0);
 144         OUT_RING(ring, view->tex2);
 145         OUT_RING(ring, sampler->tex3 | view->tex3);
 146         OUT_RING(ring, sampler->tex4);
 147         OUT_RING(ring, sampler->tex5);
 148
 149         return (1 << const_idx);
 150 }
 151
 152 static void
 153 emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx)
 154 {
 155         struct fd_texture_stateobj *fragtex = &ctx->tex[PIPE_SHADER_FRAGMENT];
 156         struct fd_texture_stateobj *verttex = &ctx->tex[PIPE_SHADER_VERTEX];
 157         texmask emitted = 0;
 158         unsigned i;
 159
 160         for (i = 0; i < verttex->num_samplers; i++)
 161                 if (verttex->samplers[i])
 162                         emitted |= emit_texture(ring, ctx, verttex, i, emitted);
 163
 164         for (i = 0; i < fragtex->num_samplers; i++)
 165                 if (fragtex->samplers[i])
 166                         emitted |= emit_texture(ring, ctx, fragtex, i, emitted);
 167 }
 168
 169 void
 170 fd2_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val,
 171                 struct fd2_vertex_buf *vbufs, uint32_t n)
 172 {
 173         unsigned i;
 174
 175         OUT_PKT3(ring, CP_SET_CONSTANT, 1 + (2 * n));
 176         OUT_RING(ring, (0x1 << 16) | (val & 0xffff));
 177         for (i = 0; i < n; i++) {
 178                 struct fd_resource *rsc = fd_resource(vbufs[i].prsc);
 179                 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3, 0);
 180                 OUT_RING (ring, vbufs[i].size);
 181         }
 182 }
 183
 184 void
 185 fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
 186 {
 187         struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend);
 188         struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa);
 189         struct fd_ringbuffer *ring = ctx->batch->draw;
 190
 191         /* NOTE: we probably want to eventually refactor this so each state
 192          * object handles emitting it's own state..  although the mapping of
 193          * state to registers is not always orthogonal, sometimes a single
 194          * register contains bitfields coming from multiple state objects,
 195          * so not sure the best way to deal with that yet.
 196          */
 197
 198         if (dirty & FD_DIRTY_SAMPLE_MASK) {
 199                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 200                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 201                 OUT_RING(ring, ctx->sample_mask);
 202         }
 203
 204         if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
 205                 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
 206
 207                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 208                 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 209                 OUT_RING(ring, zsa->rb_depthcontrol);
 210
 211                 OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 212                 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
 213                 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
 214                                 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
 215                 OUT_RING(ring, zsa->rb_stencilrefmask |
 216                                 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
 217                 OUT_RING(ring, zsa->rb_alpha_ref);
 218         }
 219
 220         if (ctx->rasterizer && dirty & FD_DIRTY_RASTERIZER) {
 221                 struct fd2_rasterizer_stateobj *rasterizer =
 222                                 fd2_rasterizer_stateobj(ctx->rasterizer);
 223                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 224                 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 225                 OUT_RING(ring, rasterizer->pa_cl_clip_cntl);
 226                 OUT_RING(ring, rasterizer->pa_su_sc_mode_cntl |
 227                                 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
 228
 229                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 230                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE));
 231                 OUT_RING(ring, rasterizer->pa_su_point_size);
 232                 OUT_RING(ring, rasterizer->pa_su_point_minmax);
 233                 OUT_RING(ring, rasterizer->pa_su_line_cntl);
 234                 OUT_RING(ring, rasterizer->pa_sc_line_stipple);
 235
 236                 OUT_PKT3(ring, CP_SET_CONSTANT, 6);
 237                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
 238                 OUT_RING(ring, rasterizer->pa_su_vtx_cntl);
 239                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_VERT_CLIP_ADJ */
 240                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_VERT_DISC_ADJ */
 241                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_HORZ_CLIP_ADJ */
 242                 OUT_RING(ring, fui(1.0));                /* PA_CL_GB_HORZ_DISC_ADJ */
 243         }
 244
 245         if (dirty & FD_DIRTY_SCISSOR) {
 246                 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 247
 248                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 249                 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 250                 OUT_RING(ring, xy2d(scissor->minx,       /* PA_SC_WINDOW_SCISSOR_TL */
 251                                 scissor->miny));
 252                 OUT_RING(ring, xy2d(scissor->maxx,       /* PA_SC_WINDOW_SCISSOR_BR */
 253                                 scissor->maxy));
 254
 255                 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
 256                 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
 257                 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
 258                 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
 259         }
 260
 261         if (dirty & FD_DIRTY_VIEWPORT) {
 262                 OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 263                 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
 264                 OUT_RING(ring, fui(ctx->viewport.scale[0]));       /* PA_CL_VPORT_XSCALE */
 265                 OUT_RING(ring, fui(ctx->viewport.translate[0]));   /* PA_CL_VPORT_XOFFSET */
 266                 OUT_RING(ring, fui(ctx->viewport.scale[1]));       /* PA_CL_VPORT_YSCALE */
 267                 OUT_RING(ring, fui(ctx->viewport.translate[1]));   /* PA_CL_VPORT_YOFFSET */
 268                 OUT_RING(ring, fui(ctx->viewport.scale[2]));       /* PA_CL_VPORT_ZSCALE */
 269                 OUT_RING(ring, fui(ctx->viewport.translate[2]));   /* PA_CL_VPORT_ZOFFSET */
 270
 271                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 272                 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 273                 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
 274                                 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 275                                 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 276                                 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 277                                 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
 278                                 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
 279                                 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
 280         }
 281
 282         if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE)) {
 283                 fd2_program_validate(ctx);
 284                 fd2_program_emit(ring, &ctx->prog);
 285         }
 286
 287         if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) {
 288                 emit_constants(ring,  VS_CONST_BASE * 4,
 289                                 &ctx->constbuf[PIPE_SHADER_VERTEX],
 290                                 (dirty & FD_DIRTY_PROG) ? ctx->prog.vp : NULL);
 291                 emit_constants(ring, PS_CONST_BASE * 4,
 292                                 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
 293                                 (dirty & FD_DIRTY_PROG) ? ctx->prog.fp : NULL);
 294         }
 295
 296         if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
 297                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 298                 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 299                 OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol);
 300         }
 301
 302         if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
 303                 enum pipe_format format =
 304                         pipe_surface_format(ctx->batch->framebuffer.cbufs[0]);
 305                 bool has_alpha = util_format_has_alpha(format);
 306
 307                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 308                 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
 309                 OUT_RING(ring, blend->rb_blendcontrol_alpha |
 310                         COND(has_alpha, blend->rb_blendcontrol_rgb) |
 311                         COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb));
 312
 313                 OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 314                 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 315                 OUT_RING(ring, blend->rb_colormask);
 316         }
 317
 318         if (dirty & FD_DIRTY_BLEND_COLOR) {
 319                 OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 320                 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
 321                 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[0]));
 322                 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[1]));
 323                 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[2]));
 324                 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[3]));
 325         }
 326
 327         if (dirty & (FD_DIRTY_TEX | FD_DIRTY_PROG))
 328                 emit_textures(ring, ctx);
 329 }
 330
 331 /* emit per-context initialization:
 332  */
 333 void
 334 fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring)
 335 {
 336         OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1);
 337         OUT_RING(ring, 0x00000002);
 338
 339         OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 340         OUT_RING(ring, 0x00007fff);
 341
 342         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 343         OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST));
 344         OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) |
 345                         A2XX_SQ_VS_CONST_SIZE(0x100));
 346
 347         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 348         OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST));
 349         OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) |
 350                         A2XX_SQ_PS_CONST_SIZE(0xe0));
 351
 352         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 353         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 354         OUT_RING(ring, 0xffffffff);        /* VGT_MAX_VTX_INDX */
 355         OUT_RING(ring, 0x00000000);        /* VGT_MIN_VTX_INDX */
 356
 357         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 358         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 359         OUT_RING(ring, 0x00000000);
 360
 361         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 362         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 363         OUT_RING(ring, 0x0000003b);
 364
 365         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 366         OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC));
 367         OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY));
 368
 369         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 370         OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL));
 371         OUT_RING(ring, 0xffffffff);
 372
 373         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 374         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG));
 375         OUT_RING(ring, 0x00000000);
 376
 377         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 378         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL));
 379         OUT_RING(ring, 0x00000000);
 380
 381         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 382         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 383         OUT_RING(ring, 0x00000000);
 384
 385         // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
 386         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 387         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 388         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 389
 390         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 391         OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS));
 392         OUT_RING(ring, 0x88888888);
 393
 394         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 395         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK));
 396         OUT_RING(ring, 0xffffffff);
 397
 398         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 399         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO));
 400         OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) |
 401                         A2XX_RB_COPY_DEST_INFO_WRITE_RED |
 402                         A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
 403                         A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
 404                         A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
 405
 406         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 407         OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0));
 408         OUT_RING(ring, 0x00000000);        /* SQ_WRAPPING_0 */
 409         OUT_RING(ring, 0x00000000);        /* SQ_WRAPPING_1 */
 410
 411         OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1);
 412         OUT_RING(ring, 0x00000000);
 413
 414         OUT_PKT3(ring, CP_WAIT_REG_EQ, 4);
 415         OUT_RING(ring, 0x000005d0);
 416         OUT_RING(ring, 0x00000000);
 417         OUT_RING(ring, 0x5f601000);
 418         OUT_RING(ring, 0x00000001);
 419
 420         OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1);
 421         OUT_RING(ring, 0x00000180);
 422
 423         OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
 424         OUT_RING(ring, 0x00000300);
 425
 426         OUT_PKT3(ring, CP_SET_SHADER_BASES, 1);
 427         OUT_RING(ring, 0x80000180);
 428
 429         /* not sure what this form of CP_SET_CONSTANT is.. */
 430         OUT_PKT3(ring, CP_SET_CONSTANT, 13);
 431         OUT_RING(ring, 0x00000000);
 432         OUT_RING(ring, 0x00000000);
 433         OUT_RING(ring, 0x00000000);
 434         OUT_RING(ring, 0x00000000);
 435         OUT_RING(ring, 0x00000000);
 436         OUT_RING(ring, 0x469c4000);
 437         OUT_RING(ring, 0x3f800000);
 438         OUT_RING(ring, 0x3f000000);
 439         OUT_RING(ring, 0x00000000);
 440         OUT_RING(ring, 0x40000000);
 441         OUT_RING(ring, 0x3f400000);
 442         OUT_RING(ring, 0x3ec00000);
 443         OUT_RING(ring, 0x3e800000);
 444
 445         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 446         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
 447         OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
 448                         A2XX_RB_COLOR_MASK_WRITE_GREEN |
 449                         A2XX_RB_COLOR_MASK_WRITE_BLUE |
 450                         A2XX_RB_COLOR_MASK_WRITE_ALPHA);
 451
 452         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 453         OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
 454         OUT_RING(ring, 0x00000000);        /* RB_BLEND_RED */
 455         OUT_RING(ring, 0x00000000);        /* RB_BLEND_GREEN */
 456         OUT_RING(ring, 0x00000000);        /* RB_BLEND_BLUE */
 457         OUT_RING(ring, 0x000000ff);        /* RB_BLEND_ALPHA */
 458 }
 459
 460 static void
 461 fd2_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 462 {
 463         __OUT_IB(ring, false, target);
 464 }
 465
 466 void
 467 fd2_emit_init(struct pipe_context *pctx)
 468 {
 469         struct fd_context *ctx = fd_context(pctx);
 470         ctx->emit_ib = fd2_emit_ib;
 471 }