1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
34 #include "freedreno_resource.h"
37 #include "fd2_blend.h"
38 #include "fd2_context.h"
39 #include "fd2_program.h"
40 #include "fd2_rasterizer.h"
41 #include "fd2_texture.h"
45 /* NOTE: just define the position for const regs statically.. the blob
46 * driver doesn't seem to change these dynamically, and I can't really
47 * think of a good reason to so..
49 #define VS_CONST_BASE 0x20
50 #define PS_CONST_BASE 0x120
53 emit_constants(struct fd_ringbuffer
*ring
, uint32_t base
,
54 struct fd_constbuf_stateobj
*constbuf
,
55 struct fd2_shader_stateobj
*shader
)
57 uint32_t enabled_mask
= constbuf
->enabled_mask
;
58 uint32_t start_base
= base
;
61 // XXX TODO only emit dirty consts.. but we need to keep track if
62 // they are clobbered by a clear, gmem2mem, or mem2gmem..
63 constbuf
->dirty_mask
= enabled_mask
;
65 /* emit user constants: */
66 while (enabled_mask
) {
67 unsigned index
= ffs(enabled_mask
) - 1;
68 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
69 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
71 // I expect that size should be a multiple of vec4's:
72 assert(size
== align(size
, 4));
74 /* hmm, sometimes we still seem to end up with consts bound,
75 * even if shader isn't using them, which ends up overwriting
76 * const reg's used for immediates.. this is a hack to work
79 if (shader
&& ((base
- start_base
) >= (shader
->first_immediate
* 4)))
82 if (constbuf
->dirty_mask
& (1 << index
)) {
83 const uint32_t *dwords
;
85 if (cb
->user_buffer
) {
86 dwords
= cb
->user_buffer
;
88 struct fd_resource
*rsc
= fd_resource(cb
->buffer
);
89 dwords
= fd_bo_map(rsc
->bo
);
92 dwords
= (uint32_t *)(((uint8_t *)dwords
) + cb
->buffer_offset
);
94 OUT_PKT3(ring
, CP_SET_CONSTANT
, size
+ 1);
96 for (i
= 0; i
< size
; i
++)
97 OUT_RING(ring
, *(dwords
++));
99 constbuf
->dirty_mask
&= ~(1 << index
);
103 enabled_mask
&= ~(1 << index
);
106 /* emit shader immediates: */
108 for (i
= 0; i
< shader
->num_immediates
; i
++) {
109 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
110 OUT_RING(ring
, start_base
+ (4 * (shader
->first_immediate
+ i
)));
111 OUT_RING(ring
, shader
->immediates
[i
].val
[0]);
112 OUT_RING(ring
, shader
->immediates
[i
].val
[1]);
113 OUT_RING(ring
, shader
->immediates
[i
].val
[2]);
114 OUT_RING(ring
, shader
->immediates
[i
].val
[3]);
120 typedef uint32_t texmask
;
123 emit_texture(struct fd_ringbuffer
*ring
, struct fd_context
*ctx
,
124 struct fd_texture_stateobj
*tex
, unsigned samp_id
, texmask emitted
)
126 unsigned const_idx
= fd2_get_const_idx(ctx
, tex
, samp_id
);
127 static const struct fd2_sampler_stateobj dummy_sampler
= {};
128 const struct fd2_sampler_stateobj
*sampler
;
129 struct fd2_pipe_sampler_view
*view
;
131 if (emitted
& (1 << const_idx
))
134 sampler
= tex
->samplers
[samp_id
] ?
135 fd2_sampler_stateobj(tex
->samplers
[samp_id
]) :
137 view
= fd2_pipe_sampler_view(tex
->textures
[samp_id
]);
139 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
140 OUT_RING(ring
, 0x00010000 + (0x6 * const_idx
));
142 OUT_RING(ring
, sampler
->tex0
| view
->tex0
);
143 OUT_RELOC(ring
, fd_resource(view
->base
.texture
)->bo
, 0, view
->fmt
, 0);
144 OUT_RING(ring
, view
->tex2
);
145 OUT_RING(ring
, sampler
->tex3
| view
->tex3
);
146 OUT_RING(ring
, sampler
->tex4
);
147 OUT_RING(ring
, sampler
->tex5
);
149 return (1 << const_idx
);
153 emit_textures(struct fd_ringbuffer
*ring
, struct fd_context
*ctx
)
155 struct fd_texture_stateobj
*fragtex
= &ctx
->tex
[PIPE_SHADER_FRAGMENT
];
156 struct fd_texture_stateobj
*verttex
= &ctx
->tex
[PIPE_SHADER_VERTEX
];
160 for (i
= 0; i
< verttex
->num_samplers
; i
++)
161 if (verttex
->samplers
[i
])
162 emitted
|= emit_texture(ring
, ctx
, verttex
, i
, emitted
);
164 for (i
= 0; i
< fragtex
->num_samplers
; i
++)
165 if (fragtex
->samplers
[i
])
166 emitted
|= emit_texture(ring
, ctx
, fragtex
, i
, emitted
);
170 fd2_emit_vertex_bufs(struct fd_ringbuffer
*ring
, uint32_t val
,
171 struct fd2_vertex_buf
*vbufs
, uint32_t n
)
175 OUT_PKT3(ring
, CP_SET_CONSTANT
, 1 + (2 * n
));
176 OUT_RING(ring
, (0x1 << 16) | (val
& 0xffff));
177 for (i
= 0; i
< n
; i
++) {
178 struct fd_resource
*rsc
= fd_resource(vbufs
[i
].prsc
);
179 OUT_RELOC(ring
, rsc
->bo
, vbufs
[i
].offset
, 3, 0);
180 OUT_RING (ring
, vbufs
[i
].size
);
185 fd2_emit_state(struct fd_context
*ctx
, const enum fd_dirty_3d_state dirty
)
187 struct fd2_blend_stateobj
*blend
= fd2_blend_stateobj(ctx
->blend
);
188 struct fd2_zsa_stateobj
*zsa
= fd2_zsa_stateobj(ctx
->zsa
);
189 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
191 /* NOTE: we probably want to eventually refactor this so each state
192 * object handles emitting it's own state.. although the mapping of
193 * state to registers is not always orthogonal, sometimes a single
194 * register contains bitfields coming from multiple state objects,
195 * so not sure the best way to deal with that yet.
198 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
199 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
200 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
201 OUT_RING(ring
, ctx
->sample_mask
);
204 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
205 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
207 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
208 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
209 OUT_RING(ring
, zsa
->rb_depthcontrol
);
211 OUT_PKT3(ring
, CP_SET_CONSTANT
, 4);
212 OUT_RING(ring
, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF
));
213 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
214 A2XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[1]));
215 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
216 A2XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
217 OUT_RING(ring
, zsa
->rb_alpha_ref
);
220 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
221 struct fd2_rasterizer_stateobj
*rasterizer
=
222 fd2_rasterizer_stateobj(ctx
->rasterizer
);
223 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
224 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
225 OUT_RING(ring
, rasterizer
->pa_cl_clip_cntl
);
226 OUT_RING(ring
, rasterizer
->pa_su_sc_mode_cntl
|
227 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE
);
229 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
230 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_POINT_SIZE
));
231 OUT_RING(ring
, rasterizer
->pa_su_point_size
);
232 OUT_RING(ring
, rasterizer
->pa_su_point_minmax
);
233 OUT_RING(ring
, rasterizer
->pa_su_line_cntl
);
234 OUT_RING(ring
, rasterizer
->pa_sc_line_stipple
);
236 OUT_PKT3(ring
, CP_SET_CONSTANT
, 6);
237 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_VTX_CNTL
));
238 OUT_RING(ring
, rasterizer
->pa_su_vtx_cntl
);
239 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
240 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
241 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
242 OUT_RING(ring
, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
245 if (dirty
& FD_DIRTY_SCISSOR
) {
246 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
248 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
249 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
250 OUT_RING(ring
, xy2d(scissor
->minx
, /* PA_SC_WINDOW_SCISSOR_TL */
252 OUT_RING(ring
, xy2d(scissor
->maxx
, /* PA_SC_WINDOW_SCISSOR_BR */
255 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
256 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
257 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
258 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
261 if (dirty
& FD_DIRTY_VIEWPORT
) {
262 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
263 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE
));
264 OUT_RING(ring
, fui(ctx
->viewport
.scale
[0])); /* PA_CL_VPORT_XSCALE */
265 OUT_RING(ring
, fui(ctx
->viewport
.translate
[0])); /* PA_CL_VPORT_XOFFSET */
266 OUT_RING(ring
, fui(ctx
->viewport
.scale
[1])); /* PA_CL_VPORT_YSCALE */
267 OUT_RING(ring
, fui(ctx
->viewport
.translate
[1])); /* PA_CL_VPORT_YOFFSET */
268 OUT_RING(ring
, fui(ctx
->viewport
.scale
[2])); /* PA_CL_VPORT_ZSCALE */
269 OUT_RING(ring
, fui(ctx
->viewport
.translate
[2])); /* PA_CL_VPORT_ZOFFSET */
271 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
272 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
273 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT
|
274 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
275 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
276 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
277 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
|
278 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA
|
279 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA
);
282 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_VTXSTATE
| FD_DIRTY_TEXSTATE
)) {
283 fd2_program_validate(ctx
);
284 fd2_program_emit(ring
, &ctx
->prog
);
287 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONST
)) {
288 emit_constants(ring
, VS_CONST_BASE
* 4,
289 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
290 (dirty
& FD_DIRTY_PROG
) ? ctx
->prog
.vp
: NULL
);
291 emit_constants(ring
, PS_CONST_BASE
* 4,
292 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
293 (dirty
& FD_DIRTY_PROG
) ? ctx
->prog
.fp
: NULL
);
296 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_ZSA
)) {
297 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
298 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLORCONTROL
));
299 OUT_RING(ring
, zsa
->rb_colorcontrol
| blend
->rb_colorcontrol
);
302 if (dirty
& FD_DIRTY_BLEND
) {
303 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
304 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_CONTROL
));
305 OUT_RING(ring
, blend
->rb_blendcontrol
);
307 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
308 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
309 OUT_RING(ring
, blend
->rb_colormask
);
312 if (dirty
& (FD_DIRTY_TEX
| FD_DIRTY_PROG
))
313 emit_textures(ring
, ctx
);
316 /* emit per-context initialization:
319 fd2_emit_restore(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
321 OUT_PKT0(ring
, REG_A2XX_TP0_CHICKEN
, 1);
322 OUT_RING(ring
, 0x00000002);
324 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
325 OUT_RING(ring
, 0x00007fff);
327 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
328 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_VS_CONST
));
329 OUT_RING(ring
, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE
) |
330 A2XX_SQ_VS_CONST_SIZE(0x100));
332 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
333 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_PS_CONST
));
334 OUT_RING(ring
, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE
) |
335 A2XX_SQ_PS_CONST_SIZE(0xe0));
337 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
338 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX
));
339 OUT_RING(ring
, 0xffffffff); /* VGT_MAX_VTX_INDX */
340 OUT_RING(ring
, 0x00000000); /* VGT_MIN_VTX_INDX */
342 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
343 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
344 OUT_RING(ring
, 0x00000000);
346 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
347 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
348 OUT_RING(ring
, 0x0000003b);
350 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
351 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_CONTEXT_MISC
));
352 OUT_RING(ring
, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY
));
354 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
355 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL
));
356 OUT_RING(ring
, 0xffffffff);
358 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
359 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_CONFIG
));
360 OUT_RING(ring
, 0x00000000);
362 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
363 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_LINE_CNTL
));
364 OUT_RING(ring
, 0x00000000);
366 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
367 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
368 OUT_RING(ring
, 0x00000000);
370 // XXX we change this dynamically for draw/clear.. vs gmem<->mem..
371 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
372 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
373 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH
));
375 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
376 OUT_RING(ring
, CP_REG(REG_A2XX_RB_SAMPLE_POS
));
377 OUT_RING(ring
, 0x88888888);
379 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
380 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK
));
381 OUT_RING(ring
, 0xffffffff);
383 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
384 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_DEST_INFO
));
385 OUT_RING(ring
, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4
) |
386 A2XX_RB_COPY_DEST_INFO_WRITE_RED
|
387 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN
|
388 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE
|
389 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA
);
391 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
392 OUT_RING(ring
, CP_REG(REG_A2XX_SQ_WRAPPING_0
));
393 OUT_RING(ring
, 0x00000000); /* SQ_WRAPPING_0 */
394 OUT_RING(ring
, 0x00000000); /* SQ_WRAPPING_1 */
396 OUT_PKT3(ring
, CP_SET_DRAW_INIT_FLAGS
, 1);
397 OUT_RING(ring
, 0x00000000);
399 OUT_PKT3(ring
, CP_WAIT_REG_EQ
, 4);
400 OUT_RING(ring
, 0x000005d0);
401 OUT_RING(ring
, 0x00000000);
402 OUT_RING(ring
, 0x5f601000);
403 OUT_RING(ring
, 0x00000001);
405 OUT_PKT0(ring
, REG_A2XX_SQ_INST_STORE_MANAGMENT
, 1);
406 OUT_RING(ring
, 0x00000180);
408 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
409 OUT_RING(ring
, 0x00000300);
411 OUT_PKT3(ring
, CP_SET_SHADER_BASES
, 1);
412 OUT_RING(ring
, 0x80000180);
414 /* not sure what this form of CP_SET_CONSTANT is.. */
415 OUT_PKT3(ring
, CP_SET_CONSTANT
, 13);
416 OUT_RING(ring
, 0x00000000);
417 OUT_RING(ring
, 0x00000000);
418 OUT_RING(ring
, 0x00000000);
419 OUT_RING(ring
, 0x00000000);
420 OUT_RING(ring
, 0x00000000);
421 OUT_RING(ring
, 0x469c4000);
422 OUT_RING(ring
, 0x3f800000);
423 OUT_RING(ring
, 0x3f000000);
424 OUT_RING(ring
, 0x00000000);
425 OUT_RING(ring
, 0x40000000);
426 OUT_RING(ring
, 0x3f400000);
427 OUT_RING(ring
, 0x3ec00000);
428 OUT_RING(ring
, 0x3e800000);
430 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
431 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_MASK
));
432 OUT_RING(ring
, A2XX_RB_COLOR_MASK_WRITE_RED
|
433 A2XX_RB_COLOR_MASK_WRITE_GREEN
|
434 A2XX_RB_COLOR_MASK_WRITE_BLUE
|
435 A2XX_RB_COLOR_MASK_WRITE_ALPHA
);
437 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
438 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_RED
));
439 OUT_RING(ring
, 0x00000000); /* RB_BLEND_RED */
440 OUT_RING(ring
, 0x00000000); /* RB_BLEND_GREEN */
441 OUT_RING(ring
, 0x00000000); /* RB_BLEND_BLUE */
442 OUT_RING(ring
, 0x000000ff); /* RB_BLEND_ALPHA */
446 fd2_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
448 __OUT_IB(ring
, false, target
);
452 fd2_emit_init(struct pipe_context
*pctx
)
454 struct fd_context
*ctx
= fd_context(pctx
);
455 ctx
->emit_ib
= fd2_emit_ib
;