src/gallium/drivers/freedreno/a2xx/fd2_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33
  34 #include "freedreno_draw.h"
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd2_gmem.h"
  39 #include "fd2_context.h"
  40 #include "fd2_emit.h"
  41 #include "fd2_program.h"
  42 #include "fd2_util.h"
  43 #include "fd2_zsa.h"
  44
  45 static uint32_t fmt2swap(enum pipe_format format)
  46 {
  47         switch (format) {
  48         case PIPE_FORMAT_B8G8R8A8_UNORM:
  49         case PIPE_FORMAT_B8G8R8X8_UNORM:
  50         case PIPE_FORMAT_B5G6R5_UNORM:
  51         case PIPE_FORMAT_B5G5R5A1_UNORM:
  52         case PIPE_FORMAT_B5G5R5X1_UNORM:
  53         case PIPE_FORMAT_B4G4R4A4_UNORM:
  54         case PIPE_FORMAT_B4G4R4X4_UNORM:
  55         /* TODO probably some more.. */
  56                 return 1;
  57         default:
  58                 return 0;
  59         }
  60 }
  61
  62 /* transfer from gmem to system memory (ie. normal RAM) */
  63
  64 static void
  65 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
  66                 struct pipe_surface *psurf)
  67 {
  68         struct fd_ringbuffer *ring = batch->gmem;
  69         struct fd_resource *rsc = fd_resource(psurf->texture);
  70         uint32_t swap = fmt2swap(psurf->format);
  71
  72         if (!rsc->valid)
  73                 return;
  74
  75         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  76         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
  77         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
  78                         A2XX_RB_COLOR_INFO_BASE(base) |
  79                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
  80
  81         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
  82         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
  83         OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
  84         OUT_RELOCW(ring, rsc->bo, 0, 0, 0);     /* RB_COPY_DEST_BASE */
  85         OUT_RING(ring, rsc->slices[0].pitch >> 5); /* RB_COPY_DEST_PITCH */
  86         OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
  87                         A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
  88                         A2XX_RB_COPY_DEST_INFO_LINEAR |
  89                         A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
  90                         A2XX_RB_COPY_DEST_INFO_WRITE_RED |
  91                         A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
  92                         A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
  93                         A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
  94
  95         if (!is_a20x(batch->ctx->screen)) {
  96                 OUT_WFI (ring);
  97
  98                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  99                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 100                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 101                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 102         }
 103
 104         fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 105                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 106 }
 107
 108 static void
 109 fd2_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 110 {
 111         struct fd_context *ctx = batch->ctx;
 112         struct fd2_context *fd2_ctx = fd2_context(ctx);
 113         struct fd_ringbuffer *ring = batch->gmem;
 114         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 115
 116         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 117                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 118                 }, 1);
 119
 120         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 121         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 122         OUT_RING(ring, 0x00000000);          /* PA_SC_WINDOW_OFFSET */
 123
 124         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 125         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 126         OUT_RING(ring, 0);
 127
 128         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 129         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 130         OUT_RING(ring, 0x0000028f);
 131
 132         fd2_program_emit(ring, &ctx->solid_prog);
 133
 134         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 135         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 136         OUT_RING(ring, 0x0000ffff);
 137
 138         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 139         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 140         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 141
 142         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 143         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 144         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 145                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 146                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 147
 148         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 149         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 150         OUT_RING(ring, xy2d(0, 0));                       /* PA_SC_WINDOW_SCISSOR_TL */
 151         OUT_RING(ring, xy2d(pfb->width, pfb->height));    /* PA_SC_WINDOW_SCISSOR_BR */
 152
 153         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 154         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 155         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
 156                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 157                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 158                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 159                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 160
 161         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 162         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 163         OUT_RING(ring, 0x00000000);
 164
 165         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 166         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 167         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
 168
 169         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 170         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
 171         OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(tile->xoff) |
 172                         A2XX_RB_COPY_DEST_OFFSET_Y(tile->yoff));
 173
 174         if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 175                 emit_gmem2mem_surf(batch, tile->bin_w * tile->bin_h, pfb->zsbuf);
 176
 177         if (batch->resolve & FD_BUFFER_COLOR)
 178                 emit_gmem2mem_surf(batch, 0, pfb->cbufs[0]);
 179
 180         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 181         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 182         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 183 }
 184
 185 /* transfer from system memory to gmem */
 186
 187 static void
 188 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
 189                 struct pipe_surface *psurf)
 190 {
 191         struct fd_ringbuffer *ring = batch->gmem;
 192         struct fd_resource *rsc = fd_resource(psurf->texture);
 193         uint32_t swiz;
 194
 195         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 196         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 197         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
 198                         A2XX_RB_COLOR_INFO_BASE(base) |
 199                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
 200
 201         swiz = fd2_tex_swiz(psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
 202                         PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
 203
 204         /* emit fb as a texture: */
 205         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 206         OUT_RING(ring, 0x00010000);
 207         OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
 208                         A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
 209                         A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
 210                         A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch));
 211         OUT_RELOC(ring, rsc->bo, 0,
 212                         fd2_pipe2surface(psurf->format) | 0x800, 0);
 213         OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
 214                         A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
 215         OUT_RING(ring, 0x01000000 | // XXX
 216                         swiz |
 217                         A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
 218                         A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
 219         OUT_RING(ring, 0x00000000);
 220         OUT_RING(ring, 0x00000200);
 221
 222         if (!is_a20x(batch->ctx->screen)) {
 223                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 224                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 225                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 226                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 227         }
 228
 229         fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 230                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 231 }
 232
 233 static void
 234 fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 235 {
 236         struct fd_context *ctx = batch->ctx;
 237         struct fd2_context *fd2_ctx = fd2_context(ctx);
 238         struct fd_ringbuffer *ring = batch->gmem;
 239         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 240         unsigned bin_w = tile->bin_w;
 241         unsigned bin_h = tile->bin_h;
 242         float x0, y0, x1, y1;
 243
 244         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 245                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
 246                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
 247                 }, 2);
 248
 249         /* write texture coordinates to vertexbuf: */
 250         x0 = ((float)tile->xoff) / ((float)pfb->width);
 251         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 252         y0 = ((float)tile->yoff) / ((float)pfb->height);
 253         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 254         OUT_PKT3(ring, CP_MEM_WRITE, 9);
 255         OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0, 0);
 256         OUT_RING(ring, fui(x0));
 257         OUT_RING(ring, fui(y0));
 258         OUT_RING(ring, fui(x1));
 259         OUT_RING(ring, fui(y0));
 260         OUT_RING(ring, fui(x0));
 261         OUT_RING(ring, fui(y1));
 262         OUT_RING(ring, fui(x1));
 263         OUT_RING(ring, fui(y1));
 264
 265         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 266         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 267         OUT_RING(ring, 0);
 268
 269         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 270         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 271         OUT_RING(ring, 0x0000003b);
 272
 273         fd2_program_emit(ring, &ctx->blit_prog[0]);
 274
 275         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 276         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 277
 278         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 279         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 280         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 281
 282         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 283         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 284         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
 285                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 286                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 287
 288         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 289         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 290         OUT_RING(ring, 0x0000ffff);
 291
 292         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 293         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 294         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
 295                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 296                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 297                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 298                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 299
 300         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 301         OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
 302         OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
 303                         A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND2_DST_PLUS_SRC) |
 304                         A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
 305                         A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
 306                         A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND2_DST_PLUS_SRC) |
 307                         A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
 308
 309         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 310         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 311         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
 312                         xy2d(0,0));                     /* PA_SC_WINDOW_SCISSOR_TL */
 313         OUT_RING(ring, xy2d(bin_w, bin_h));     /* PA_SC_WINDOW_SCISSOR_BR */
 314
 315         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 316         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
 317         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XSCALE */
 318         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XOFFSET */
 319         OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
 320         OUT_RING(ring, fui((float)bin_h/2.0));  /* PA_CL_VPORT_YOFFSET */
 321
 322         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 323         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 324         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
 325                         A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT |       // XXX check this???
 326                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 327                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 328                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 329                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 330
 331         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 332         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 333         OUT_RING(ring, 0x00000000);
 334
 335         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 336                 emit_mem2gmem_surf(batch, bin_w * bin_h, pfb->zsbuf);
 337
 338         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR))
 339                 emit_mem2gmem_surf(batch, 0, pfb->cbufs[0]);
 340
 341         /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
 342 }
 343
 344 /* before first tile */
 345 static void
 346 fd2_emit_tile_init(struct fd_batch *batch)
 347 {
 348         struct fd_context *ctx = batch->ctx;
 349         struct fd_ringbuffer *ring = batch->gmem;
 350         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 351         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 352         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 353         uint32_t reg;
 354
 355         fd2_emit_restore(ctx, ring);
 356
 357         OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 358         OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
 359         OUT_RING(ring, gmem->bin_w);                 /* RB_SURFACE_INFO */
 360         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 361                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 362         reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
 363         if (pfb->zsbuf)
 364                 reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 365         OUT_RING(ring, reg);                         /* RB_DEPTH_INFO */
 366 }
 367
 368 /* before mem2gmem */
 369 static void
 370 fd2_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 371 {
 372         struct fd_ringbuffer *ring = batch->gmem;
 373         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 374         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 375
 376         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 377         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 378         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
 379                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 380
 381         /* setup screen scissor for current tile (same for mem2gmem): */
 382         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 383         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
 384         OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_TL_X(0) |
 385                         A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(0));
 386         OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_BR_X(tile->bin_w) |
 387                         A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(tile->bin_h));
 388 }
 389
 390 /* before IB to rendering cmds: */
 391 static void
 392 fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 393 {
 394         struct fd_ringbuffer *ring = batch->gmem;
 395         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 396         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 397
 398         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 399         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 400         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 401                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 402
 403         /* setup window scissor and offset for current tile (different
 404          * from mem2gmem):
 405          */
 406         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 407         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 408         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-tile->xoff) |
 409                         A2XX_PA_SC_WINDOW_OFFSET_Y(-tile->yoff));
 410 }
 411
 412 void
 413 fd2_gmem_init(struct pipe_context *pctx)
 414 {
 415         struct fd_context *ctx = fd_context(pctx);
 416
 417         ctx->emit_tile_init = fd2_emit_tile_init;
 418         ctx->emit_tile_prep = fd2_emit_tile_prep;
 419         ctx->emit_tile_mem2gmem = fd2_emit_tile_mem2gmem;
 420         ctx->emit_tile_renderprep = fd2_emit_tile_renderprep;
 421         ctx->emit_tile_gmem2mem = fd2_emit_tile_gmem2mem;
 422 }