src/gallium/drivers/freedreno/a2xx/fd2_gmem.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_inlines.h"
  31
  32 #include "freedreno_draw.h"
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd2_gmem.h"
  37 #include "fd2_context.h"
  38 #include "fd2_emit.h"
  39 #include "fd2_program.h"
  40 #include "fd2_util.h"
  41 #include "fd2_zsa.h"
  42
  43 static uint32_t fmt2swap(enum pipe_format format)
  44 {
  45         switch (format) {
  46         case PIPE_FORMAT_B8G8R8A8_UNORM:
  47         case PIPE_FORMAT_B8G8R8X8_UNORM:
  48         case PIPE_FORMAT_B5G6R5_UNORM:
  49         case PIPE_FORMAT_B5G5R5A1_UNORM:
  50         case PIPE_FORMAT_B5G5R5X1_UNORM:
  51         case PIPE_FORMAT_B4G4R4A4_UNORM:
  52         case PIPE_FORMAT_B4G4R4X4_UNORM:
  53         /* TODO probably some more.. */
  54                 return 1;
  55         default:
  56                 return 0;
  57         }
  58 }
  59
  60 /* transfer from gmem to system memory (ie. normal RAM) */
  61
  62 static void
  63 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
  64                 struct pipe_surface *psurf)
  65 {
  66         struct fd_ringbuffer *ring = batch->gmem;
  67         struct fd_resource *rsc = fd_resource(psurf->texture);
  68         uint32_t swap = fmt2swap(psurf->format);
  69         struct fd_resource_slice *slice =
  70                 fd_resource_slice(rsc, psurf->u.tex.level);
  71         uint32_t offset =
  72                 fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
  73
  74         assert((slice->pitch & 31) == 0);
  75         assert((offset & 0xfff) == 0);
  76
  77         if (!rsc->valid)
  78                 return;
  79
  80         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  81         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
  82         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
  83                         A2XX_RB_COLOR_INFO_BASE(base) |
  84                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
  85
  86         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
  87         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
  88         OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
  89         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);     /* RB_COPY_DEST_BASE */
  90         OUT_RING(ring, slice->pitch >> 5); /* RB_COPY_DEST_PITCH */
  91         OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
  92                         A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
  93                         A2XX_RB_COPY_DEST_INFO_LINEAR |
  94                         A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
  95                         A2XX_RB_COPY_DEST_INFO_WRITE_RED |
  96                         A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
  97                         A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
  98                         A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
  99
 100         if (!is_a20x(batch->ctx->screen)) {
 101                 OUT_WFI (ring);
 102
 103                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 104                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 105                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 106                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 107         }
 108
 109         fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 110                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 111 }
 112
 113 static void
 114 fd2_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 115 {
 116         struct fd_context *ctx = batch->ctx;
 117         struct fd2_context *fd2_ctx = fd2_context(ctx);
 118         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 119         struct fd_ringbuffer *ring = batch->gmem;
 120         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 121
 122         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 123                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 124                 }, 1);
 125
 126         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 127         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 128         OUT_RING(ring, 0x00000000);          /* PA_SC_WINDOW_OFFSET */
 129
 130         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 131         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 132         OUT_RING(ring, 0);
 133
 134         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 135         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 136         OUT_RING(ring, 0x0000028f);
 137
 138         fd2_program_emit(ring, &ctx->solid_prog);
 139
 140         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 141         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 142         OUT_RING(ring, 0x0000ffff);
 143
 144         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 145         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 146         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 147
 148         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 149         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 150         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 151                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 152                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 153
 154         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 155         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 156         OUT_RING(ring, xy2d(0, 0));                       /* PA_SC_WINDOW_SCISSOR_TL */
 157         OUT_RING(ring, xy2d(pfb->width, pfb->height));    /* PA_SC_WINDOW_SCISSOR_BR */
 158
 159         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 160         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 161         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
 162                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 163                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 164                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 165                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 166
 167         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 168         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 169         OUT_RING(ring, 0x00000000);
 170
 171         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 172         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 173         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
 174
 175         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 176         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
 177         OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(tile->xoff) |
 178                         A2XX_RB_COPY_DEST_OFFSET_Y(tile->yoff));
 179
 180         if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 181                 emit_gmem2mem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf);
 182
 183         if (batch->resolve & FD_BUFFER_COLOR)
 184                 emit_gmem2mem_surf(batch, gmem->cbuf_base[0], pfb->cbufs[0]);
 185
 186         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 187         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 188         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 189 }
 190
 191 /* transfer from system memory to gmem */
 192
 193 static void
 194 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
 195                 struct pipe_surface *psurf)
 196 {
 197         struct fd_ringbuffer *ring = batch->gmem;
 198         struct fd_resource *rsc = fd_resource(psurf->texture);
 199         struct fd_resource_slice *slice =
 200                 fd_resource_slice(rsc, psurf->u.tex.level);
 201         uint32_t offset =
 202                 fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
 203         uint32_t swiz;
 204
 205         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 206         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 207         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
 208                         A2XX_RB_COLOR_INFO_BASE(base) |
 209                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
 210
 211         swiz = fd2_tex_swiz(psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
 212                         PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
 213
 214         /* emit fb as a texture: */
 215         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 216         OUT_RING(ring, 0x00010000);
 217         OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
 218                         A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
 219                         A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
 220                         A2XX_SQ_TEX_0_PITCH(slice->pitch));
 221         OUT_RELOC(ring, rsc->bo, offset,
 222                         fd2_pipe2surface(psurf->format) |
 223                         A2XX_SQ_TEX_1_CLAMP_POLICY(SQ_TEX_CLAMP_POLICY_OGL), 0);
 224         OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
 225                         A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
 226         OUT_RING(ring, A2XX_SQ_TEX_3_MIP_FILTER(SQ_TEX_FILTER_BASEMAP) |
 227                         swiz |
 228                         A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
 229                         A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
 230         OUT_RING(ring, 0x00000000);
 231         OUT_RING(ring, A2XX_SQ_TEX_5_DIMENSION(SQ_TEX_DIMENSION_2D));
 232
 233         if (!is_a20x(batch->ctx->screen)) {
 234                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 235                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 236                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 237                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 238         }
 239
 240         fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 241                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 242 }
 243
 244 static void
 245 fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 246 {
 247         struct fd_context *ctx = batch->ctx;
 248         struct fd2_context *fd2_ctx = fd2_context(ctx);
 249         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 250         struct fd_ringbuffer *ring = batch->gmem;
 251         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 252         unsigned bin_w = tile->bin_w;
 253         unsigned bin_h = tile->bin_h;
 254         float x0, y0, x1, y1;
 255
 256         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 257                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
 258                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
 259                 }, 2);
 260
 261         /* write texture coordinates to vertexbuf: */
 262         x0 = ((float)tile->xoff) / ((float)pfb->width);
 263         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 264         y0 = ((float)tile->yoff) / ((float)pfb->height);
 265         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 266         OUT_PKT3(ring, CP_MEM_WRITE, 9);
 267         OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0, 0);
 268         OUT_RING(ring, fui(x0));
 269         OUT_RING(ring, fui(y0));
 270         OUT_RING(ring, fui(x1));
 271         OUT_RING(ring, fui(y0));
 272         OUT_RING(ring, fui(x0));
 273         OUT_RING(ring, fui(y1));
 274         OUT_RING(ring, fui(x1));
 275         OUT_RING(ring, fui(y1));
 276
 277         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 278         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 279         OUT_RING(ring, 0);
 280
 281         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 282         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 283         OUT_RING(ring, 0x0000003b);
 284
 285         fd2_program_emit(ring, &ctx->blit_prog[0]);
 286
 287         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 288         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 289
 290         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 291         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 292         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 293
 294         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 295         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 296         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
 297                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 298                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 299
 300         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 301         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 302         OUT_RING(ring, 0x0000ffff);
 303
 304         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 305         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 306         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
 307                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 308                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 309                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 310                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 311
 312         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 313         OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
 314         OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
 315                         A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND2_DST_PLUS_SRC) |
 316                         A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
 317                         A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
 318                         A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND2_DST_PLUS_SRC) |
 319                         A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
 320
 321         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 322         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 323         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
 324                         xy2d(0,0));                     /* PA_SC_WINDOW_SCISSOR_TL */
 325         OUT_RING(ring, xy2d(bin_w, bin_h));     /* PA_SC_WINDOW_SCISSOR_BR */
 326
 327         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 328         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
 329         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XSCALE */
 330         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XOFFSET */
 331         OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
 332         OUT_RING(ring, fui((float)bin_h/2.0));  /* PA_CL_VPORT_YOFFSET */
 333
 334         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 335         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 336         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
 337                         A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT |       // XXX check this???
 338                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 339                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 340                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 341                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 342
 343         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 344         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 345         OUT_RING(ring, 0x00000000);
 346
 347         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 348                 emit_mem2gmem_surf(batch, gmem->zsbuf_base[0], pfb->zsbuf);
 349
 350         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR))
 351                 emit_mem2gmem_surf(batch, gmem->cbuf_base[0], pfb->cbufs[0]);
 352
 353         /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
 354 }
 355
 356 /* before first tile */
 357 static void
 358 fd2_emit_tile_init(struct fd_batch *batch)
 359 {
 360         struct fd_context *ctx = batch->ctx;
 361         struct fd_ringbuffer *ring = batch->gmem;
 362         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 363         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 364         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 365         uint32_t reg;
 366
 367         fd2_emit_restore(ctx, ring);
 368
 369         OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 370         OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
 371         OUT_RING(ring, gmem->bin_w);                 /* RB_SURFACE_INFO */
 372         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 373                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 374         reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]);
 375         if (pfb->zsbuf)
 376                 reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 377         OUT_RING(ring, reg);                         /* RB_DEPTH_INFO */
 378 }
 379
 380 /* before mem2gmem */
 381 static void
 382 fd2_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 383 {
 384         struct fd_ringbuffer *ring = batch->gmem;
 385         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 386         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 387
 388         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 389         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 390         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
 391                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 392
 393         /* setup screen scissor for current tile (same for mem2gmem): */
 394         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 395         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
 396         OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_TL_X(0) |
 397                         A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(0));
 398         OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_BR_X(tile->bin_w) |
 399                         A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(tile->bin_h));
 400 }
 401
 402 /* before IB to rendering cmds: */
 403 static void
 404 fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 405 {
 406         struct fd_ringbuffer *ring = batch->gmem;
 407         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 408         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 409
 410         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 411         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 412         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 413                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 414
 415         /* setup window scissor and offset for current tile (different
 416          * from mem2gmem):
 417          */
 418         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 419         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 420         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-tile->xoff) |
 421                         A2XX_PA_SC_WINDOW_OFFSET_Y(-tile->yoff));
 422 }
 423
 424 void
 425 fd2_gmem_init(struct pipe_context *pctx)
 426 {
 427         struct fd_context *ctx = fd_context(pctx);
 428
 429         ctx->emit_tile_init = fd2_emit_tile_init;
 430         ctx->emit_tile_prep = fd2_emit_tile_prep;
 431         ctx->emit_tile_mem2gmem = fd2_emit_tile_mem2gmem;
 432         ctx->emit_tile_renderprep = fd2_emit_tile_renderprep;
 433         ctx->emit_tile_gmem2mem = fd2_emit_tile_gmem2mem;
 434 }