src/gallium/drivers/freedreno/a2xx/fd2_gmem.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33
  34 #include "freedreno_draw.h"
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd2_gmem.h"
  39 #include "fd2_context.h"
  40 #include "fd2_emit.h"
  41 #include "fd2_program.h"
  42 #include "fd2_util.h"
  43 #include "fd2_zsa.h"
  44
  45 static uint32_t fmt2swap(enum pipe_format format)
  46 {
  47         switch (format) {
  48         case PIPE_FORMAT_B8G8R8A8_UNORM:
  49         /* TODO probably some more.. */
  50                 return 1;
  51         default:
  52                 return 0;
  53         }
  54 }
  55
  56 /* transfer from gmem to system memory (ie. normal RAM) */
  57
  58 static void
  59 emit_gmem2mem_surf(struct fd_context *ctx, uint32_t base,
  60                 struct pipe_surface *psurf)
  61 {
  62         struct fd_ringbuffer *ring = ctx->ring;
  63         struct fd_resource *rsc = fd_resource(psurf->texture);
  64         uint32_t swap = fmt2swap(psurf->format);
  65
  66         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  67         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
  68         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
  69                         A2XX_RB_COLOR_INFO_BASE(base) |
  70                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
  71
  72         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
  73         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
  74         OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
  75         OUT_RELOCW(ring, rsc->bo, 0, 0, 0);     /* RB_COPY_DEST_BASE */
  76         OUT_RING(ring, rsc->slices[0].pitch >> 5); /* RB_COPY_DEST_PITCH */
  77         OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
  78                         A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
  79                         A2XX_RB_COPY_DEST_INFO_LINEAR |
  80                         A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
  81                         A2XX_RB_COPY_DEST_INFO_WRITE_RED |
  82                         A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
  83                         A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
  84                         A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
  85
  86         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
  87         OUT_RING(ring, 0x0000000);
  88
  89         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  90         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
  91         OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
  92         OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
  93
  94         fd_draw(ctx, DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX, 3,
  95                         INDEX_SIZE_IGN, 0, 0, NULL);
  96 }
  97
  98 static void
  99 fd2_emit_tile_gmem2mem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 100                 uint32_t bin_w, uint32_t bin_h)
 101 {
 102         struct fd2_context *fd2_ctx = fd2_context(ctx);
 103         struct fd_ringbuffer *ring = ctx->ring;
 104         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 105
 106         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 107                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 108                 }, 1);
 109
 110         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 111         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 112         OUT_RING(ring, 0x00000000);          /* PA_SC_WINDOW_OFFSET */
 113
 114         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 115         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 116         OUT_RING(ring, 0);
 117
 118         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 119         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 120         OUT_RING(ring, 0x0000028f);
 121
 122         fd2_program_emit(ring, &ctx->solid_prog);
 123
 124         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 125         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 126         OUT_RING(ring, 0x0000ffff);
 127
 128         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 129         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 130         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 131
 132         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 133         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 134         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 135                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 136                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 137
 138         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 139         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 140         OUT_RING(ring, xy2d(0, 0));                       /* PA_SC_WINDOW_SCISSOR_TL */
 141         OUT_RING(ring, xy2d(pfb->width, pfb->height));    /* PA_SC_WINDOW_SCISSOR_BR */
 142
 143         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 144         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 145         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
 146                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 147                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 148                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 149                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 150
 151         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 152         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 153         OUT_RING(ring, 0x00000000);
 154
 155         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 156         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 157         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
 158
 159         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 160         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
 161         OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(xoff) |
 162                         A2XX_RB_COPY_DEST_OFFSET_Y(yoff));
 163
 164         if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 165                 emit_gmem2mem_surf(ctx, bin_w * bin_h, pfb->zsbuf);
 166
 167         if (ctx->resolve & FD_BUFFER_COLOR)
 168                 emit_gmem2mem_surf(ctx, 0, pfb->cbufs[0]);
 169
 170         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 171         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 172         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 173 }
 174
 175 /* transfer from system memory to gmem */
 176
 177 static void
 178 emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base,
 179                 struct pipe_surface *psurf)
 180 {
 181         struct fd_ringbuffer *ring = ctx->ring;
 182         struct fd_resource *rsc = fd_resource(psurf->texture);
 183         uint32_t swiz;
 184
 185         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 186         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 187         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
 188                         A2XX_RB_COLOR_INFO_BASE(base) |
 189                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
 190
 191         swiz = fd2_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
 192                         PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA);
 193
 194         /* emit fb as a texture: */
 195         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 196         OUT_RING(ring, 0x00010000);
 197         OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
 198                         A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
 199                         A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
 200                         A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch));
 201         OUT_RELOC(ring, rsc->bo, 0,
 202                         fd2_pipe2surface(psurf->format) | 0x800, 0);
 203         OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
 204                         A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
 205         OUT_RING(ring, 0x01000000 | // XXX
 206                         swiz |
 207                         A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
 208                         A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
 209         OUT_RING(ring, 0x00000000);
 210         OUT_RING(ring, 0x00000200);
 211
 212         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 213         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 214         OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 215         OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 216
 217         fd_draw(ctx, DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX, 3,
 218                         INDEX_SIZE_IGN, 0, 0, NULL);
 219 }
 220
 221 static void
 222 fd2_emit_tile_mem2gmem(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 223                 uint32_t bin_w, uint32_t bin_h)
 224 {
 225         struct fd2_context *fd2_ctx = fd2_context(ctx);
 226         struct fd_ringbuffer *ring = ctx->ring;
 227         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 228         float x0, y0, x1, y1;
 229
 230         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 231                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
 232                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
 233                 }, 2);
 234
 235         /* write texture coordinates to vertexbuf: */
 236         x0 = ((float)xoff) / ((float)pfb->width);
 237         x1 = ((float)xoff + bin_w) / ((float)pfb->width);
 238         y0 = ((float)yoff) / ((float)pfb->height);
 239         y1 = ((float)yoff + bin_h) / ((float)pfb->height);
 240         OUT_PKT3(ring, CP_MEM_WRITE, 9);
 241         OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0, 0);
 242         OUT_RING(ring, fui(x0));
 243         OUT_RING(ring, fui(y0));
 244         OUT_RING(ring, fui(x1));
 245         OUT_RING(ring, fui(y0));
 246         OUT_RING(ring, fui(x0));
 247         OUT_RING(ring, fui(y1));
 248         OUT_RING(ring, fui(x1));
 249         OUT_RING(ring, fui(y1));
 250
 251         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 252         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 253         OUT_RING(ring, 0);
 254
 255         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 256         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 257         OUT_RING(ring, 0x0000003b);
 258
 259         fd2_program_emit(ring, &ctx->blit_prog);
 260
 261         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 262         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 263
 264         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 265         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 266         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 267
 268         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 269         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 270         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
 271                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 272                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 273
 274         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 275         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 276         OUT_RING(ring, 0x0000ffff);
 277
 278         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 279         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 280         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
 281                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 282                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 283                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 284                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 285
 286         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 287         OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
 288         OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
 289                         A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) |
 290                         A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
 291                         A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
 292                         A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) |
 293                         A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
 294
 295         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 296         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 297         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
 298                         xy2d(0,0));                     /* PA_SC_WINDOW_SCISSOR_TL */
 299         OUT_RING(ring, xy2d(bin_w, bin_h));     /* PA_SC_WINDOW_SCISSOR_BR */
 300
 301         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 302         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
 303         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XSCALE */
 304         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XOFFSET */
 305         OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
 306         OUT_RING(ring, fui((float)bin_h/2.0));  /* PA_CL_VPORT_YOFFSET */
 307
 308         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 309         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 310         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
 311                         A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT |       // XXX check this???
 312                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 313                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 314                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 315                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 316
 317         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 318         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 319         OUT_RING(ring, 0x00000000);
 320
 321         if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 322                 emit_mem2gmem_surf(ctx, bin_w * bin_h, pfb->zsbuf);
 323
 324         if (ctx->restore & FD_BUFFER_COLOR)
 325                 emit_mem2gmem_surf(ctx, 0, pfb->cbufs[0]);
 326
 327         /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
 328 }
 329
 330 /* before first tile */
 331 static void
 332 fd2_emit_tile_init(struct fd_context *ctx)
 333 {
 334         struct fd_ringbuffer *ring = ctx->ring;
 335         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 336         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 337         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 338         uint32_t reg;
 339
 340         OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 341         OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
 342         OUT_RING(ring, gmem->bin_w);                 /* RB_SURFACE_INFO */
 343         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 344                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 345         reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
 346         if (pfb->zsbuf)
 347                 reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 348         OUT_RING(ring, reg);                         /* RB_DEPTH_INFO */
 349 }
 350
 351 /* before mem2gmem */
 352 static void
 353 fd2_emit_tile_prep(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 354                 uint32_t bin_w, uint32_t bin_h)
 355 {
 356         struct fd_ringbuffer *ring = ctx->ring;
 357         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 358         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 359
 360         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 361         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 362         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
 363                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 364
 365         /* setup screen scissor for current tile (same for mem2gmem): */
 366         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 367         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
 368         OUT_RING(ring, xy2d(0,0));           /* PA_SC_SCREEN_SCISSOR_TL */
 369         OUT_RING(ring, xy2d(bin_w, bin_h));  /* PA_SC_SCREEN_SCISSOR_BR */
 370 }
 371
 372 /* before IB to rendering cmds: */
 373 static void
 374 fd2_emit_tile_renderprep(struct fd_context *ctx, uint32_t xoff, uint32_t yoff,
 375                 uint32_t bin_w, uint32_t bin_h)
 376 {
 377         struct fd_ringbuffer *ring = ctx->ring;
 378         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 379         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 380
 381         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 382         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 383         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 384                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 385
 386         /* setup window scissor and offset for current tile (different
 387          * from mem2gmem):
 388          */
 389         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 390         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 391         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff) |
 392                         A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff));
 393 }
 394
 395 void
 396 fd2_gmem_init(struct pipe_context *pctx)
 397 {
 398         struct fd_context *ctx = fd_context(pctx);
 399
 400         ctx->emit_tile_init = fd2_emit_tile_init;
 401         ctx->emit_tile_prep = fd2_emit_tile_prep;
 402         ctx->emit_tile_mem2gmem = fd2_emit_tile_mem2gmem;
 403         ctx->emit_tile_renderprep = fd2_emit_tile_renderprep;
 404         ctx->emit_tile_gmem2mem = fd2_emit_tile_gmem2mem;
 405 }