src/gallium/drivers/freedreno/a2xx/fd2_gmem.c

   1 /*
   2  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_inlines.h"
  31
  32 #include "freedreno_draw.h"
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd2_gmem.h"
  37 #include "fd2_context.h"
  38 #include "fd2_emit.h"
  39 #include "fd2_program.h"
  40 #include "fd2_util.h"
  41 #include "fd2_zsa.h"
  42
  43 static uint32_t fmt2swap(enum pipe_format format)
  44 {
  45         switch (format) {
  46         case PIPE_FORMAT_B8G8R8A8_UNORM:
  47         case PIPE_FORMAT_B8G8R8X8_UNORM:
  48         case PIPE_FORMAT_B5G6R5_UNORM:
  49         case PIPE_FORMAT_B5G5R5A1_UNORM:
  50         case PIPE_FORMAT_B5G5R5X1_UNORM:
  51         case PIPE_FORMAT_B4G4R4A4_UNORM:
  52         case PIPE_FORMAT_B4G4R4X4_UNORM:
  53         /* TODO probably some more.. */
  54                 return 1;
  55         default:
  56                 return 0;
  57         }
  58 }
  59
  60 /* transfer from gmem to system memory (ie. normal RAM) */
  61
  62 static void
  63 emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
  64                 struct pipe_surface *psurf)
  65 {
  66         struct fd_ringbuffer *ring = batch->gmem;
  67         struct fd_resource *rsc = fd_resource(psurf->texture);
  68         uint32_t swap = fmt2swap(psurf->format);
  69
  70         if (!rsc->valid)
  71                 return;
  72
  73         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  74         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
  75         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
  76                         A2XX_RB_COLOR_INFO_BASE(base) |
  77                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
  78
  79         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
  80         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
  81         OUT_RING(ring, 0x00000000);             /* RB_COPY_CONTROL */
  82         OUT_RELOCW(ring, rsc->bo, 0, 0, 0);     /* RB_COPY_DEST_BASE */
  83         OUT_RING(ring, rsc->slices[0].pitch >> 5); /* RB_COPY_DEST_PITCH */
  84         OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
  85                         A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(psurf->format)) |
  86                         A2XX_RB_COPY_DEST_INFO_LINEAR |
  87                         A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
  88                         A2XX_RB_COPY_DEST_INFO_WRITE_RED |
  89                         A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
  90                         A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
  91                         A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
  92
  93         if (!is_a20x(batch->ctx->screen)) {
  94                 OUT_WFI (ring);
  95
  96                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  97                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
  98                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
  99                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 100         }
 101
 102         fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 103                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 104 }
 105
 106 static void
 107 fd2_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 108 {
 109         struct fd_context *ctx = batch->ctx;
 110         struct fd2_context *fd2_ctx = fd2_context(ctx);
 111         struct fd_ringbuffer *ring = batch->gmem;
 112         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 113
 114         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 115                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
 116                 }, 1);
 117
 118         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 119         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 120         OUT_RING(ring, 0x00000000);          /* PA_SC_WINDOW_OFFSET */
 121
 122         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 123         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 124         OUT_RING(ring, 0);
 125
 126         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 127         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 128         OUT_RING(ring, 0x0000028f);
 129
 130         fd2_program_emit(ring, &ctx->solid_prog);
 131
 132         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 133         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 134         OUT_RING(ring, 0x0000ffff);
 135
 136         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 137         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 138         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 139
 140         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 141         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 142         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 143                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 144                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 145
 146         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 147         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 148         OUT_RING(ring, xy2d(0, 0));                       /* PA_SC_WINDOW_SCISSOR_TL */
 149         OUT_RING(ring, xy2d(pfb->width, pfb->height));    /* PA_SC_WINDOW_SCISSOR_BR */
 150
 151         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 152         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 153         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
 154                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 155                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 156                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 157                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 158
 159         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 160         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 161         OUT_RING(ring, 0x00000000);
 162
 163         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 164         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 165         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
 166
 167         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 168         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
 169         OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(tile->xoff) |
 170                         A2XX_RB_COPY_DEST_OFFSET_Y(tile->yoff));
 171
 172         if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 173                 emit_gmem2mem_surf(batch, tile->bin_w * tile->bin_h, pfb->zsbuf);
 174
 175         if (batch->resolve & FD_BUFFER_COLOR)
 176                 emit_gmem2mem_surf(batch, 0, pfb->cbufs[0]);
 177
 178         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 179         OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
 180         OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
 181 }
 182
 183 /* transfer from system memory to gmem */
 184
 185 static void
 186 emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
 187                 struct pipe_surface *psurf)
 188 {
 189         struct fd_ringbuffer *ring = batch->gmem;
 190         struct fd_resource *rsc = fd_resource(psurf->texture);
 191         uint32_t swiz;
 192
 193         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 194         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 195         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
 196                         A2XX_RB_COLOR_INFO_BASE(base) |
 197                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)));
 198
 199         swiz = fd2_tex_swiz(psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
 200                         PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
 201
 202         /* emit fb as a texture: */
 203         OUT_PKT3(ring, CP_SET_CONSTANT, 7);
 204         OUT_RING(ring, 0x00010000);
 205         OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
 206                         A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
 207                         A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
 208                         A2XX_SQ_TEX_0_PITCH(rsc->slices[0].pitch));
 209         OUT_RELOC(ring, rsc->bo, 0,
 210                         fd2_pipe2surface(psurf->format) | 0x800, 0);
 211         OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
 212                         A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
 213         OUT_RING(ring, 0x01000000 | // XXX
 214                         swiz |
 215                         A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
 216                         A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
 217         OUT_RING(ring, 0x00000000);
 218         OUT_RING(ring, 0x00000200);
 219
 220         if (!is_a20x(batch->ctx->screen)) {
 221                 OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 222                 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
 223                 OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
 224                 OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
 225         }
 226
 227         fd_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 228                         DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 229 }
 230
 231 static void
 232 fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 233 {
 234         struct fd_context *ctx = batch->ctx;
 235         struct fd2_context *fd2_ctx = fd2_context(ctx);
 236         struct fd_ringbuffer *ring = batch->gmem;
 237         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 238         unsigned bin_w = tile->bin_w;
 239         unsigned bin_h = tile->bin_h;
 240         float x0, y0, x1, y1;
 241
 242         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
 243                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
 244                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
 245                 }, 2);
 246
 247         /* write texture coordinates to vertexbuf: */
 248         x0 = ((float)tile->xoff) / ((float)pfb->width);
 249         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 250         y0 = ((float)tile->yoff) / ((float)pfb->height);
 251         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 252         OUT_PKT3(ring, CP_MEM_WRITE, 9);
 253         OUT_RELOC(ring, fd_resource(fd2_ctx->solid_vertexbuf)->bo, 0x60, 0, 0);
 254         OUT_RING(ring, fui(x0));
 255         OUT_RING(ring, fui(y0));
 256         OUT_RING(ring, fui(x1));
 257         OUT_RING(ring, fui(y0));
 258         OUT_RING(ring, fui(x0));
 259         OUT_RING(ring, fui(y1));
 260         OUT_RING(ring, fui(x1));
 261         OUT_RING(ring, fui(y1));
 262
 263         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 264         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
 265         OUT_RING(ring, 0);
 266
 267         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 268         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
 269         OUT_RING(ring, 0x0000003b);
 270
 271         fd2_program_emit(ring, &ctx->blit_prog[0]);
 272
 273         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
 274         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
 275
 276         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 277         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
 278         OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
 279
 280         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 281         OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
 282         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
 283                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 284                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
 285
 286         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 287         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
 288         OUT_RING(ring, 0x0000ffff);
 289
 290         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 291         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
 292         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
 293                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
 294                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
 295                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
 296                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
 297
 298         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 299         OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
 300         OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
 301                         A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND2_DST_PLUS_SRC) |
 302                         A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
 303                         A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
 304                         A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND2_DST_PLUS_SRC) |
 305                         A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
 306
 307         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 308         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
 309         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
 310                         xy2d(0,0));                     /* PA_SC_WINDOW_SCISSOR_TL */
 311         OUT_RING(ring, xy2d(bin_w, bin_h));     /* PA_SC_WINDOW_SCISSOR_BR */
 312
 313         OUT_PKT3(ring, CP_SET_CONSTANT, 5);
 314         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
 315         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XSCALE */
 316         OUT_RING(ring, fui((float)bin_w/2.0));  /* PA_CL_VPORT_XOFFSET */
 317         OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
 318         OUT_RING(ring, fui((float)bin_h/2.0));  /* PA_CL_VPORT_YOFFSET */
 319
 320         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 321         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
 322         OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
 323                         A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT |       // XXX check this???
 324                         A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
 325                         A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
 326                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
 327                         A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
 328
 329         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 330         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
 331         OUT_RING(ring, 0x00000000);
 332
 333         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
 334                 emit_mem2gmem_surf(batch, bin_w * bin_h, pfb->zsbuf);
 335
 336         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR))
 337                 emit_mem2gmem_surf(batch, 0, pfb->cbufs[0]);
 338
 339         /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
 340 }
 341
 342 /* before first tile */
 343 static void
 344 fd2_emit_tile_init(struct fd_batch *batch)
 345 {
 346         struct fd_context *ctx = batch->ctx;
 347         struct fd_ringbuffer *ring = batch->gmem;
 348         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 349         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 350         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 351         uint32_t reg;
 352
 353         fd2_emit_restore(ctx, ring);
 354
 355         OUT_PKT3(ring, CP_SET_CONSTANT, 4);
 356         OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
 357         OUT_RING(ring, gmem->bin_w);                 /* RB_SURFACE_INFO */
 358         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 359                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 360         reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
 361         if (pfb->zsbuf)
 362                 reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
 363         OUT_RING(ring, reg);                         /* RB_DEPTH_INFO */
 364 }
 365
 366 /* before mem2gmem */
 367 static void
 368 fd2_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 369 {
 370         struct fd_ringbuffer *ring = batch->gmem;
 371         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 372         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 373
 374         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 375         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 376         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
 377                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 378
 379         /* setup screen scissor for current tile (same for mem2gmem): */
 380         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 381         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
 382         OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_TL_X(0) |
 383                         A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(0));
 384         OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_BR_X(tile->bin_w) |
 385                         A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(tile->bin_h));
 386 }
 387
 388 /* before IB to rendering cmds: */
 389 static void
 390 fd2_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 391 {
 392         struct fd_ringbuffer *ring = batch->gmem;
 393         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 394         enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
 395
 396         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 397         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 398         OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(format)) |
 399                         A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(format)));
 400
 401         /* setup window scissor and offset for current tile (different
 402          * from mem2gmem):
 403          */
 404         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 405         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
 406         OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-tile->xoff) |
 407                         A2XX_PA_SC_WINDOW_OFFSET_Y(-tile->yoff));
 408 }
 409
 410 void
 411 fd2_gmem_init(struct pipe_context *pctx)
 412 {
 413         struct fd_context *ctx = fd_context(pctx);
 414
 415         ctx->emit_tile_init = fd2_emit_tile_init;
 416         ctx->emit_tile_prep = fd2_emit_tile_prep;
 417         ctx->emit_tile_mem2gmem = fd2_emit_tile_mem2gmem;
 418         ctx->emit_tile_renderprep = fd2_emit_tile_renderprep;
 419         ctx->emit_tile_gmem2mem = fd2_emit_tile_gmem2mem;
 420 }