4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9009 bytes, from 2014-01-11 16:56:35)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 56545 bytes, from 2014-02-26 16:32:11)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
19 Copyright (C) 2013-2014 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 enum a3xx_render_mode
{
45 RB_RENDERING_PASS
= 0,
55 enum a3xx_threadmode
{
60 enum a3xx_instrbuffermode
{
64 enum a3xx_threadsize
{
69 enum a3xx_state_block_id
{
70 HLSQ_BLOCK_ID_TP_TEX
= 2,
71 HLSQ_BLOCK_ID_TP_MIPMAP
= 3,
72 HLSQ_BLOCK_ID_SP_VS
= 4,
73 HLSQ_BLOCK_ID_SP_FS
= 6,
76 enum a3xx_cache_opcode
{
83 VFMT_FLOAT_32_32_32
= 2,
84 VFMT_FLOAT_32_32_32_32
= 3,
87 VFMT_FLOAT_16_16_16
= 6,
88 VFMT_FLOAT_16_16_16_16
= 7,
91 VFMT_FIXED_32_32_32
= 10,
92 VFMT_FIXED_32_32_32_32
= 11,
94 VFMT_SHORT_16_16
= 17,
95 VFMT_SHORT_16_16_16
= 18,
96 VFMT_SHORT_16_16_16_16
= 19,
98 VFMT_USHORT_16_16
= 21,
99 VFMT_USHORT_16_16_16
= 22,
100 VFMT_USHORT_16_16_16_16
= 23,
101 VFMT_NORM_SHORT_16
= 24,
102 VFMT_NORM_SHORT_16_16
= 25,
103 VFMT_NORM_SHORT_16_16_16
= 26,
104 VFMT_NORM_SHORT_16_16_16_16
= 27,
105 VFMT_NORM_USHORT_16
= 28,
106 VFMT_NORM_USHORT_16_16
= 29,
107 VFMT_NORM_USHORT_16_16_16
= 30,
108 VFMT_NORM_USHORT_16_16_16_16
= 31,
111 VFMT_UBYTE_8_8_8
= 42,
112 VFMT_UBYTE_8_8_8_8
= 43,
113 VFMT_NORM_UBYTE_8
= 44,
114 VFMT_NORM_UBYTE_8_8
= 45,
115 VFMT_NORM_UBYTE_8_8_8
= 46,
116 VFMT_NORM_UBYTE_8_8_8_8
= 47,
119 VFMT_BYTE_8_8_8
= 50,
120 VFMT_BYTE_8_8_8_8
= 51,
121 VFMT_NORM_BYTE_8
= 52,
122 VFMT_NORM_BYTE_8_8
= 53,
123 VFMT_NORM_BYTE_8_8_8
= 54,
124 VFMT_NORM_BYTE_8_8_8_8
= 55,
125 VFMT_UINT_10_10_10_2
= 60,
126 VFMT_NORM_UINT_10_10_10_2
= 61,
127 VFMT_INT_10_10_10_2
= 62,
128 VFMT_NORM_INT_10_10_10_2
= 63,
132 TFMT_NORM_USHORT_565
= 4,
133 TFMT_NORM_USHORT_5551
= 6,
134 TFMT_NORM_USHORT_4444
= 7,
135 TFMT_NORM_UINT_X8Z24
= 10,
136 TFMT_NORM_UINT_NV12_UV_TILED
= 17,
137 TFMT_NORM_UINT_NV12_Y_TILED
= 19,
138 TFMT_NORM_UINT_NV12_UV
= 21,
139 TFMT_NORM_UINT_NV12_Y
= 23,
140 TFMT_NORM_UINT_I420_Y
= 24,
141 TFMT_NORM_UINT_I420_U
= 26,
142 TFMT_NORM_UINT_I420_V
= 27,
143 TFMT_NORM_UINT_2_10_10_10
= 41,
144 TFMT_NORM_UINT_A8
= 44,
145 TFMT_NORM_UINT_L8_A8
= 47,
146 TFMT_NORM_UINT_8
= 48,
147 TFMT_NORM_UINT_8_8
= 49,
148 TFMT_NORM_UINT_8_8_8
= 50,
149 TFMT_NORM_UINT_8_8_8_8
= 51,
151 TFMT_FLOAT_16_16
= 65,
152 TFMT_FLOAT_16_16_16_16
= 67,
154 TFMT_FLOAT_32_32
= 85,
155 TFMT_FLOAT_32_32_32_32
= 87,
158 enum a3xx_tex_fetchsize
{
167 enum a3xx_color_fmt
{
169 RB_R8G8B8A8_UNORM
= 8,
172 RB_R16G16B16A16_FLOAT
= 27,
173 RB_R32G32B32A32_FLOAT
= 51,
176 enum a3xx_color_swap
{
183 enum a3xx_msaa_samples
{
189 enum a3xx_sp_perfcounter_select
{
190 SP_FS_CFLOW_INSTRUCTIONS
= 12,
191 SP_FS_FULL_ALU_INSTRUCTIONS
= 14,
192 SP0_ICL1_MISSES
= 26,
193 SP_ALU_ACTIVE_CYCLES
= 29,
199 ROP_AND_INVERTED
= 2,
200 ROP_COPY_INVERTED
= 3,
208 ROP_OR_INVERTED
= 11,
215 enum adreno_rb_copy_control_mode
{
217 RB_COPY_DEPTH_STENCIL
= 5,
220 enum a3xx_tex_filter
{
221 A3XX_TEX_NEAREST
= 0,
225 enum a3xx_tex_clamp
{
227 A3XX_TEX_CLAMP_TO_EDGE
= 1,
228 A3XX_TEX_MIRROR_REPEAT
= 2,
229 A3XX_TEX_CLAMP_NONE
= 3,
248 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
249 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
250 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
251 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
252 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
253 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
254 #define A3XX_INT0_VFD_ERROR 0x00000040
255 #define A3XX_INT0_CP_SW_INT 0x00000080
256 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
257 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
258 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
259 #define A3XX_INT0_CP_HW_FAULT 0x00000800
260 #define A3XX_INT0_CP_DMA 0x00001000
261 #define A3XX_INT0_CP_IB2_INT 0x00002000
262 #define A3XX_INT0_CP_IB1_INT 0x00004000
263 #define A3XX_INT0_CP_RB_INT 0x00008000
264 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
265 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000
266 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000
267 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000
268 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
269 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
270 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000
271 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
272 #define REG_A3XX_RBBM_HW_VERSION 0x00000000
274 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001
276 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002
278 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010
280 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012
282 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018
284 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020
286 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021
288 #define REG_A3XX_RBBM_AHB_CMD 0x00000022
290 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027
292 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
294 #define REG_A3XX_RBBM_STATUS 0x00000030
295 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
296 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
297 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
298 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
299 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
300 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
301 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
302 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
303 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
304 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
305 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
306 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
307 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
308 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
309 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
310 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
311 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
312 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
313 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
314 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
315 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
317 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
319 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
321 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
323 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051
325 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054
327 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057
329 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
331 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
333 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
335 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063
337 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
339 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
341 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
343 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
345 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
347 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
349 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
351 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
353 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
355 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
357 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
359 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
361 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
363 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
365 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
367 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
369 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
371 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
373 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
375 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
377 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
379 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
381 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
383 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
385 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
387 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
389 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
391 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
393 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
395 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
397 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
399 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
401 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
403 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
405 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
407 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
409 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
411 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
413 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
415 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
417 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
419 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
421 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
423 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
425 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
427 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
429 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
431 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
433 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
435 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
437 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
439 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
441 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
443 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
445 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
447 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
449 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
451 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
453 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
455 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
457 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
459 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
461 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
463 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
465 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
467 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
469 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
471 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
473 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
475 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
477 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
479 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
481 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
483 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
485 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
487 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
489 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
491 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
493 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
495 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
497 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
499 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
501 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
503 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
505 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
507 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
509 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
511 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
513 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
515 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
517 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
519 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
521 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
523 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
525 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
527 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
529 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
531 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
533 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
535 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100
537 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
539 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
541 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9
543 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca
545 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc
547 #define REG_A3XX_CP_ROQ_DATA 0x000001cd
549 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1
551 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2
553 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3
555 #define REG_A3XX_CP_MEQ_ADDR 0x000001da
557 #define REG_A3XX_CP_MEQ_DATA 0x000001db
559 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
561 #define REG_A3XX_CP_HW_FAULT 0x0000045c
563 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
565 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
567 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
569 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
571 #define REG_A3XX_CP_AHB_FAULT 0x0000054d
573 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
574 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
575 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
576 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
577 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
578 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
579 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
580 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000
581 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000
582 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000
584 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
585 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
586 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
587 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val
)
589 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK
;
591 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
592 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
593 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val
)
595 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK
;
598 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048
599 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
600 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
601 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val
)
603 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK
;
606 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049
607 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
608 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
609 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val
)
611 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_XSCALE__MASK
;
614 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a
615 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
616 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
617 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val
)
619 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK
;
622 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b
623 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
624 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
625 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val
)
627 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_YSCALE__MASK
;
630 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c
631 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
632 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
633 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val
)
635 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK
;
638 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d
639 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
640 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
641 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val
)
643 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK
;
646 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
648 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
650 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
651 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
652 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
653 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val
)
655 return ((((uint32_t)(val
* 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK
;
658 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
659 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
660 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
661 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val
)
663 return ((((uint32_t)(val
* 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
666 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
667 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
668 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
669 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
670 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
671 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
672 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val
)
674 return ((((uint32_t)(val
* 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT
) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK
;
676 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
678 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072
679 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0
680 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4
681 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
683 return ((val
) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK
;
685 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00
686 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8
687 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val
)
689 return ((val
) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT
) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK
;
691 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
692 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
693 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val
)
695 return ((val
) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK
;
698 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074
699 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
700 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
701 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
702 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val
)
704 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
;
706 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
707 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
708 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val
)
710 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
;
713 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075
714 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
715 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
716 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
717 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val
)
719 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
;
721 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
722 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
723 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val
)
725 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
;
728 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079
729 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
730 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
731 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
732 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
734 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
;
736 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
737 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
738 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
740 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
;
743 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a
744 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
745 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
746 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
747 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
749 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
;
751 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
752 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
753 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
755 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
;
758 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0
759 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080
760 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700
761 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8
762 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
764 return ((val
) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT
) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK
;
766 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
767 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
769 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
770 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008
771 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
772 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
773 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val
)
775 return ((val
>> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT
) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK
;
777 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
778 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
779 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000
780 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
781 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
782 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
783 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
784 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
785 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
786 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val
)
788 return ((val
) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT
) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK
;
791 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
792 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
793 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000
794 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12
795 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val
)
797 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK
;
799 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000
800 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16
801 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val
)
803 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK
;
806 #define REG_A3XX_RB_ALPHA_REF 0x000020c3
807 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
808 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
809 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val
)
811 return ((val
) << A3XX_RB_ALPHA_REF_UINT__SHIFT
) & A3XX_RB_ALPHA_REF_UINT__MASK
;
813 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
814 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
815 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val
)
817 return ((util_float_to_half(val
)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT
) & A3XX_RB_ALPHA_REF_FLOAT__MASK
;
820 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
822 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
823 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
824 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
825 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
826 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
827 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
828 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val
)
830 return ((val
) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK
;
832 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000
833 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12
834 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val
)
836 return ((val
) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT
) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
;
838 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
839 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
840 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val
)
842 return ((val
) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
845 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0
) { return 0x000020c5 + 0x4*i0
; }
846 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
847 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
848 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val
)
850 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
;
852 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
853 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
854 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val
)
856 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
;
858 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00
859 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10
860 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
862 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
;
864 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000
865 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
866 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val
)
868 return ((val
>> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK
;
871 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0
) { return 0x000020c6 + 0x4*i0
; }
872 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
873 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
874 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val
)
876 return ((val
>> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT
) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK
;
879 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0
) { return 0x000020c7 + 0x4*i0
; }
880 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
881 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
882 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val
)
884 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
;
886 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
887 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
888 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val
)
890 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
;
892 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
893 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
894 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val
)
896 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
;
898 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
899 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
900 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val
)
902 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
;
904 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
905 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
906 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val
)
908 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
;
910 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
911 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
912 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val
)
914 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
;
916 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
918 #define REG_A3XX_RB_BLEND_RED 0x000020e4
919 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
920 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0
921 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val
)
923 return ((val
) << A3XX_RB_BLEND_RED_UINT__SHIFT
) & A3XX_RB_BLEND_RED_UINT__MASK
;
925 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
926 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
927 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val
)
929 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT
) & A3XX_RB_BLEND_RED_FLOAT__MASK
;
932 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5
933 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
934 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
935 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val
)
937 return ((val
) << A3XX_RB_BLEND_GREEN_UINT__SHIFT
) & A3XX_RB_BLEND_GREEN_UINT__MASK
;
939 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
940 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
941 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val
)
943 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT
) & A3XX_RB_BLEND_GREEN_FLOAT__MASK
;
946 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6
947 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
948 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
949 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val
)
951 return ((val
) << A3XX_RB_BLEND_BLUE_UINT__SHIFT
) & A3XX_RB_BLEND_BLUE_UINT__MASK
;
953 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
954 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
955 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val
)
957 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT
) & A3XX_RB_BLEND_BLUE_FLOAT__MASK
;
960 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
961 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
962 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
963 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val
)
965 return ((val
) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT
) & A3XX_RB_BLEND_ALPHA_UINT__MASK
;
967 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
968 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
969 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val
)
971 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT
) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK
;
974 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
976 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9
978 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea
980 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb
982 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec
983 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
984 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
985 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val
)
987 return ((val
) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT
) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK
;
989 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
990 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
991 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val
)
993 return ((val
) << A3XX_RB_COPY_CONTROL_MODE__SHIFT
) & A3XX_RB_COPY_CONTROL_MODE__MASK
;
995 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
996 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
997 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val
)
999 return ((val
>> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT
) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK
;
1002 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
1003 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0
1004 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
1005 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val
)
1007 return ((val
>> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT
) & A3XX_RB_COPY_DEST_BASE_BASE__MASK
;
1010 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
1011 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1012 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1013 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val
)
1015 return ((val
>> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT
) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK
;
1018 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
1019 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003
1020 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0
1021 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val
)
1023 return ((val
) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_TILE__MASK
;
1025 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1026 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
1027 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val
)
1029 return ((val
) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK
;
1031 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1032 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1033 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val
)
1035 return ((val
) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT
) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK
;
1037 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1038 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1039 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val
)
1041 return ((val
) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK
;
1043 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1044 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1045 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val
)
1047 return ((val
) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT
) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK
;
1050 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
1051 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1052 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1053 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1054 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
1055 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1056 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1057 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val
)
1059 return ((val
) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT
) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK
;
1061 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1062 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1064 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
1066 #define REG_A3XX_RB_DEPTH_INFO 0x00002102
1067 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
1068 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1069 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val
)
1071 return ((val
) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
;
1073 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800
1074 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
1075 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val
)
1077 return ((val
>> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
1080 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103
1081 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff
1082 #define A3XX_RB_DEPTH_PITCH__SHIFT 0
1083 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val
)
1085 return ((val
>> 3) << A3XX_RB_DEPTH_PITCH__SHIFT
) & A3XX_RB_DEPTH_PITCH__MASK
;
1088 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
1089 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1090 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1091 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1092 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1093 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1094 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val
)
1096 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK
;
1098 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1099 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1100 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val
)
1102 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK
;
1104 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1105 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1106 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val
)
1108 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK
;
1110 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1111 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1112 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val
)
1114 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK
;
1116 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1117 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1118 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val
)
1120 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
;
1122 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1123 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1124 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val
)
1126 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
;
1128 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1129 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1130 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val
)
1132 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
;
1134 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1135 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1136 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val
)
1138 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
;
1141 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
1143 #define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106
1145 #define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107
1147 #define REG_A3XX_RB_STENCILREFMASK 0x00002108
1148 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1149 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1150 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
1152 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK
;
1154 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1155 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1156 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
1158 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
1160 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1161 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1162 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
1164 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
1167 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109
1168 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1169 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1170 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val
)
1172 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
;
1174 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1175 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1176 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val
)
1178 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
;
1180 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1181 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1182 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val
)
1184 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
;
1187 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c
1188 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002
1190 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e
1191 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff
1192 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0
1193 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val
)
1195 return ((val
) << A3XX_RB_WINDOW_OFFSET_X__SHIFT
) & A3XX_RB_WINDOW_OFFSET_X__MASK
;
1197 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000
1198 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16
1199 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val
)
1201 return ((val
) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT
) & A3XX_RB_WINDOW_OFFSET_Y__MASK
;
1204 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
1206 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
1208 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114
1210 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
1212 #define REG_A3XX_VGT_BIN_BASE 0x000021e1
1214 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2
1216 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1217 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
1218 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
1219 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val
)
1221 return ((val
) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT
) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK
;
1223 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
1224 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22
1225 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val
)
1227 return ((val
) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT
) & A3XX_PC_VSTREAM_CONTROL_N__MASK
;
1230 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
1232 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec
1233 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
1234 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0
1235 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val
)
1237 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK
;
1239 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0
1240 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5
1241 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val
)
1243 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK
;
1245 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700
1246 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8
1247 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val
)
1249 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK
;
1251 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1252 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
1254 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1256 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
1257 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
1258 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1259 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val
)
1261 return ((val
) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
;
1263 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1264 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1265 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1266 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1267 #define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE 0x08000000
1268 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1269 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1270 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1271 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1273 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1274 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
1275 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1276 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val
)
1278 return ((val
) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK
;
1280 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1281 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
1282 #define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
1284 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1285 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1286 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1287 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val
)
1289 return ((val
) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT
) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK
;
1292 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1293 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
1294 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
1295 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val
)
1297 return ((val
) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT
) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK
;
1300 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1301 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1302 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1303 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1305 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK
;
1307 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1308 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1309 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1311 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1313 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1314 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1315 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1317 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK
;
1320 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1321 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1322 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1323 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1325 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK
;
1327 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1328 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1329 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1331 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1333 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1334 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1335 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1337 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK
;
1340 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1341 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1342 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1343 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1345 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK
;
1347 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1348 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1349 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1351 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK
;
1354 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1355 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1356 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1357 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1359 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK
;
1361 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1362 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1363 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1365 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK
;
1368 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1370 #define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b
1372 #define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c
1374 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
1376 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212
1378 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
1380 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215
1382 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
1384 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
1386 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
1388 #define REG_A3XX_VFD_CONTROL_0 0x00002240
1389 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff
1390 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1391 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val
)
1393 return ((val
) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT
) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK
;
1395 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000
1396 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18
1397 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val
)
1399 return ((val
) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT
) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK
;
1401 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000
1402 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22
1403 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val
)
1405 return ((val
) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK
;
1407 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1408 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1409 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val
)
1411 return ((val
) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK
;
1414 #define REG_A3XX_VFD_CONTROL_1 0x00002241
1415 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1416 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1417 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val
)
1419 return ((val
) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT
) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK
;
1421 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1422 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1423 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val
)
1425 return ((val
) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK
;
1427 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1428 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1429 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val
)
1431 return ((val
) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4INST__MASK
;
1434 #define REG_A3XX_VFD_INDEX_MIN 0x00002242
1436 #define REG_A3XX_VFD_INDEX_MAX 0x00002243
1438 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244
1440 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1442 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1444 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1445 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1446 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1447 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val
)
1449 return ((val
) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK
;
1451 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1452 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1453 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val
)
1455 return ((val
) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK
;
1457 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000
1458 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000
1459 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18
1460 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val
)
1462 return ((val
) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK
;
1464 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000
1465 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24
1466 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val
)
1468 return ((val
) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK
;
1471 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0
) { return 0x00002247 + 0x2*i0
; }
1473 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1475 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1476 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1477 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1478 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val
)
1480 return ((val
) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT
) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK
;
1482 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1483 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1484 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1485 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val
)
1487 return ((val
) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT
) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK
;
1489 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1490 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1491 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val
)
1493 return ((val
) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT
) & A3XX_VFD_DECODE_INSTR_REGID__MASK
;
1495 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1496 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1497 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val
)
1499 return ((val
) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT
) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK
;
1501 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1502 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1504 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e
1505 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f
1506 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0
1507 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val
)
1509 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK
;
1511 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00
1512 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8
1513 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val
)
1515 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK
;
1518 #define REG_A3XX_VPC_ATTR 0x00002280
1519 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1520 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
1521 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val
)
1523 return ((val
) << A3XX_VPC_ATTR_TOTALATTR__SHIFT
) & A3XX_VPC_ATTR_TOTALATTR__MASK
;
1525 #define A3XX_VPC_ATTR_PSIZE 0x00000200
1526 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
1527 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1528 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val
)
1530 return ((val
) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT
) & A3XX_VPC_ATTR_THRDASSIGN__MASK
;
1532 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000
1533 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28
1534 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val
)
1536 return ((val
) << A3XX_VPC_ATTR_LMSIZE__SHIFT
) & A3XX_VPC_ATTR_LMSIZE__MASK
;
1539 #define REG_A3XX_VPC_PACK 0x00002281
1540 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1541 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1542 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val
)
1544 return ((val
) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT
) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK
;
1546 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1547 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1548 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val
)
1550 return ((val
) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT
) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK
;
1553 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1555 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1557 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1559 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1561 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
1563 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b
1565 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
1566 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
1567 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000
1568 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
1569 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val
)
1571 return ((val
) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK
;
1573 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000
1574 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
1575 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
1576 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val
)
1578 return ((val
) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK
;
1580 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000
1581 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22
1582 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val
)
1584 return ((val
) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK
;
1587 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
1588 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1589 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1590 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1592 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK
;
1594 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1595 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1596 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1598 return ((val
) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1600 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1601 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1602 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1603 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1605 return ((val
) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
1607 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1608 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1609 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
1611 return ((val
) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
1613 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1614 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1615 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
1617 return ((val
) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
1619 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1620 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1621 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
1623 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
;
1625 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1626 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1627 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
1628 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
1629 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val
)
1631 return ((val
) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK
;
1634 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5
1635 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
1636 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1637 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
1639 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK
;
1641 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
1642 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
1643 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
1645 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
1647 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000
1648 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1649 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
1651 return ((val
) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
1654 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6
1655 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1656 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1657 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val
)
1659 return ((val
) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK
;
1661 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1662 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1663 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val
)
1665 return ((val
) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK
;
1667 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1668 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1669 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val
)
1671 return ((val
) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT
) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK
;
1674 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
1676 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
1677 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1678 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1679 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val
)
1681 return ((val
) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_A_REGID__MASK
;
1683 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1684 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1685 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val
)
1687 return ((val
) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK
;
1689 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1690 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1691 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val
)
1693 return ((val
) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_B_REGID__MASK
;
1695 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1696 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1697 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val
)
1699 return ((val
) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK
;
1702 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
1704 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
1705 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1706 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1707 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val
)
1709 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
;
1711 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1712 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1713 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val
)
1715 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
;
1717 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1718 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1719 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val
)
1721 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
;
1723 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1724 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1725 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val
)
1727 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
;
1730 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
1731 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1732 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1733 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
1735 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
1737 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1738 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1739 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
1741 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
1744 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
1746 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
1748 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
1750 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
1752 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
1753 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
1754 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
1755 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
1757 return ((val
) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK
;
1760 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0
1761 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1762 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1763 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1765 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK
;
1767 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1768 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1769 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1771 return ((val
) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1773 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1774 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1775 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1776 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1778 return ((val
) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
1780 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1781 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1782 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
1784 return ((val
) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
1786 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1787 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1788 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
1790 return ((val
) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
1792 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1793 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1794 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
1796 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
;
1798 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1799 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1800 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
1801 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
1802 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val
)
1804 return ((val
) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK
;
1807 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1
1808 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
1809 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1810 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
1812 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK
;
1814 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
1815 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
1816 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
1818 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
1820 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
1821 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
1822 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
1824 return ((val
) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
1826 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
1827 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
1828 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val
)
1830 return ((val
) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT
) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK
;
1833 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
1834 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1835 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1836 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
1838 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
1840 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1841 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1842 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
1844 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
1847 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
1849 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
1851 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
1853 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
1855 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
1857 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
1859 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
1860 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1861 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1862 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1863 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val
)
1865 return ((val
) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT
) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK
;
1868 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
1870 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
1871 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1872 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
1873 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val
)
1875 return ((val
) << A3XX_SP_FS_MRT_REG_REGID__SHIFT
) & A3XX_SP_FS_MRT_REG_REGID__MASK
;
1877 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1879 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
1881 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
1882 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
1883 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
1884 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val
)
1886 return ((val
) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT
) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK
;
1889 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff
1890 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
1891 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0
1892 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
1894 return ((val
) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK
;
1897 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340
1898 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
1899 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
1900 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
1902 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
1904 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
1905 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
1906 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
1908 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
1910 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
1911 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
1912 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
1914 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK
;
1917 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341
1919 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342
1920 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
1921 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
1922 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
1924 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
1926 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
1927 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
1928 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
1930 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
1932 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
1933 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
1934 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
1936 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK
;
1939 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343
1941 #define REG_A3XX_VBIF_CLKON 0x00003001
1943 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c
1945 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d
1947 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e
1949 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c
1951 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d
1953 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1955 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1957 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1959 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030
1961 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031
1963 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034
1965 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035
1967 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036
1969 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c
1971 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1973 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058
1975 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e
1977 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
1979 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01
1980 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1981 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1982 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val
)
1984 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT
) & A3XX_VSC_BIN_SIZE_WIDTH__MASK
;
1986 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1987 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1988 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val
)
1990 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT
) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK
;
1993 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
1995 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
1997 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
1998 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
1999 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
2000 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val
)
2002 return ((val
) << A3XX_VSC_PIPE_CONFIG_X__SHIFT
) & A3XX_VSC_PIPE_CONFIG_X__MASK
;
2004 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00
2005 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10
2006 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val
)
2008 return ((val
) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT
) & A3XX_VSC_PIPE_CONFIG_Y__MASK
;
2010 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000
2011 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20
2012 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val
)
2014 return ((val
) << A3XX_VSC_PIPE_CONFIG_W__SHIFT
) & A3XX_VSC_PIPE_CONFIG_W__MASK
;
2016 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000
2017 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24
2018 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val
)
2020 return ((val
) << A3XX_VSC_PIPE_CONFIG_H__SHIFT
) & A3XX_VSC_PIPE_CONFIG_H__MASK
;
2023 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0
) { return 0x00000c07 + 0x3*i0
; }
2025 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0
) { return 0x00000c08 + 0x3*i0
; }
2027 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c
2028 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001
2030 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
2032 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
2034 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
2036 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
2038 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
2040 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81
2042 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
2044 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
2046 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
2048 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
2050 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
2052 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
2054 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0
) { return 0x00000ca1 + 0x4*i0
; }
2056 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0
) { return 0x00000ca2 + 0x4*i0
; }
2058 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0
) { return 0x00000ca3 + 0x4*i0
; }
2060 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
2062 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1
2064 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
2066 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
2068 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
2069 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
2070 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
2071 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val
)
2073 return ((val
) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT
) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK
;
2075 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000
2076 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14
2077 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val
)
2079 return ((val
) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT
) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK
;
2082 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
2084 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
2086 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
2088 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
2090 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
2092 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
2094 #define REG_A3XX_UNKNOWN_0E43 0x00000e43
2096 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
2098 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
2100 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
2102 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
2104 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
2106 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
2108 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
2110 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
2112 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
2114 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
2116 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
2118 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
2120 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
2122 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
2123 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
2124 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
2125 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val
)
2127 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK
;
2130 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1
2131 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff
2132 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0
2133 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val
)
2135 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK
;
2137 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000
2138 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28
2139 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val
)
2141 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK
;
2143 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
2145 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6
2147 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
2149 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
2151 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6
2153 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7
2155 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8
2157 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9
2159 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca
2161 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb
2163 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0
2165 #define REG_A3XX_UNKNOWN_0F03 0x00000f03
2167 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
2169 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
2171 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
2173 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
2175 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
2177 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
2179 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0
2181 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
2183 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
2184 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
2185 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
2186 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val
)
2188 return ((val
) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK
;
2190 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
2191 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
2192 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val
)
2194 return ((val
) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK
;
2196 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
2197 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
2198 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val
)
2200 return ((val
) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK
;
2202 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
2203 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
2204 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val
)
2206 return ((val
) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK
;
2208 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
2209 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
2210 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
2211 #define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000
2212 #define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16
2213 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val
)
2215 return ((val
) << A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK
;
2218 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd
2220 #define REG_A3XX_TEX_SAMP_0 0x00000000
2221 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
2222 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
2223 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
2224 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val
)
2226 return ((val
) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT
) & A3XX_TEX_SAMP_0_XY_MAG__MASK
;
2228 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030
2229 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4
2230 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val
)
2232 return ((val
) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT
) & A3XX_TEX_SAMP_0_XY_MIN__MASK
;
2234 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0
2235 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6
2236 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val
)
2238 return ((val
) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_S__MASK
;
2240 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00
2241 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9
2242 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val
)
2244 return ((val
) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_T__MASK
;
2246 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000
2247 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12
2248 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val
)
2250 return ((val
) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_R__MASK
;
2252 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
2254 #define REG_A3XX_TEX_SAMP_1 0x00000001
2255 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000
2256 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12
2257 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val
)
2259 return ((((uint32_t)(val
* 12.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT
) & A3XX_TEX_SAMP_1_MAX_LOD__MASK
;
2261 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000
2262 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22
2263 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val
)
2265 return ((((uint32_t)(val
* 12.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT
) & A3XX_TEX_SAMP_1_MIN_LOD__MASK
;
2268 #define REG_A3XX_TEX_CONST_0 0x00000000
2269 #define A3XX_TEX_CONST_0_TILED 0x00000001
2270 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2271 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2272 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val
)
2274 return ((val
) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_X__MASK
;
2276 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2277 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2278 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val
)
2280 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Y__MASK
;
2282 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2283 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2284 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val
)
2286 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Z__MASK
;
2288 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2289 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2290 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val
)
2292 return ((val
) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_W__MASK
;
2294 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2295 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2296 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val
)
2298 return ((val
) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT
) & A3XX_TEX_CONST_0_MIPLVLS__MASK
;
2300 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2301 #define A3XX_TEX_CONST_0_FMT__SHIFT 22
2302 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val
)
2304 return ((val
) << A3XX_TEX_CONST_0_FMT__SHIFT
) & A3XX_TEX_CONST_0_FMT__MASK
;
2306 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
2307 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30
2308 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val
)
2310 return ((val
) << A3XX_TEX_CONST_0_TYPE__SHIFT
) & A3XX_TEX_CONST_0_TYPE__MASK
;
2313 #define REG_A3XX_TEX_CONST_1 0x00000001
2314 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
2315 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0
2316 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val
)
2318 return ((val
) << A3XX_TEX_CONST_1_HEIGHT__SHIFT
) & A3XX_TEX_CONST_1_HEIGHT__MASK
;
2320 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000
2321 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14
2322 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val
)
2324 return ((val
) << A3XX_TEX_CONST_1_WIDTH__SHIFT
) & A3XX_TEX_CONST_1_WIDTH__MASK
;
2326 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000
2327 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28
2328 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val
)
2330 return ((val
) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT
) & A3XX_TEX_CONST_1_FETCHSIZE__MASK
;
2333 #define REG_A3XX_TEX_CONST_2 0x00000002
2334 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff
2335 #define A3XX_TEX_CONST_2_INDX__SHIFT 0
2336 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val
)
2338 return ((val
) << A3XX_TEX_CONST_2_INDX__SHIFT
) & A3XX_TEX_CONST_2_INDX__MASK
;
2340 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000
2341 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12
2342 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val
)
2344 return ((val
) << A3XX_TEX_CONST_2_PITCH__SHIFT
) & A3XX_TEX_CONST_2_PITCH__MASK
;
2346 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2347 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30
2348 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val
)
2350 return ((val
) << A3XX_TEX_CONST_2_SWAP__SHIFT
) & A3XX_TEX_CONST_2_SWAP__MASK
;
2353 #define REG_A3XX_TEX_CONST_3 0x00000003
2356 #endif /* A3XX_XML */