4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 32800 bytes, from 2013-10-22 23:57:49)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 10345 bytes, from 2013-10-25 14:31:35)
16 - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 52655 bytes, from 2013-10-25 14:43:32)
18 Copyright (C) 2013 by the following authors:
19 - Rob Clark <robdclark@gmail.com> (robclark)
21 Permission is hereby granted, free of charge, to any person obtaining
22 a copy of this software and associated documentation files (the
23 "Software"), to deal in the Software without restriction, including
24 without limitation the rights to use, copy, modify, merge, publish,
25 distribute, sublicense, and/or sell copies of the Software, and to
26 permit persons to whom the Software is furnished to do so, subject to
27 the following conditions:
29 The above copyright notice and this permission notice (including the
30 next paragraph) shall be included in all copies or substantial
31 portions of the Software.
33 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
35 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
36 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
37 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
38 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
39 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
43 enum a3xx_render_mode
{
44 RB_RENDERING_PASS
= 0,
54 enum a3xx_threadmode
{
59 enum a3xx_instrbuffermode
{
63 enum a3xx_threadsize
{
68 enum a3xx_state_block_id
{
69 HLSQ_BLOCK_ID_TP_TEX
= 2,
70 HLSQ_BLOCK_ID_TP_MIPMAP
= 3,
71 HLSQ_BLOCK_ID_SP_VS
= 4,
72 HLSQ_BLOCK_ID_SP_FS
= 6,
75 enum a3xx_cache_opcode
{
82 VFMT_FLOAT_32_32_32
= 2,
83 VFMT_FLOAT_32_32_32_32
= 3,
86 VFMT_FLOAT_16_16_16
= 6,
87 VFMT_FLOAT_16_16_16_16
= 7,
90 VFMT_FIXED_32_32_32
= 10,
91 VFMT_FIXED_32_32_32_32
= 11,
93 VFMT_SHORT_16_16
= 17,
94 VFMT_SHORT_16_16_16
= 18,
95 VFMT_SHORT_16_16_16_16
= 19,
97 VFMT_USHORT_16_16
= 21,
98 VFMT_USHORT_16_16_16
= 22,
99 VFMT_USHORT_16_16_16_16
= 23,
100 VFMT_NORM_SHORT_16
= 24,
101 VFMT_NORM_SHORT_16_16
= 25,
102 VFMT_NORM_SHORT_16_16_16
= 26,
103 VFMT_NORM_SHORT_16_16_16_16
= 27,
104 VFMT_NORM_USHORT_16
= 28,
105 VFMT_NORM_USHORT_16_16
= 29,
106 VFMT_NORM_USHORT_16_16_16
= 30,
107 VFMT_NORM_USHORT_16_16_16_16
= 31,
110 VFMT_UBYTE_8_8_8
= 42,
111 VFMT_UBYTE_8_8_8_8
= 43,
112 VFMT_NORM_UBYTE_8
= 44,
113 VFMT_NORM_UBYTE_8_8
= 45,
114 VFMT_NORM_UBYTE_8_8_8
= 46,
115 VFMT_NORM_UBYTE_8_8_8_8
= 47,
118 VFMT_BYTE_8_8_8
= 50,
119 VFMT_BYTE_8_8_8_8
= 51,
120 VFMT_NORM_BYTE_8
= 52,
121 VFMT_NORM_BYTE_8_8
= 53,
122 VFMT_NORM_BYTE_8_8_8
= 54,
123 VFMT_NORM_BYTE_8_8_8_8
= 55,
124 VFMT_UINT_10_10_10_2
= 60,
125 VFMT_NORM_UINT_10_10_10_2
= 61,
126 VFMT_INT_10_10_10_2
= 62,
127 VFMT_NORM_INT_10_10_10_2
= 63,
131 TFMT_NORM_USHORT_565
= 4,
132 TFMT_NORM_USHORT_5551
= 6,
133 TFMT_NORM_USHORT_4444
= 7,
134 TFMT_NORM_UINT_X8Z24
= 10,
135 TFMT_NORM_UINT_NV12_UV_TILED
= 17,
136 TFMT_NORM_UINT_NV12_Y_TILED
= 19,
137 TFMT_NORM_UINT_NV12_UV
= 21,
138 TFMT_NORM_UINT_NV12_Y
= 23,
139 TFMT_NORM_UINT_I420_Y
= 24,
140 TFMT_NORM_UINT_I420_U
= 26,
141 TFMT_NORM_UINT_I420_V
= 27,
142 TFMT_NORM_UINT_2_10_10_10
= 41,
143 TFMT_NORM_UINT_A8
= 44,
144 TFMT_NORM_UINT_L8_A8
= 47,
145 TFMT_NORM_UINT_8
= 48,
146 TFMT_NORM_UINT_8_8
= 49,
147 TFMT_NORM_UINT_8_8_8
= 50,
148 TFMT_NORM_UINT_8_8_8_8
= 51,
150 TFMT_FLOAT_16_16
= 65,
151 TFMT_FLOAT_16_16_16_16
= 67,
153 TFMT_FLOAT_32_32
= 85,
154 TFMT_FLOAT_32_32_32_32
= 87,
157 enum a3xx_tex_fetchsize
{
166 enum a3xx_color_fmt
{
168 RB_R8G8B8A8_UNORM
= 8,
173 enum a3xx_color_swap
{
180 enum a3xx_msaa_samples
{
186 enum a3xx_sp_perfcounter_select
{
187 SP_FS_CFLOW_INSTRUCTIONS
= 12,
188 SP_FS_FULL_ALU_INSTRUCTIONS
= 14,
189 SP0_ICL1_MISSES
= 26,
190 SP_ALU_ACTIVE_CYCLES
= 29,
193 enum adreno_rb_copy_control_mode
{
195 RB_COPY_DEPTH_STENCIL
= 5,
198 enum a3xx_tex_filter
{
199 A3XX_TEX_NEAREST
= 0,
203 enum a3xx_tex_clamp
{
205 A3XX_TEX_CLAMP_TO_EDGE
= 1,
206 A3XX_TEX_MIRROR_REPEAT
= 2,
207 A3XX_TEX_CLAMP_NONE
= 3,
226 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
227 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
228 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
229 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
230 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
231 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
232 #define A3XX_INT0_VFD_ERROR 0x00000040
233 #define A3XX_INT0_CP_SW_INT 0x00000080
234 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
235 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
236 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
237 #define A3XX_INT0_CP_HW_FAULT 0x00000800
238 #define A3XX_INT0_CP_DMA 0x00001000
239 #define A3XX_INT0_CP_IB2_INT 0x00002000
240 #define A3XX_INT0_CP_IB1_INT 0x00004000
241 #define A3XX_INT0_CP_RB_INT 0x00008000
242 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
243 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000
244 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000
245 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000
246 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
247 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
248 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000
249 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
250 #define REG_A3XX_RBBM_HW_VERSION 0x00000000
252 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001
254 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002
256 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010
258 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012
260 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018
262 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020
264 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021
266 #define REG_A3XX_RBBM_AHB_CMD 0x00000022
268 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027
270 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
272 #define REG_A3XX_RBBM_STATUS 0x00000030
273 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
274 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
275 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
276 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
277 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
278 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
279 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
280 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
281 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
282 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
283 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
284 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
285 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
286 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
287 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
288 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
289 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
290 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
291 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
292 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
293 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
295 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
297 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
299 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
301 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051
303 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054
305 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057
307 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
309 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
311 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
313 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063
315 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
317 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
319 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
321 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
323 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
325 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
327 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
329 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
331 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
333 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
335 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
337 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
339 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
341 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
343 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
345 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
347 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
349 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
351 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
353 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
355 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
357 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
359 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
361 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
363 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
365 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
367 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
369 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
371 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
373 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
375 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
377 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
379 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
381 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
383 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
385 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
387 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
389 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
391 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
393 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
395 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
397 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
399 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
401 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
403 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
405 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
407 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
409 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
411 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
413 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
415 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
417 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
419 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
421 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
423 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
425 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
427 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
429 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
431 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
433 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
435 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
437 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
439 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
441 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
443 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
445 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
447 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
449 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
451 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
453 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
455 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
457 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
459 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
461 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
463 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
465 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
467 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
469 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
471 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
473 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
475 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
477 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
479 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
481 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
483 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
485 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
487 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
489 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
491 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
493 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
495 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
497 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
499 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
501 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
503 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
505 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
507 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
509 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
511 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
513 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100
515 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
517 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
519 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9
521 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca
523 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc
525 #define REG_A3XX_CP_ROQ_DATA 0x000001cd
527 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1
529 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2
531 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3
533 #define REG_A3XX_CP_MEQ_ADDR 0x000001da
535 #define REG_A3XX_CP_MEQ_DATA 0x000001db
537 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
539 #define REG_A3XX_CP_HW_FAULT 0x0000045c
541 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
543 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
545 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
547 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
549 #define REG_A3XX_CP_AHB_FAULT 0x0000054d
551 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
552 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
553 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
554 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
555 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
556 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
557 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
559 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
560 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
561 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
562 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val
)
564 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK
;
566 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
567 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
568 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val
)
570 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK
;
573 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048
574 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
575 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
576 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val
)
578 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK
;
581 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049
582 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
583 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
584 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val
)
586 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_XSCALE__MASK
;
589 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a
590 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
591 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
592 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val
)
594 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK
;
597 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b
598 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
599 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
600 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val
)
602 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_YSCALE__MASK
;
605 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c
606 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
607 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
608 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val
)
610 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK
;
613 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d
614 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
615 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
616 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val
)
618 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK
;
621 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
623 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
625 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
626 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
627 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
628 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val
)
630 return ((((uint32_t)(val
* 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK
;
633 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
634 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
635 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
636 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val
)
638 return ((((uint32_t)(val
* 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
641 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
642 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
643 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
644 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
645 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
646 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
647 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val
)
649 return ((((uint32_t)(val
* 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT
) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK
;
651 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
653 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072
654 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0
655 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4
656 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
658 return ((val
) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK
;
660 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00
661 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8
662 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val
)
664 return ((val
) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT
) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK
;
666 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
667 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
668 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val
)
670 return ((val
) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK
;
673 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074
674 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
675 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
676 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
677 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val
)
679 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
;
681 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
682 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
683 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val
)
685 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
;
688 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075
689 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
690 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
691 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
692 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val
)
694 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
;
696 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
697 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
698 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val
)
700 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
;
703 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079
704 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
705 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
706 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
707 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
709 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
;
711 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
712 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
713 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
715 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
;
718 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a
719 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
720 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
721 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
722 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
724 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
;
726 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
727 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
728 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
730 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
;
733 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0
734 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080
735 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700
736 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8
737 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
739 return ((val
) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT
) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK
;
741 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
742 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
744 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
745 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
746 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
747 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val
)
749 return ((val
>> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT
) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK
;
751 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
752 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
753 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
754 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
755 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
756 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val
)
758 return ((val
) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT
) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK
;
761 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
762 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
763 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000
764 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12
765 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val
)
767 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK
;
769 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000
770 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16
771 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val
)
773 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK
;
776 #define REG_A3XX_RB_ALPHA_REF 0x000020c3
777 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
778 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
779 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val
)
781 return ((val
) << A3XX_RB_ALPHA_REF_UINT__SHIFT
) & A3XX_RB_ALPHA_REF_UINT__MASK
;
783 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
784 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
785 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val
)
787 return ((util_float_to_half(val
)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT
) & A3XX_RB_ALPHA_REF_FLOAT__MASK
;
790 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
792 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
793 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
794 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
795 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
796 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
797 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
798 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(uint32_t val
)
800 return ((val
) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK
;
802 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000
803 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12
804 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val
)
806 return ((val
) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT
) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
;
808 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
809 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
810 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val
)
812 return ((val
) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
815 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0
) { return 0x000020c5 + 0x4*i0
; }
816 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
817 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
818 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val
)
820 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
;
822 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
823 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
824 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val
)
826 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
;
828 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00
829 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10
830 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
832 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
;
834 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000
835 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
836 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val
)
838 return ((val
>> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK
;
841 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0
) { return 0x000020c6 + 0x4*i0
; }
842 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
843 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
844 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val
)
846 return ((val
>> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT
) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK
;
849 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0
) { return 0x000020c7 + 0x4*i0
; }
850 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
851 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
852 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val
)
854 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
;
856 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
857 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
858 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val
)
860 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
;
862 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
863 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
864 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val
)
866 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
;
868 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
869 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
870 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val
)
872 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
;
874 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
875 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
876 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val
)
878 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
;
880 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
881 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
882 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val
)
884 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
;
886 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
888 #define REG_A3XX_RB_BLEND_RED 0x000020e4
889 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
890 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0
891 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val
)
893 return ((val
) << A3XX_RB_BLEND_RED_UINT__SHIFT
) & A3XX_RB_BLEND_RED_UINT__MASK
;
895 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
896 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
897 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val
)
899 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT
) & A3XX_RB_BLEND_RED_FLOAT__MASK
;
902 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5
903 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
904 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
905 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val
)
907 return ((val
) << A3XX_RB_BLEND_GREEN_UINT__SHIFT
) & A3XX_RB_BLEND_GREEN_UINT__MASK
;
909 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
910 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
911 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val
)
913 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT
) & A3XX_RB_BLEND_GREEN_FLOAT__MASK
;
916 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6
917 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
918 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
919 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val
)
921 return ((val
) << A3XX_RB_BLEND_BLUE_UINT__SHIFT
) & A3XX_RB_BLEND_BLUE_UINT__MASK
;
923 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
924 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
925 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val
)
927 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT
) & A3XX_RB_BLEND_BLUE_FLOAT__MASK
;
930 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
931 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
932 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
933 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val
)
935 return ((val
) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT
) & A3XX_RB_BLEND_ALPHA_UINT__MASK
;
937 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
938 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
939 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val
)
941 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT
) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK
;
944 #define REG_A3XX_UNKNOWN_20E8 0x000020e8
946 #define REG_A3XX_UNKNOWN_20E9 0x000020e9
948 #define REG_A3XX_UNKNOWN_20EA 0x000020ea
950 #define REG_A3XX_UNKNOWN_20EB 0x000020eb
952 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec
953 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
954 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
955 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val
)
957 return ((val
) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT
) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK
;
959 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
960 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
961 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val
)
963 return ((val
) << A3XX_RB_COPY_CONTROL_MODE__SHIFT
) & A3XX_RB_COPY_CONTROL_MODE__MASK
;
965 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xfffffc00
966 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 10
967 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val
)
969 return ((val
>> 10) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT
) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK
;
972 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
973 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0
974 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
975 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val
)
977 return ((val
>> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT
) & A3XX_RB_COPY_DEST_BASE_BASE__MASK
;
980 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
981 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
982 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
983 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val
)
985 return ((val
>> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT
) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK
;
988 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
989 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003
990 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0
991 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val
)
993 return ((val
) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_TILE__MASK
;
995 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
996 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
997 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val
)
999 return ((val
) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK
;
1001 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1002 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1003 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val
)
1005 return ((val
) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT
) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK
;
1007 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1008 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1009 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val
)
1011 return ((val
) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK
;
1013 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1014 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1015 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val
)
1017 return ((val
) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT
) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK
;
1020 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
1021 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1022 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1023 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
1024 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1025 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1026 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val
)
1028 return ((val
) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT
) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK
;
1030 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1031 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1033 #define REG_A3XX_UNKNOWN_2101 0x00002101
1035 #define REG_A3XX_RB_DEPTH_INFO 0x00002102
1036 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
1037 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1038 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val
)
1040 return ((val
) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
;
1042 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800
1043 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
1044 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val
)
1046 return ((val
>> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
1049 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103
1050 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff
1051 #define A3XX_RB_DEPTH_PITCH__SHIFT 0
1052 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val
)
1054 return ((val
>> 3) << A3XX_RB_DEPTH_PITCH__SHIFT
) & A3XX_RB_DEPTH_PITCH__MASK
;
1057 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
1058 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1059 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1060 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1061 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1062 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1063 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val
)
1065 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK
;
1067 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1068 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1069 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val
)
1071 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK
;
1073 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1074 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1075 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val
)
1077 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK
;
1079 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1080 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1081 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val
)
1083 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK
;
1085 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1086 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1087 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val
)
1089 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
;
1091 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1092 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1093 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val
)
1095 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
;
1097 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1098 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1099 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val
)
1101 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
;
1103 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1104 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1105 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val
)
1107 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
;
1110 #define REG_A3XX_UNKNOWN_2105 0x00002105
1112 #define REG_A3XX_UNKNOWN_2106 0x00002106
1114 #define REG_A3XX_UNKNOWN_2107 0x00002107
1116 #define REG_A3XX_RB_STENCILREFMASK 0x00002108
1117 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1118 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1119 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
1121 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK
;
1123 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1124 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1125 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
1127 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
1129 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1130 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1131 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
1133 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
1136 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109
1137 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1138 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1139 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val
)
1141 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
;
1143 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1144 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1145 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val
)
1147 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
;
1149 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1150 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1151 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val
)
1153 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
;
1156 #define REG_A3XX_PA_SC_WINDOW_OFFSET 0x0000210e
1157 #define A3XX_PA_SC_WINDOW_OFFSET_X__MASK 0x0000ffff
1158 #define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0
1159 static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val
)
1161 return ((val
) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT
) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK
;
1163 #define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK 0xffff0000
1164 #define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16
1165 static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val
)
1167 return ((val
) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT
) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK
;
1170 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1172 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
1174 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec
1175 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
1176 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0
1177 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val
)
1179 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK
;
1181 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0
1182 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5
1183 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val
)
1185 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK
;
1187 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700
1188 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8
1189 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val
)
1191 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK
;
1193 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1195 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1197 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
1198 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
1199 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1200 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val
)
1202 return ((val
) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
;
1204 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1205 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1206 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1207 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1208 #define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE 0x08000000
1209 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1210 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1211 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1212 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1214 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1215 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
1216 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1217 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val
)
1219 return ((val
) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK
;
1221 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1222 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
1224 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1225 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1226 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1227 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val
)
1229 return ((val
) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT
) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK
;
1232 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1234 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1235 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1236 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1237 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1239 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK
;
1241 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1242 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1243 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1245 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1247 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1248 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1249 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1251 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK
;
1254 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1255 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1256 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1257 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1259 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK
;
1261 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1262 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1263 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1265 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1267 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1268 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1269 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1271 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK
;
1274 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1275 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1276 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1277 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1279 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK
;
1281 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1282 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1283 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1285 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK
;
1288 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1289 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1290 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1291 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1293 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK
;
1295 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1296 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1297 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1299 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK
;
1302 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1304 #define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b
1306 #define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c
1308 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
1310 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212
1312 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
1314 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215
1316 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
1318 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
1320 #define REG_A3XX_VFD_CONTROL_0 0x00002240
1321 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff
1322 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1323 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val
)
1325 return ((val
) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT
) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK
;
1327 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000
1328 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18
1329 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val
)
1331 return ((val
) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT
) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK
;
1333 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000
1334 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22
1335 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val
)
1337 return ((val
) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK
;
1339 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1340 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1341 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val
)
1343 return ((val
) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK
;
1346 #define REG_A3XX_VFD_CONTROL_1 0x00002241
1347 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1348 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1349 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val
)
1351 return ((val
) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT
) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK
;
1353 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1354 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1355 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val
)
1357 return ((val
) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK
;
1359 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1360 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1361 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val
)
1363 return ((val
) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4INST__MASK
;
1366 #define REG_A3XX_VFD_INDEX_MIN 0x00002242
1368 #define REG_A3XX_VFD_INDEX_MAX 0x00002243
1370 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244
1372 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1374 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1376 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1377 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1378 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1379 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val
)
1381 return ((val
) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK
;
1383 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1384 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1385 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val
)
1387 return ((val
) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK
;
1389 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000
1390 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000
1391 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18
1392 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val
)
1394 return ((val
) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK
;
1396 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000
1397 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24
1398 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val
)
1400 return ((val
) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK
;
1403 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0
) { return 0x00002247 + 0x2*i0
; }
1405 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1407 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1408 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1409 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1410 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val
)
1412 return ((val
) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT
) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK
;
1414 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1415 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1416 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1417 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val
)
1419 return ((val
) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT
) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK
;
1421 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1422 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1423 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val
)
1425 return ((val
) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT
) & A3XX_VFD_DECODE_INSTR_REGID__MASK
;
1427 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1428 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1429 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val
)
1431 return ((val
) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT
) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK
;
1433 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1434 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1436 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e
1437 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f
1438 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0
1439 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val
)
1441 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK
;
1443 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00
1444 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8
1445 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val
)
1447 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK
;
1450 #define REG_A3XX_VPC_ATTR 0x00002280
1451 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x00000fff
1452 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
1453 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val
)
1455 return ((val
) << A3XX_VPC_ATTR_TOTALATTR__SHIFT
) & A3XX_VPC_ATTR_TOTALATTR__MASK
;
1457 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
1458 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1459 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val
)
1461 return ((val
) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT
) & A3XX_VPC_ATTR_THRDASSIGN__MASK
;
1463 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000
1464 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28
1465 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val
)
1467 return ((val
) << A3XX_VPC_ATTR_LMSIZE__SHIFT
) & A3XX_VPC_ATTR_LMSIZE__MASK
;
1470 #define REG_A3XX_VPC_PACK 0x00002281
1471 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1472 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1473 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val
)
1475 return ((val
) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT
) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK
;
1477 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1478 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1479 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val
)
1481 return ((val
) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT
) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK
;
1484 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1486 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1488 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1490 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1492 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
1494 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b
1496 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
1497 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
1498 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x000c0000
1499 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
1500 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val
)
1502 return ((val
) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK
;
1504 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
1505 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
1506 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val
)
1508 return ((val
) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK
;
1510 #define A3XX_SP_SP_CTRL_REG_LOMODE__MASK 0x00c00000
1511 #define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT 22
1512 static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val
)
1514 return ((val
) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK
;
1517 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
1518 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1519 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1520 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1522 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK
;
1524 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1525 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1526 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1528 return ((val
) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1530 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1531 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1532 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1533 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1535 return ((val
) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
1537 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1538 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1539 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
1541 return ((val
) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
1543 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1544 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1545 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
1547 return ((val
) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
1549 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1550 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1551 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
1553 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
;
1555 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1556 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1557 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
1558 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
1559 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val
)
1561 return ((val
) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK
;
1564 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5
1565 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
1566 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1567 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
1569 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK
;
1571 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
1572 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
1573 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
1575 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
1577 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000
1578 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1579 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
1581 return ((val
) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
1584 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6
1585 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1586 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1587 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val
)
1589 return ((val
) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK
;
1591 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1592 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1593 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val
)
1595 return ((val
) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK
;
1597 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1598 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1599 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val
)
1601 return ((val
) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT
) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK
;
1604 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
1606 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
1607 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1608 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1609 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val
)
1611 return ((val
) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_A_REGID__MASK
;
1613 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1614 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1615 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val
)
1617 return ((val
) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK
;
1619 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1620 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1621 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val
)
1623 return ((val
) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_B_REGID__MASK
;
1625 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1626 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1627 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val
)
1629 return ((val
) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK
;
1632 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
1634 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
1635 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1636 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1637 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val
)
1639 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
;
1641 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1642 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1643 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val
)
1645 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
;
1647 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1648 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1649 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val
)
1651 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
;
1653 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1654 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1655 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val
)
1657 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
;
1660 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
1661 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1662 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1663 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
1665 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
1667 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1668 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1669 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
1671 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
1674 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
1676 #define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG 0x000022d6
1678 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
1680 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
1682 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
1683 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
1684 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
1685 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
1687 return ((val
) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK
;
1690 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0
1691 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1692 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1693 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1695 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK
;
1697 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1698 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1699 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1701 return ((val
) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1703 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1704 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1705 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1706 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1708 return ((val
) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
1710 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1711 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1712 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
1714 return ((val
) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
1716 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1717 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1718 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
1720 return ((val
) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
1722 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1723 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1724 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
1726 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
;
1728 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1729 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1730 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
1731 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
1732 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val
)
1734 return ((val
) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK
;
1737 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1
1738 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
1739 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1740 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
1742 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK
;
1744 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
1745 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
1746 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
1748 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
1750 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
1751 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
1752 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
1754 return ((val
) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
1756 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
1757 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
1758 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val
)
1760 return ((val
) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT
) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK
;
1763 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
1764 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1765 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1766 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
1768 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
1770 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1771 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1772 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
1774 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
1777 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
1779 #define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG 0x000022e4
1781 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
1783 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
1785 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
1787 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
1789 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
1791 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
1793 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
1794 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1795 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
1796 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val
)
1798 return ((val
) << A3XX_SP_FS_MRT_REG_REGID__SHIFT
) & A3XX_SP_FS_MRT_REG_REGID__MASK
;
1800 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1802 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
1804 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
1805 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
1806 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
1807 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val
)
1809 return ((val
) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT
) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK
;
1812 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff
1813 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
1814 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0
1815 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
1817 return ((val
) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK
;
1820 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340
1821 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
1822 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
1823 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
1825 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
1827 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
1828 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
1829 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
1831 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
1833 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
1834 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
1835 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
1837 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK
;
1840 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341
1842 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342
1843 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
1844 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
1845 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
1847 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
1849 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
1850 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
1851 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
1853 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
1855 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
1856 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
1857 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
1859 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK
;
1862 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343
1864 #define REG_A3XX_VBIF_CLKON 0x00003001
1866 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c
1868 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d
1870 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e
1872 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c
1874 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d
1876 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1878 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1880 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1882 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030
1884 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031
1886 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034
1888 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035
1890 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036
1892 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c
1894 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1896 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058
1898 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e
1900 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
1902 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01
1903 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1904 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1905 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val
)
1907 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT
) & A3XX_VSC_BIN_SIZE_WIDTH__MASK
;
1909 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1910 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1911 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val
)
1913 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT
) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK
;
1916 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
1918 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
1920 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
1921 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
1922 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
1923 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val
)
1925 return ((val
) << A3XX_VSC_PIPE_CONFIG_X__SHIFT
) & A3XX_VSC_PIPE_CONFIG_X__MASK
;
1927 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00
1928 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10
1929 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val
)
1931 return ((val
) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT
) & A3XX_VSC_PIPE_CONFIG_Y__MASK
;
1933 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000
1934 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20
1935 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val
)
1937 return ((val
) << A3XX_VSC_PIPE_CONFIG_W__SHIFT
) & A3XX_VSC_PIPE_CONFIG_W__MASK
;
1939 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000
1940 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24
1941 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val
)
1943 return ((val
) << A3XX_VSC_PIPE_CONFIG_H__SHIFT
) & A3XX_VSC_PIPE_CONFIG_H__MASK
;
1946 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0
) { return 0x00000c07 + 0x3*i0
; }
1948 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0
) { return 0x00000c08 + 0x3*i0
; }
1950 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
1952 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
1954 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
1956 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
1958 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
1960 #define REG_A3XX_UNKNOWN_0C81 0x00000c81
1962 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
1964 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
1966 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
1968 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
1970 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
1972 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
1974 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0
) { return 0x00000ca1 + 0x4*i0
; }
1976 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0
) { return 0x00000ca2 + 0x4*i0
; }
1978 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0
) { return 0x00000ca3 + 0x4*i0
; }
1980 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
1982 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
1984 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
1986 #define REG_A3XX_RB_WINDOW_SIZE 0x00000ce0
1987 #define A3XX_RB_WINDOW_SIZE_WIDTH__MASK 0x00003fff
1988 #define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT 0
1989 static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val
)
1991 return ((val
) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT
) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK
;
1993 #define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK 0x0fffc000
1994 #define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT 14
1995 static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val
)
1997 return ((val
) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT
) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK
;
2000 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
2002 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
2004 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
2006 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
2008 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
2010 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
2012 #define REG_A3XX_UNKNOWN_0E43 0x00000e43
2014 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
2016 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
2018 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
2020 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
2022 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
2024 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
2026 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
2028 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
2030 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
2032 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
2034 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
2036 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
2038 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
2040 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
2041 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
2042 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
2043 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val
)
2045 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK
;
2048 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1
2049 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff
2050 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0
2051 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val
)
2053 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK
;
2055 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000
2056 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28
2057 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val
)
2059 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK
;
2061 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
2063 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
2065 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
2067 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6
2069 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7
2071 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8
2073 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9
2075 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca
2077 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb
2079 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0
2081 #define REG_A3XX_UNKNOWN_0F03 0x00000f03
2083 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
2085 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
2087 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
2089 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
2091 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
2093 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
2095 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
2097 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
2099 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd
2101 #define REG_A3XX_TEX_SAMP_0 0x00000000
2102 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
2103 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
2104 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
2105 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val
)
2107 return ((val
) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT
) & A3XX_TEX_SAMP_0_XY_MAG__MASK
;
2109 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030
2110 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4
2111 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val
)
2113 return ((val
) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT
) & A3XX_TEX_SAMP_0_XY_MIN__MASK
;
2115 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0
2116 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6
2117 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val
)
2119 return ((val
) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_S__MASK
;
2121 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00
2122 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9
2123 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val
)
2125 return ((val
) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_T__MASK
;
2127 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000
2128 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12
2129 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val
)
2131 return ((val
) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_R__MASK
;
2133 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
2135 #define REG_A3XX_TEX_SAMP_1 0x00000001
2137 #define REG_A3XX_TEX_CONST_0 0x00000000
2138 #define A3XX_TEX_CONST_0_TILED 0x00000001
2139 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2140 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2141 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val
)
2143 return ((val
) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_X__MASK
;
2145 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2146 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2147 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val
)
2149 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Y__MASK
;
2151 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2152 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2153 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val
)
2155 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Z__MASK
;
2157 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2158 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2159 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val
)
2161 return ((val
) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_W__MASK
;
2163 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2164 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2165 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val
)
2167 return ((val
) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT
) & A3XX_TEX_CONST_0_MIPLVLS__MASK
;
2169 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2170 #define A3XX_TEX_CONST_0_FMT__SHIFT 22
2171 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val
)
2173 return ((val
) << A3XX_TEX_CONST_0_FMT__SHIFT
) & A3XX_TEX_CONST_0_FMT__MASK
;
2175 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
2176 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30
2177 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val
)
2179 return ((val
) << A3XX_TEX_CONST_0_TYPE__SHIFT
) & A3XX_TEX_CONST_0_TYPE__MASK
;
2182 #define REG_A3XX_TEX_CONST_1 0x00000001
2183 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
2184 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0
2185 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val
)
2187 return ((val
) << A3XX_TEX_CONST_1_HEIGHT__SHIFT
) & A3XX_TEX_CONST_1_HEIGHT__MASK
;
2189 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000
2190 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14
2191 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val
)
2193 return ((val
) << A3XX_TEX_CONST_1_WIDTH__SHIFT
) & A3XX_TEX_CONST_1_WIDTH__MASK
;
2195 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000
2196 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28
2197 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val
)
2199 return ((val
) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT
) & A3XX_TEX_CONST_1_FETCHSIZE__MASK
;
2202 #define REG_A3XX_TEX_CONST_2 0x00000002
2203 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff
2204 #define A3XX_TEX_CONST_2_INDX__SHIFT 0
2205 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val
)
2207 return ((val
) << A3XX_TEX_CONST_2_INDX__SHIFT
) & A3XX_TEX_CONST_2_INDX__MASK
;
2209 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000
2210 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12
2211 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val
)
2213 return ((val
) << A3XX_TEX_CONST_2_PITCH__SHIFT
) & A3XX_TEX_CONST_2_PITCH__MASK
;
2215 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2216 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30
2217 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val
)
2219 return ((val
) << A3XX_TEX_CONST_2_SWAP__SHIFT
) & A3XX_TEX_CONST_2_SWAP__MASK
;
2222 #define REG_A3XX_TEX_CONST_3 0x00000003
2225 #endif /* A3XX_XML */