4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-06 12:50:15)
16 - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-09 15:24:38)
18 Copyright (C) 2013 by the following authors:
19 - Rob Clark <robdclark@gmail.com> (robclark)
21 Permission is hereby granted, free of charge, to any person obtaining
22 a copy of this software and associated documentation files (the
23 "Software"), to deal in the Software without restriction, including
24 without limitation the rights to use, copy, modify, merge, publish,
25 distribute, sublicense, and/or sell copies of the Software, and to
26 permit persons to whom the Software is furnished to do so, subject to
27 the following conditions:
29 The above copyright notice and this permission notice (including the
30 next paragraph) shall be included in all copies or substantial
31 portions of the Software.
33 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
35 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
36 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
37 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
38 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
39 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
43 enum a3xx_render_mode
{
44 RB_RENDERING_PASS
= 0,
54 enum a3xx_threadmode
{
59 enum a3xx_instrbuffermode
{
63 enum a3xx_threadsize
{
68 enum a3xx_state_block_id
{
69 HLSQ_BLOCK_ID_TP_TEX
= 2,
70 HLSQ_BLOCK_ID_TP_MIPMAP
= 3,
71 HLSQ_BLOCK_ID_SP_VS
= 4,
72 HLSQ_BLOCK_ID_SP_FS
= 6,
75 enum a3xx_cache_opcode
{
82 VFMT_FLOAT_32_32_32
= 2,
83 VFMT_FLOAT_32_32_32_32
= 3,
86 VFMT_FLOAT_16_16_16
= 6,
87 VFMT_FLOAT_16_16_16_16
= 7,
90 VFMT_FIXED_32_32_32
= 10,
91 VFMT_FIXED_32_32_32_32
= 11,
93 VFMT_SHORT_16_16
= 17,
94 VFMT_SHORT_16_16_16
= 18,
95 VFMT_SHORT_16_16_16_16
= 19,
97 VFMT_USHORT_16_16
= 21,
98 VFMT_USHORT_16_16_16
= 22,
99 VFMT_USHORT_16_16_16_16
= 23,
100 VFMT_NORM_SHORT_16
= 24,
101 VFMT_NORM_SHORT_16_16
= 25,
102 VFMT_NORM_SHORT_16_16_16
= 26,
103 VFMT_NORM_SHORT_16_16_16_16
= 27,
104 VFMT_NORM_USHORT_16
= 28,
105 VFMT_NORM_USHORT_16_16
= 29,
106 VFMT_NORM_USHORT_16_16_16
= 30,
107 VFMT_NORM_USHORT_16_16_16_16
= 31,
110 VFMT_UBYTE_8_8_8
= 42,
111 VFMT_UBYTE_8_8_8_8
= 43,
112 VFMT_NORM_UBYTE_8
= 44,
113 VFMT_NORM_UBYTE_8_8
= 45,
114 VFMT_NORM_UBYTE_8_8_8
= 46,
115 VFMT_NORM_UBYTE_8_8_8_8
= 47,
118 VFMT_BYTE_8_8_8
= 50,
119 VFMT_BYTE_8_8_8_8
= 51,
120 VFMT_NORM_BYTE_8
= 52,
121 VFMT_NORM_BYTE_8_8
= 53,
122 VFMT_NORM_BYTE_8_8_8
= 54,
123 VFMT_NORM_BYTE_8_8_8_8
= 55,
124 VFMT_UINT_10_10_10_2
= 60,
125 VFMT_NORM_UINT_10_10_10_2
= 61,
126 VFMT_INT_10_10_10_2
= 62,
127 VFMT_NORM_INT_10_10_10_2
= 63,
131 TFMT_NORM_USHORT_565
= 4,
132 TFMT_NORM_USHORT_5551
= 6,
133 TFMT_NORM_USHORT_4444
= 7,
134 TFMT_NORM_UINT_X8Z24
= 10,
135 TFMT_NORM_UINT_NV12_UV_TILED
= 17,
136 TFMT_NORM_UINT_NV12_Y_TILED
= 19,
137 TFMT_NORM_UINT_NV12_UV
= 21,
138 TFMT_NORM_UINT_NV12_Y
= 23,
139 TFMT_NORM_UINT_I420_Y
= 24,
140 TFMT_NORM_UINT_I420_U
= 26,
141 TFMT_NORM_UINT_I420_V
= 27,
142 TFMT_NORM_UINT_2_10_10_10
= 41,
143 TFMT_NORM_UINT_A8
= 44,
144 TFMT_NORM_UINT_L8_A8
= 47,
145 TFMT_NORM_UINT_8
= 48,
146 TFMT_NORM_UINT_8_8
= 49,
147 TFMT_NORM_UINT_8_8_8
= 50,
148 TFMT_NORM_UINT_8_8_8_8
= 51,
150 TFMT_FLOAT_16_16
= 65,
151 TFMT_FLOAT_16_16_16_16
= 67,
153 TFMT_FLOAT_32_32
= 85,
154 TFMT_FLOAT_32_32_32_32
= 87,
157 enum a3xx_tex_fetchsize
{
166 enum a3xx_color_fmt
{
168 RB_R8G8B8A8_UNORM
= 8,
173 enum a3xx_color_swap
{
180 enum a3xx_msaa_samples
{
186 enum a3xx_sp_perfcounter_select
{
187 SP_FS_CFLOW_INSTRUCTIONS
= 12,
188 SP_FS_FULL_ALU_INSTRUCTIONS
= 14,
189 SP0_ICL1_MISSES
= 26,
190 SP_ALU_ACTIVE_CYCLES
= 29,
193 enum adreno_rb_copy_control_mode
{
195 RB_COPY_DEPTH_STENCIL
= 5,
198 enum a3xx_tex_filter
{
199 A3XX_TEX_NEAREST
= 0,
203 enum a3xx_tex_clamp
{
205 A3XX_TEX_CLAMP_TO_EDGE
= 1,
206 A3XX_TEX_MIRROR_REPEAT
= 2,
207 A3XX_TEX_CLAMP_NONE
= 3,
226 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
227 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
228 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
229 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
230 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
231 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
232 #define A3XX_INT0_VFD_ERROR 0x00000040
233 #define A3XX_INT0_CP_SW_INT 0x00000080
234 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
235 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
236 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
237 #define A3XX_INT0_CP_HW_FAULT 0x00000800
238 #define A3XX_INT0_CP_DMA 0x00001000
239 #define A3XX_INT0_CP_IB2_INT 0x00002000
240 #define A3XX_INT0_CP_IB1_INT 0x00004000
241 #define A3XX_INT0_CP_RB_INT 0x00008000
242 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
243 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000
244 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000
245 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000
246 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
247 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
248 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000
249 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
250 #define REG_A3XX_RBBM_HW_VERSION 0x00000000
252 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001
254 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002
256 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010
258 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012
260 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018
262 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020
264 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021
266 #define REG_A3XX_RBBM_AHB_CMD 0x00000022
268 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027
270 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
272 #define REG_A3XX_RBBM_STATUS 0x00000030
273 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
274 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
275 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
276 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
277 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
278 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
279 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
280 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
281 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
282 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
283 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
284 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
285 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
286 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
287 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
288 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
289 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
290 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
291 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
292 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
293 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
295 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
297 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
299 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051
301 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054
303 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057
305 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
307 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
309 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063
311 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
313 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
315 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
317 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
319 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
321 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
323 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
325 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
327 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
329 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
331 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
333 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
335 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
337 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
339 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
341 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
343 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
345 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
347 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
349 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
351 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
353 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
355 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
357 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
359 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
361 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
363 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
365 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
367 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
369 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
371 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
373 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
375 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
377 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
379 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
381 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
383 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
385 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
387 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
389 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
391 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
393 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
395 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
397 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
399 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
401 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
403 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
405 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
407 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
409 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
411 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
413 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
415 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
417 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
419 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
421 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
423 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
425 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
427 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
429 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
431 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
433 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
435 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
437 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
439 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
441 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
443 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
445 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
447 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
449 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
451 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
453 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
455 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
457 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
459 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
461 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
463 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
465 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
467 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
469 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
471 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
473 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
475 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
477 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
479 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
481 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
483 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
485 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
487 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
489 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
491 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
493 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
495 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
497 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
499 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
501 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
503 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
505 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
507 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
509 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100
511 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
513 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
515 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9
517 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca
519 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc
521 #define REG_A3XX_CP_ROQ_DATA 0x000001cd
523 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1
525 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2
527 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3
529 #define REG_A3XX_CP_MEQ_ADDR 0x000001da
531 #define REG_A3XX_CP_MEQ_DATA 0x000001db
533 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
535 #define REG_A3XX_CP_HW_FAULT 0x0000045c
537 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
539 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
541 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
543 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
545 #define REG_A3XX_CP_AHB_FAULT 0x0000054d
547 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
548 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
549 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
550 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
551 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
552 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
553 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
555 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
556 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
557 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
558 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val
)
560 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK
;
562 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
563 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
564 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val
)
566 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK
;
569 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048
570 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
571 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
572 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val
)
574 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK
;
577 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049
578 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
579 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
580 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val
)
582 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_XSCALE__MASK
;
585 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a
586 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
587 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
588 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val
)
590 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK
;
593 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b
594 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
595 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
596 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val
)
598 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_YSCALE__MASK
;
601 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c
602 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
603 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
604 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val
)
606 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK
;
609 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d
610 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
611 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
612 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val
)
614 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK
;
617 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
619 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
621 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
622 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
623 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
624 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val
)
626 return ((((uint32_t)(val
* 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK
;
629 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
630 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
631 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
632 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val
)
634 return ((((uint32_t)(val
* 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
637 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
638 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
639 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
640 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
641 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
642 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
643 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val
)
645 return ((((uint32_t)(val
* 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT
) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK
;
647 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
649 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072
650 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0
651 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4
652 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
654 return ((val
) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK
;
656 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00
657 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8
658 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val
)
660 return ((val
) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT
) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK
;
662 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
663 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
664 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val
)
666 return ((val
) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK
;
669 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074
670 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
671 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
672 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
673 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val
)
675 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
;
677 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
678 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
679 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val
)
681 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
;
684 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075
685 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
686 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
687 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
688 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val
)
690 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
;
692 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
693 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
694 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val
)
696 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
;
699 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079
700 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
701 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
702 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
703 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
705 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
;
707 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
708 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
709 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
711 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
;
714 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a
715 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
716 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
717 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
718 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
720 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
;
722 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
723 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
724 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
726 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
;
729 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0
730 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080
731 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700
732 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8
733 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
735 return ((val
) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT
) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK
;
737 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
738 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
740 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
741 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
742 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
743 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val
)
745 return ((val
>> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT
) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK
;
747 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
748 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
749 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
750 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
751 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
752 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val
)
754 return ((val
) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT
) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK
;
757 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
758 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
759 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000
760 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12
761 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val
)
763 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK
;
765 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000
766 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16
767 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val
)
769 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK
;
772 #define REG_A3XX_RB_ALPHA_REF 0x000020c3
773 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
774 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
775 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val
)
777 return ((val
) << A3XX_RB_ALPHA_REF_UINT__SHIFT
) & A3XX_RB_ALPHA_REF_UINT__MASK
;
779 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
780 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
781 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val
)
783 return ((util_float_to_half(val
)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT
) & A3XX_RB_ALPHA_REF_FLOAT__MASK
;
786 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
788 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
789 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
790 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
791 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
792 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
793 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
794 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(uint32_t val
)
796 return ((val
) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK
;
798 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000
799 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12
800 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val
)
802 return ((val
) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT
) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
;
804 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
805 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
806 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val
)
808 return ((val
) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
811 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0
) { return 0x000020c5 + 0x4*i0
; }
812 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
813 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
814 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val
)
816 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
;
818 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
819 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
820 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val
)
822 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
;
824 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00
825 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10
826 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
828 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
;
830 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000
831 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
832 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val
)
834 return ((val
>> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK
;
837 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0
) { return 0x000020c6 + 0x4*i0
; }
838 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
839 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
840 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val
)
842 return ((val
>> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT
) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK
;
845 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0
) { return 0x000020c7 + 0x4*i0
; }
846 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
847 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
848 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val
)
850 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
;
852 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
853 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
854 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val
)
856 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
;
858 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
859 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
860 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val
)
862 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
;
864 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
865 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
866 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val
)
868 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
;
870 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
871 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
872 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val
)
874 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
;
876 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
877 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
878 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val
)
880 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
;
882 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
884 #define REG_A3XX_RB_BLEND_RED 0x000020e4
885 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
886 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0
887 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val
)
889 return ((val
) << A3XX_RB_BLEND_RED_UINT__SHIFT
) & A3XX_RB_BLEND_RED_UINT__MASK
;
891 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
892 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
893 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val
)
895 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT
) & A3XX_RB_BLEND_RED_FLOAT__MASK
;
898 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5
899 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
900 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
901 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val
)
903 return ((val
) << A3XX_RB_BLEND_GREEN_UINT__SHIFT
) & A3XX_RB_BLEND_GREEN_UINT__MASK
;
905 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
906 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
907 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val
)
909 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT
) & A3XX_RB_BLEND_GREEN_FLOAT__MASK
;
912 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6
913 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
914 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
915 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val
)
917 return ((val
) << A3XX_RB_BLEND_BLUE_UINT__SHIFT
) & A3XX_RB_BLEND_BLUE_UINT__MASK
;
919 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
920 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
921 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val
)
923 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT
) & A3XX_RB_BLEND_BLUE_FLOAT__MASK
;
926 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
927 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
928 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
929 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val
)
931 return ((val
) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT
) & A3XX_RB_BLEND_ALPHA_UINT__MASK
;
933 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
934 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
935 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val
)
937 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT
) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK
;
940 #define REG_A3XX_UNKNOWN_20E8 0x000020e8
942 #define REG_A3XX_UNKNOWN_20E9 0x000020e9
944 #define REG_A3XX_UNKNOWN_20EA 0x000020ea
946 #define REG_A3XX_UNKNOWN_20EB 0x000020eb
948 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec
949 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
950 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
951 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val
)
953 return ((val
) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT
) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK
;
955 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
956 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
957 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val
)
959 return ((val
) << A3XX_RB_COPY_CONTROL_MODE__SHIFT
) & A3XX_RB_COPY_CONTROL_MODE__MASK
;
961 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xfffffc00
962 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 10
963 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val
)
965 return ((val
>> 10) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT
) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK
;
968 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
969 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0
970 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
971 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val
)
973 return ((val
>> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT
) & A3XX_RB_COPY_DEST_BASE_BASE__MASK
;
976 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
977 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
978 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
979 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val
)
981 return ((val
>> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT
) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK
;
984 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
985 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003
986 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0
987 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val
)
989 return ((val
) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_TILE__MASK
;
991 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
992 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
993 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val
)
995 return ((val
) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK
;
997 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
998 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
999 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val
)
1001 return ((val
) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT
) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK
;
1003 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1004 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1005 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val
)
1007 return ((val
) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK
;
1009 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1010 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1011 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val
)
1013 return ((val
) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT
) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK
;
1016 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
1017 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1018 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1019 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
1020 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1021 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1022 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val
)
1024 return ((val
) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT
) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK
;
1026 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1027 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1029 #define REG_A3XX_UNKNOWN_2101 0x00002101
1031 #define REG_A3XX_RB_DEPTH_INFO 0x00002102
1032 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
1033 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1034 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val
)
1036 return ((val
) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
;
1038 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800
1039 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
1040 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val
)
1042 return ((val
>> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
1045 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103
1046 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff
1047 #define A3XX_RB_DEPTH_PITCH__SHIFT 0
1048 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val
)
1050 return ((val
>> 3) << A3XX_RB_DEPTH_PITCH__SHIFT
) & A3XX_RB_DEPTH_PITCH__MASK
;
1053 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
1054 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1055 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1056 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1057 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1058 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1059 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val
)
1061 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK
;
1063 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1064 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1065 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val
)
1067 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK
;
1069 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1070 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1071 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val
)
1073 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK
;
1075 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1076 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1077 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val
)
1079 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK
;
1081 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1082 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1083 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val
)
1085 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
;
1087 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1088 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1089 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val
)
1091 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
;
1093 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1094 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1095 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val
)
1097 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
;
1099 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1100 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1101 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val
)
1103 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
;
1106 #define REG_A3XX_UNKNOWN_2105 0x00002105
1108 #define REG_A3XX_UNKNOWN_2106 0x00002106
1110 #define REG_A3XX_UNKNOWN_2107 0x00002107
1112 #define REG_A3XX_RB_STENCILREFMASK 0x00002108
1113 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1114 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1115 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
1117 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK
;
1119 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1120 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1121 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
1123 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
1125 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1126 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1127 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
1129 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
1132 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109
1133 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1134 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1135 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val
)
1137 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
;
1139 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1140 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1141 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val
)
1143 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
;
1145 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1146 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1147 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val
)
1149 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
;
1152 #define REG_A3XX_PA_SC_WINDOW_OFFSET 0x0000210e
1153 #define A3XX_PA_SC_WINDOW_OFFSET_X__MASK 0x0000ffff
1154 #define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0
1155 static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val
)
1157 return ((val
) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT
) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK
;
1159 #define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK 0xffff0000
1160 #define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16
1161 static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val
)
1163 return ((val
) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT
) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK
;
1166 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1168 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
1170 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec
1171 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
1172 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0
1173 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val
)
1175 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK
;
1177 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0
1178 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5
1179 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val
)
1181 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK
;
1183 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700
1184 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8
1185 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val
)
1187 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK
;
1189 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1191 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1193 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
1194 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
1195 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1196 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val
)
1198 return ((val
) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
;
1200 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1201 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1202 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1203 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1204 #define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE 0x08000000
1205 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1206 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1207 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1208 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1210 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1211 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
1212 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1213 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val
)
1215 return ((val
) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK
;
1217 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1218 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
1220 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1221 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1222 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1223 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val
)
1225 return ((val
) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT
) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK
;
1228 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1230 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1231 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1232 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1233 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1235 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK
;
1237 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1238 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1239 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1241 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1243 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1244 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1245 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1247 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK
;
1250 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1251 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1252 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1253 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1255 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK
;
1257 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1258 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1259 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1261 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1263 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1264 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1265 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1267 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK
;
1270 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1271 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1272 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1273 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1275 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK
;
1277 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1278 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1279 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1281 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK
;
1284 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1285 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1286 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1287 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1289 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK
;
1291 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1292 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1293 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1295 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK
;
1298 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1300 #define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b
1302 #define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c
1304 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
1306 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212
1308 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
1310 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215
1312 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
1314 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
1316 #define REG_A3XX_VFD_CONTROL_0 0x00002240
1317 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff
1318 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1319 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val
)
1321 return ((val
) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT
) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK
;
1323 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000
1324 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18
1325 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val
)
1327 return ((val
) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT
) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK
;
1329 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000
1330 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22
1331 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val
)
1333 return ((val
) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK
;
1335 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1336 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1337 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val
)
1339 return ((val
) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK
;
1342 #define REG_A3XX_VFD_CONTROL_1 0x00002241
1343 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1344 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1345 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val
)
1347 return ((val
) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT
) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK
;
1349 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1350 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1351 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val
)
1353 return ((val
) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK
;
1355 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1356 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1357 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val
)
1359 return ((val
) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4INST__MASK
;
1362 #define REG_A3XX_VFD_INDEX_MIN 0x00002242
1364 #define REG_A3XX_VFD_INDEX_MAX 0x00002243
1366 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244
1368 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1370 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1372 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1373 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1374 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1375 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val
)
1377 return ((val
) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK
;
1379 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1380 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1381 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val
)
1383 return ((val
) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK
;
1385 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000
1386 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000
1387 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18
1388 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val
)
1390 return ((val
) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK
;
1392 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000
1393 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24
1394 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val
)
1396 return ((val
) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK
;
1399 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0
) { return 0x00002247 + 0x2*i0
; }
1401 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1403 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1404 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1405 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1406 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val
)
1408 return ((val
) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT
) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK
;
1410 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1411 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1412 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1413 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val
)
1415 return ((val
) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT
) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK
;
1417 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1418 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1419 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val
)
1421 return ((val
) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT
) & A3XX_VFD_DECODE_INSTR_REGID__MASK
;
1423 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1424 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1425 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val
)
1427 return ((val
) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT
) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK
;
1429 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1430 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1432 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e
1433 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f
1434 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0
1435 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val
)
1437 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK
;
1439 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00
1440 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8
1441 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val
)
1443 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK
;
1446 #define REG_A3XX_VPC_ATTR 0x00002280
1447 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x00000fff
1448 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
1449 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val
)
1451 return ((val
) << A3XX_VPC_ATTR_TOTALATTR__SHIFT
) & A3XX_VPC_ATTR_TOTALATTR__MASK
;
1453 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
1454 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1455 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val
)
1457 return ((val
) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT
) & A3XX_VPC_ATTR_THRDASSIGN__MASK
;
1459 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000
1460 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28
1461 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val
)
1463 return ((val
) << A3XX_VPC_ATTR_LMSIZE__SHIFT
) & A3XX_VPC_ATTR_LMSIZE__MASK
;
1466 #define REG_A3XX_VPC_PACK 0x00002281
1467 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1468 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1469 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val
)
1471 return ((val
) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT
) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK
;
1473 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1474 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1475 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val
)
1477 return ((val
) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT
) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK
;
1480 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1482 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1484 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1486 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1488 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
1490 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b
1492 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
1493 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
1494 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x000c0000
1495 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
1496 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val
)
1498 return ((val
) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK
;
1500 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
1501 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
1502 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val
)
1504 return ((val
) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK
;
1506 #define A3XX_SP_SP_CTRL_REG_LOMODE__MASK 0x00c00000
1507 #define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT 22
1508 static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val
)
1510 return ((val
) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK
;
1513 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
1514 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1515 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1516 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1518 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK
;
1520 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1521 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1522 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1524 return ((val
) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1526 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1527 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1528 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1529 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1531 return ((val
) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
1533 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1534 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1535 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
1537 return ((val
) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
1539 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1540 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1541 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
1543 return ((val
) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
1545 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1546 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1547 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
1549 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
;
1551 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1552 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1553 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
1554 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
1555 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val
)
1557 return ((val
) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK
;
1560 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5
1561 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
1562 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1563 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
1565 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK
;
1567 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
1568 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
1569 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
1571 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
1573 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000
1574 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1575 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
1577 return ((val
) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
1580 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6
1581 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1582 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1583 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val
)
1585 return ((val
) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK
;
1587 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1588 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1589 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val
)
1591 return ((val
) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK
;
1593 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1594 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1595 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val
)
1597 return ((val
) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT
) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK
;
1600 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
1602 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
1603 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1604 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1605 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val
)
1607 return ((val
) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_A_REGID__MASK
;
1609 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1610 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1611 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val
)
1613 return ((val
) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK
;
1615 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1616 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1617 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val
)
1619 return ((val
) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_B_REGID__MASK
;
1621 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1622 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1623 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val
)
1625 return ((val
) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK
;
1628 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
1630 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
1631 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1632 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1633 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val
)
1635 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
;
1637 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1638 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1639 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val
)
1641 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
;
1643 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1644 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1645 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val
)
1647 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
;
1649 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1650 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1651 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val
)
1653 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
;
1656 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
1657 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1658 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1659 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
1661 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
1663 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1664 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1665 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
1667 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
1670 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
1672 #define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG 0x000022d6
1674 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
1676 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
1678 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
1679 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
1680 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
1681 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
1683 return ((val
) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK
;
1686 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0
1687 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1688 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1689 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1691 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK
;
1693 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1694 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1695 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1697 return ((val
) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1699 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1700 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1701 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1702 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1704 return ((val
) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
1706 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1707 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1708 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
1710 return ((val
) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
1712 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1713 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1714 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
1716 return ((val
) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
1718 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1719 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1720 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
1722 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
;
1724 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1725 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1726 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
1727 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
1728 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val
)
1730 return ((val
) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK
;
1733 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1
1734 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
1735 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1736 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
1738 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK
;
1740 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
1741 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
1742 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
1744 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
1746 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
1747 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
1748 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
1750 return ((val
) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
1752 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
1753 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
1754 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val
)
1756 return ((val
) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT
) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK
;
1759 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
1760 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1761 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1762 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
1764 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
1766 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1767 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1768 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
1770 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
1773 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
1775 #define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG 0x000022e4
1777 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
1779 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
1781 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
1783 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
1785 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
1787 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
1789 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
1790 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1791 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
1792 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val
)
1794 return ((val
) << A3XX_SP_FS_MRT_REG_REGID__SHIFT
) & A3XX_SP_FS_MRT_REG_REGID__MASK
;
1796 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1798 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
1800 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
1801 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
1802 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
1803 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val
)
1805 return ((val
) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT
) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK
;
1808 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff
1809 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
1810 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0
1811 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
1813 return ((val
) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK
;
1816 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340
1817 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
1818 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
1819 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
1821 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
1823 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
1824 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
1825 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
1827 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
1829 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
1830 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
1831 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
1833 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK
;
1836 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341
1838 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342
1839 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
1840 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
1841 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
1843 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
1845 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
1846 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
1847 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
1849 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
1851 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
1852 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
1853 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
1855 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK
;
1858 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343
1860 #define REG_A3XX_VBIF_CLKON 0x00003001
1862 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c
1864 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d
1866 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e
1868 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c
1870 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d
1872 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1874 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1876 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1878 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030
1880 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031
1882 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034
1884 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035
1886 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036
1888 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c
1890 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1892 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058
1894 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e
1896 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
1898 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01
1899 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1900 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1901 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val
)
1903 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT
) & A3XX_VSC_BIN_SIZE_WIDTH__MASK
;
1905 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1906 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1907 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val
)
1909 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT
) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK
;
1912 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
1914 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
1916 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
1917 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
1918 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
1919 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val
)
1921 return ((val
) << A3XX_VSC_PIPE_CONFIG_X__SHIFT
) & A3XX_VSC_PIPE_CONFIG_X__MASK
;
1923 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00
1924 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10
1925 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val
)
1927 return ((val
) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT
) & A3XX_VSC_PIPE_CONFIG_Y__MASK
;
1929 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000
1930 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20
1931 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val
)
1933 return ((val
) << A3XX_VSC_PIPE_CONFIG_W__SHIFT
) & A3XX_VSC_PIPE_CONFIG_W__MASK
;
1935 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000
1936 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24
1937 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val
)
1939 return ((val
) << A3XX_VSC_PIPE_CONFIG_H__SHIFT
) & A3XX_VSC_PIPE_CONFIG_H__MASK
;
1942 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0
) { return 0x00000c07 + 0x3*i0
; }
1944 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0
) { return 0x00000c08 + 0x3*i0
; }
1946 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
1948 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
1950 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
1952 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
1954 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
1956 #define REG_A3XX_UNKNOWN_0C81 0x00000c81
1958 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
1960 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
1962 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
1964 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
1966 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
1968 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
1970 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0
) { return 0x00000ca1 + 0x4*i0
; }
1972 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0
) { return 0x00000ca2 + 0x4*i0
; }
1974 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0
) { return 0x00000ca3 + 0x4*i0
; }
1976 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
1978 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
1980 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
1982 #define REG_A3XX_RB_WINDOW_SIZE 0x00000ce0
1983 #define A3XX_RB_WINDOW_SIZE_WIDTH__MASK 0x00003fff
1984 #define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT 0
1985 static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val
)
1987 return ((val
) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT
) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK
;
1989 #define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK 0x0fffc000
1990 #define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT 14
1991 static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val
)
1993 return ((val
) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT
) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK
;
1996 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
1998 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
2000 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
2002 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
2004 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
2006 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
2008 #define REG_A3XX_UNKNOWN_0E43 0x00000e43
2010 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
2012 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
2014 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
2016 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
2018 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
2020 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
2022 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
2024 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
2026 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
2028 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
2030 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
2032 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
2034 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
2036 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
2037 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
2038 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
2039 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val
)
2041 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK
;
2044 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1
2045 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff
2046 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0
2047 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val
)
2049 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK
;
2051 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000
2052 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28
2053 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val
)
2055 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK
;
2057 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
2059 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
2061 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
2063 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6
2065 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7
2067 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8
2069 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9
2071 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca
2073 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb
2075 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0
2077 #define REG_A3XX_UNKNOWN_0F03 0x00000f03
2079 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
2081 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
2083 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
2085 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
2087 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
2089 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
2091 #define REG_A3XX_TEX_SAMP_0 0x00000000
2092 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
2093 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
2094 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
2095 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val
)
2097 return ((val
) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT
) & A3XX_TEX_SAMP_0_XY_MAG__MASK
;
2099 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030
2100 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4
2101 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val
)
2103 return ((val
) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT
) & A3XX_TEX_SAMP_0_XY_MIN__MASK
;
2105 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0
2106 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6
2107 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val
)
2109 return ((val
) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_S__MASK
;
2111 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00
2112 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9
2113 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val
)
2115 return ((val
) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_T__MASK
;
2117 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000
2118 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12
2119 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val
)
2121 return ((val
) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_R__MASK
;
2123 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
2125 #define REG_A3XX_TEX_SAMP_1 0x00000001
2127 #define REG_A3XX_TEX_CONST_0 0x00000000
2128 #define A3XX_TEX_CONST_0_TILED 0x00000001
2129 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2130 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2131 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val
)
2133 return ((val
) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_X__MASK
;
2135 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2136 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2137 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val
)
2139 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Y__MASK
;
2141 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2142 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2143 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val
)
2145 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Z__MASK
;
2147 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2148 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2149 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val
)
2151 return ((val
) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_W__MASK
;
2153 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2154 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2155 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val
)
2157 return ((val
) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT
) & A3XX_TEX_CONST_0_MIPLVLS__MASK
;
2159 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2160 #define A3XX_TEX_CONST_0_FMT__SHIFT 22
2161 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val
)
2163 return ((val
) << A3XX_TEX_CONST_0_FMT__SHIFT
) & A3XX_TEX_CONST_0_FMT__MASK
;
2165 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
2166 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30
2167 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val
)
2169 return ((val
) << A3XX_TEX_CONST_0_TYPE__SHIFT
) & A3XX_TEX_CONST_0_TYPE__MASK
;
2172 #define REG_A3XX_TEX_CONST_1 0x00000001
2173 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
2174 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0
2175 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val
)
2177 return ((val
) << A3XX_TEX_CONST_1_HEIGHT__SHIFT
) & A3XX_TEX_CONST_1_HEIGHT__MASK
;
2179 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000
2180 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14
2181 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val
)
2183 return ((val
) << A3XX_TEX_CONST_1_WIDTH__SHIFT
) & A3XX_TEX_CONST_1_WIDTH__MASK
;
2185 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000
2186 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28
2187 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val
)
2189 return ((val
) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT
) & A3XX_TEX_CONST_1_FETCHSIZE__MASK
;
2192 #define REG_A3XX_TEX_CONST_2 0x00000002
2193 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff
2194 #define A3XX_TEX_CONST_2_INDX__SHIFT 0
2195 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val
)
2197 return ((val
) << A3XX_TEX_CONST_2_INDX__SHIFT
) & A3XX_TEX_CONST_2_INDX__MASK
;
2199 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000
2200 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12
2201 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val
)
2203 return ((val
) << A3XX_TEX_CONST_2_PITCH__SHIFT
) & A3XX_TEX_CONST_2_PITCH__MASK
;
2205 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2206 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30
2207 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val
)
2209 return ((val
) << A3XX_TEX_CONST_2_SWAP__SHIFT
) & A3XX_TEX_CONST_2_SWAP__MASK
;
2212 #define REG_A3XX_TEX_CONST_3 0x00000003
2215 #endif /* A3XX_XML */