4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06)
19 Copyright (C) 2013-2015 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
49 enum a3xx_state_block_id
{
50 HLSQ_BLOCK_ID_TP_TEX
= 2,
51 HLSQ_BLOCK_ID_TP_MIPMAP
= 3,
52 HLSQ_BLOCK_ID_SP_VS
= 4,
53 HLSQ_BLOCK_ID_SP_FS
= 6,
56 enum a3xx_cache_opcode
{
63 VFMT_32_32_32_FLOAT
= 2,
64 VFMT_32_32_32_32_FLOAT
= 3,
67 VFMT_16_16_16_FLOAT
= 6,
68 VFMT_16_16_16_16_FLOAT
= 7,
71 VFMT_32_32_32_FIXED
= 10,
72 VFMT_32_32_32_32_FIXED
= 11,
75 VFMT_16_16_16_SINT
= 18,
76 VFMT_16_16_16_16_SINT
= 19,
79 VFMT_16_16_16_UINT
= 22,
80 VFMT_16_16_16_16_UINT
= 23,
82 VFMT_16_16_SNORM
= 25,
83 VFMT_16_16_16_SNORM
= 26,
84 VFMT_16_16_16_16_SNORM
= 27,
86 VFMT_16_16_UNORM
= 29,
87 VFMT_16_16_16_UNORM
= 30,
88 VFMT_16_16_16_16_UNORM
= 31,
91 VFMT_32_32_32_UINT
= 34,
92 VFMT_32_32_32_32_UINT
= 35,
95 VFMT_32_32_32_SINT
= 38,
96 VFMT_32_32_32_32_SINT
= 39,
100 VFMT_8_8_8_8_UINT
= 43,
103 VFMT_8_8_8_UNORM
= 46,
104 VFMT_8_8_8_8_UNORM
= 47,
107 VFMT_8_8_8_SINT
= 50,
108 VFMT_8_8_8_8_SINT
= 51,
111 VFMT_8_8_8_SNORM
= 54,
112 VFMT_8_8_8_8_SNORM
= 55,
113 VFMT_10_10_10_2_UINT
= 60,
114 VFMT_10_10_10_2_UNORM
= 61,
115 VFMT_10_10_10_2_SINT
= 62,
116 VFMT_10_10_10_2_SNORM
= 63,
120 TFMT_5_6_5_UNORM
= 4,
121 TFMT_5_5_5_1_UNORM
= 5,
122 TFMT_4_4_4_4_UNORM
= 7,
124 TFMT_X8Z24_UNORM
= 10,
126 TFMT_NV12_UV_TILED
= 17,
127 TFMT_NV12_Y_TILED
= 19,
134 TFMT_ATC_RGBA_EXPLICIT
= 33,
136 TFMT_ATC_RGBA_INTERPOLATED
= 35,
140 TFMT_10_10_10_2_UNORM
= 41,
141 TFMT_9_9_9_E5_FLOAT
= 42,
142 TFMT_11_11_10_FLOAT
= 43,
144 TFMT_L8_A8_UNORM
= 47,
147 TFMT_8_8_8_UNORM
= 50,
148 TFMT_8_8_8_8_UNORM
= 51,
151 TFMT_8_8_8_SNORM
= 54,
152 TFMT_8_8_8_8_SNORM
= 55,
155 TFMT_8_8_8_UINT
= 58,
156 TFMT_8_8_8_8_UINT
= 59,
159 TFMT_8_8_8_SINT
= 62,
160 TFMT_8_8_8_8_SINT
= 63,
162 TFMT_16_16_FLOAT
= 65,
163 TFMT_16_16_16_16_FLOAT
= 67,
165 TFMT_16_16_UINT
= 69,
166 TFMT_16_16_16_16_UINT
= 71,
168 TFMT_16_16_SINT
= 73,
169 TFMT_16_16_16_16_SINT
= 75,
171 TFMT_16_16_UNORM
= 77,
172 TFMT_16_16_16_16_UNORM
= 79,
174 TFMT_16_16_SNORM
= 81,
175 TFMT_16_16_16_16_SNORM
= 83,
177 TFMT_32_32_FLOAT
= 85,
178 TFMT_32_32_32_32_FLOAT
= 87,
180 TFMT_32_32_UINT
= 89,
181 TFMT_32_32_32_32_UINT
= 91,
183 TFMT_32_32_SINT
= 93,
184 TFMT_32_32_32_32_SINT
= 95,
185 TFMT_ETC2_RG11_SNORM
= 112,
186 TFMT_ETC2_RG11_UNORM
= 113,
187 TFMT_ETC2_R11_SNORM
= 114,
188 TFMT_ETC2_R11_UNORM
= 115,
189 TFMT_ETC2_RGBA8
= 116,
190 TFMT_ETC2_RGB8A1
= 117,
191 TFMT_ETC2_RGB8
= 118,
194 enum a3xx_tex_fetchsize
{
203 enum a3xx_color_fmt
{
205 RB_R5G5B5A1_UNORM
= 1,
206 RB_R4G4B4A4_UNORM
= 3,
208 RB_R8G8B8A8_UNORM
= 8,
209 RB_R8G8B8A8_SNORM
= 9,
210 RB_R8G8B8A8_UINT
= 10,
211 RB_R8G8B8A8_SINT
= 11,
216 RB_R10G10B10A2_UNORM
= 16,
220 RB_R16G16_FLOAT
= 25,
221 RB_R16G16B16A16_FLOAT
= 27,
222 RB_R11G11B10_FLOAT
= 28,
224 RB_R16G16_SNORM
= 33,
225 RB_R16G16B16A16_SNORM
= 35,
227 RB_R16G16_UNORM
= 37,
228 RB_R16G16B16A16_UNORM
= 39,
231 RB_R16G16B16A16_SINT
= 43,
234 RB_R16G16B16A16_UINT
= 47,
236 RB_R32G32_FLOAT
= 49,
237 RB_R32G32B32A32_FLOAT
= 51,
240 RB_R32G32B32A32_SINT
= 55,
243 RB_R32G32B32A32_UINT
= 59,
246 enum a3xx_sp_perfcounter_select
{
247 SP_FS_CFLOW_INSTRUCTIONS
= 12,
248 SP_FS_FULL_ALU_INSTRUCTIONS
= 14,
249 SP0_ICL1_MISSES
= 26,
250 SP_ALU_ACTIVE_CYCLES
= 29,
256 ROP_AND_INVERTED
= 2,
257 ROP_COPY_INVERTED
= 3,
265 ROP_OR_INVERTED
= 11,
272 enum a3xx_rb_blend_opcode
{
273 BLEND_DST_PLUS_SRC
= 0,
274 BLEND_SRC_MINUS_DST
= 1,
275 BLEND_DST_MINUS_SRC
= 2,
276 BLEND_MIN_DST_SRC
= 3,
277 BLEND_MAX_DST_SRC
= 4,
280 enum a3xx_intp_mode
{
285 enum a3xx_repl_mode
{
291 enum a3xx_tex_filter
{
292 A3XX_TEX_NEAREST
= 0,
297 enum a3xx_tex_clamp
{
299 A3XX_TEX_CLAMP_TO_EDGE
= 1,
300 A3XX_TEX_MIRROR_REPEAT
= 2,
301 A3XX_TEX_CLAMP_TO_BORDER
= 3,
302 A3XX_TEX_MIRROR_CLAMP
= 4,
305 enum a3xx_tex_aniso
{
306 A3XX_TEX_ANISO_1
= 0,
307 A3XX_TEX_ANISO_2
= 1,
308 A3XX_TEX_ANISO_4
= 2,
309 A3XX_TEX_ANISO_8
= 3,
310 A3XX_TEX_ANISO_16
= 4,
330 A3XX_TPL1_MSAA1X
= 0,
331 A3XX_TPL1_MSAA2X
= 1,
332 A3XX_TPL1_MSAA4X
= 2,
333 A3XX_TPL1_MSAA8X
= 3,
336 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
337 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
338 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
339 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
340 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
341 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
342 #define A3XX_INT0_VFD_ERROR 0x00000040
343 #define A3XX_INT0_CP_SW_INT 0x00000080
344 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
345 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
346 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
347 #define A3XX_INT0_CP_HW_FAULT 0x00000800
348 #define A3XX_INT0_CP_DMA 0x00001000
349 #define A3XX_INT0_CP_IB2_INT 0x00002000
350 #define A3XX_INT0_CP_IB1_INT 0x00004000
351 #define A3XX_INT0_CP_RB_INT 0x00008000
352 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
353 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000
354 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000
355 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000
356 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
357 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
358 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000
359 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
360 #define REG_A3XX_RBBM_HW_VERSION 0x00000000
362 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001
364 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002
366 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010
368 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012
370 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018
372 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020
374 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021
376 #define REG_A3XX_RBBM_AHB_CMD 0x00000022
378 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027
380 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
382 #define REG_A3XX_RBBM_STATUS 0x00000030
383 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
384 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
385 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
386 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
387 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
388 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
389 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
390 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
391 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
392 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
393 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
394 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
395 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
396 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
397 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
398 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
399 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
400 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
401 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
402 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
403 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
405 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
407 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
409 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
411 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051
413 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054
415 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057
417 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
419 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
421 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
423 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063
425 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
427 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
428 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001
430 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
432 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
434 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
436 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
438 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
440 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
442 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
444 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
446 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
448 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
450 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
452 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
454 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
456 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
458 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
460 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
462 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
464 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
466 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
468 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
470 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
472 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
474 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
476 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
478 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
480 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
482 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
484 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
486 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
488 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
490 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
492 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
494 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
496 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
498 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
500 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
502 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
504 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
506 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
508 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
510 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
512 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
514 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
516 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
518 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
520 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
522 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
524 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
526 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
528 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
530 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
532 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
534 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
536 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
538 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
540 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
542 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
544 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
546 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
548 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
550 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
552 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
554 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
556 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
558 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
560 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
562 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
564 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
566 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
568 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
570 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
572 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
574 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
576 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
578 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
580 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
582 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
584 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
586 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
588 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
590 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
592 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
594 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
596 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
598 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
600 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
602 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
604 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
606 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
608 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
610 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
612 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
614 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
616 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
618 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
620 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
622 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
624 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100
626 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
628 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
630 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9
632 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca
634 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc
636 #define REG_A3XX_CP_ROQ_DATA 0x000001cd
638 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1
640 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2
642 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3
644 #define REG_A3XX_CP_MEQ_ADDR 0x000001da
646 #define REG_A3XX_CP_MEQ_DATA 0x000001db
648 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5
650 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d
652 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
654 #define REG_A3XX_CP_HW_FAULT 0x0000045c
656 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
658 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
660 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
662 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0
) { return 0x00000460 + 0x1*i0
; }
664 #define REG_A3XX_CP_AHB_FAULT 0x0000054d
666 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00
668 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02
670 #define REG_A3XX_TP0_CHICKEN 0x00000e1e
672 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22
674 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23
676 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
677 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
678 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
679 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
680 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
681 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
682 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
683 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000
684 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000
685 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000
687 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
688 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
689 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
690 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val
)
692 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK
;
694 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
695 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
696 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val
)
698 return ((val
) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT
) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK
;
701 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048
702 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
703 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
704 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val
)
706 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK
;
709 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049
710 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
711 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
712 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val
)
714 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_XSCALE__MASK
;
717 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a
718 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
719 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
720 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val
)
722 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK
;
725 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b
726 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
727 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
728 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val
)
730 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_YSCALE__MASK
;
733 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c
734 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
735 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
736 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val
)
738 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT
) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK
;
741 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d
742 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
743 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
744 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val
)
746 return ((fui(val
)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT
) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK
;
749 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
750 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
751 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
752 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val
)
754 return ((((uint32_t)(val
* 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK
;
756 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
757 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
758 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val
)
760 return ((((uint32_t)(val
* 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK
;
763 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
764 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
765 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0
766 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val
)
768 return ((((int32_t)(val
* 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT
) & A3XX_GRAS_SU_POINT_SIZE__MASK
;
771 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
772 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
773 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
774 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val
)
776 return ((((int32_t)(val
* 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK
;
779 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
780 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
781 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
782 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val
)
784 return ((((int32_t)(val
* 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
787 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
788 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
789 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
790 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
791 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
792 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
793 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val
)
795 return ((((int32_t)(val
* 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT
) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK
;
797 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
799 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072
800 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0
801 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4
802 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
804 return ((val
) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK
;
806 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00
807 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8
808 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val
)
810 return ((val
) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT
) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK
;
812 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
813 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
814 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val
)
816 return ((val
) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT
) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK
;
819 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074
820 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
821 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
822 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
823 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val
)
825 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
;
827 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
828 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
829 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val
)
831 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
;
834 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075
835 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
836 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
837 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
838 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val
)
840 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
;
842 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
843 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
844 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val
)
846 return ((val
) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
;
849 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079
850 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
851 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
852 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
853 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
855 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
;
857 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
858 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
859 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
861 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
;
864 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a
865 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
866 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
867 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
868 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
870 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
;
872 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
873 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
874 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
876 return ((val
) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
;
879 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0
880 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080
881 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700
882 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8
883 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val
)
885 return ((val
) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT
) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK
;
887 #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000
888 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12
889 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val
)
891 return ((val
) << A3XX_RB_MODE_CONTROL_MRT__SHIFT
) & A3XX_RB_MODE_CONTROL_MRT__MASK
;
893 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
894 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
896 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
897 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008
898 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
899 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
900 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val
)
902 return ((val
>> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT
) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK
;
904 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
905 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
906 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000
907 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
908 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
909 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
910 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
911 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
912 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
913 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val
)
915 return ((val
) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT
) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK
;
918 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
919 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
920 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000
921 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12
922 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val
)
924 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK
;
926 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000
927 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16
928 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val
)
930 return ((val
) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT
) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK
;
933 #define REG_A3XX_RB_ALPHA_REF 0x000020c3
934 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
935 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
936 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val
)
938 return ((val
) << A3XX_RB_ALPHA_REF_UINT__SHIFT
) & A3XX_RB_ALPHA_REF_UINT__MASK
;
940 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
941 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
942 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val
)
944 return ((util_float_to_half(val
)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT
) & A3XX_RB_ALPHA_REF_FLOAT__MASK
;
947 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
949 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0
) { return 0x000020c4 + 0x4*i0
; }
950 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
951 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
952 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
953 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
954 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
955 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val
)
957 return ((val
) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT
) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK
;
959 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000
960 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12
961 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val
)
963 return ((val
) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT
) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
;
965 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
966 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
967 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val
)
969 return ((val
) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
972 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0
) { return 0x000020c5 + 0x4*i0
; }
973 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
974 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
975 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val
)
977 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
;
979 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
980 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
981 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val
)
983 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
;
985 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00
986 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10
987 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
989 return ((val
) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
;
991 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000
992 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000
993 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
994 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val
)
996 return ((val
>> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT
) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK
;
999 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0
) { return 0x000020c6 + 0x4*i0
; }
1000 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
1001 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
1002 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val
)
1004 return ((val
>> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT
) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK
;
1007 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0
) { return 0x000020c7 + 0x4*i0
; }
1008 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1009 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
1010 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val
)
1012 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
;
1014 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1015 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
1016 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val
)
1018 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
;
1020 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1021 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
1022 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val
)
1024 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
;
1026 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1027 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
1028 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val
)
1030 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
;
1032 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1033 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
1034 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val
)
1036 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
;
1038 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1039 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
1040 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val
)
1042 return ((val
) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
;
1044 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
1046 #define REG_A3XX_RB_BLEND_RED 0x000020e4
1047 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1048 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0
1049 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val
)
1051 return ((val
) << A3XX_RB_BLEND_RED_UINT__SHIFT
) & A3XX_RB_BLEND_RED_UINT__MASK
;
1053 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1054 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
1055 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val
)
1057 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT
) & A3XX_RB_BLEND_RED_FLOAT__MASK
;
1060 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5
1061 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1062 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
1063 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val
)
1065 return ((val
) << A3XX_RB_BLEND_GREEN_UINT__SHIFT
) & A3XX_RB_BLEND_GREEN_UINT__MASK
;
1067 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1068 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1069 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val
)
1071 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT
) & A3XX_RB_BLEND_GREEN_FLOAT__MASK
;
1074 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6
1075 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1076 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
1077 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val
)
1079 return ((val
) << A3XX_RB_BLEND_BLUE_UINT__SHIFT
) & A3XX_RB_BLEND_BLUE_UINT__MASK
;
1081 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1082 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1083 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val
)
1085 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT
) & A3XX_RB_BLEND_BLUE_FLOAT__MASK
;
1088 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
1089 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1090 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1091 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val
)
1093 return ((val
) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT
) & A3XX_RB_BLEND_ALPHA_UINT__MASK
;
1095 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1096 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1097 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val
)
1099 return ((util_float_to_half(val
)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT
) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK
;
1102 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
1104 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9
1106 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea
1108 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb
1110 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec
1111 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1112 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
1113 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val
)
1115 return ((val
) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT
) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK
;
1117 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008
1118 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1119 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
1120 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val
)
1122 return ((val
) << A3XX_RB_COPY_CONTROL_MODE__SHIFT
) & A3XX_RB_COPY_CONTROL_MODE__MASK
;
1124 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1125 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1126 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val
)
1128 return ((val
) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT
) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK
;
1130 #define A3XX_RB_COPY_CONTROL_UNK12 0x00001000
1131 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1132 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
1133 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val
)
1135 return ((val
>> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT
) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK
;
1138 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
1139 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0
1140 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
1141 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val
)
1143 return ((val
>> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT
) & A3XX_RB_COPY_DEST_BASE_BASE__MASK
;
1146 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
1147 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1148 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1149 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val
)
1151 return ((val
>> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT
) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK
;
1154 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
1155 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003
1156 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0
1157 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val
)
1159 return ((val
) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_TILE__MASK
;
1161 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1162 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
1163 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val
)
1165 return ((val
) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT
) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK
;
1167 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1168 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1169 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val
)
1171 return ((val
) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT
) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK
;
1173 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1174 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1175 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val
)
1177 return ((val
) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK
;
1179 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1180 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1181 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val
)
1183 return ((val
) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT
) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK
;
1185 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1186 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1187 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val
)
1189 return ((val
) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT
) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK
;
1192 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
1193 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1194 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1195 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1196 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
1197 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1198 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1199 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val
)
1201 return ((val
) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT
) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK
;
1203 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1204 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1206 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
1208 #define REG_A3XX_RB_DEPTH_INFO 0x00002102
1209 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1210 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1211 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val
)
1213 return ((val
) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK
;
1215 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800
1216 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
1217 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val
)
1219 return ((val
>> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT
) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK
;
1222 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103
1223 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff
1224 #define A3XX_RB_DEPTH_PITCH__SHIFT 0
1225 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val
)
1227 return ((val
>> 3) << A3XX_RB_DEPTH_PITCH__SHIFT
) & A3XX_RB_DEPTH_PITCH__MASK
;
1230 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
1231 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1232 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1233 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1234 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1235 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1236 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val
)
1238 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK
;
1240 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1241 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1242 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val
)
1244 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK
;
1246 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1247 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1248 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val
)
1250 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK
;
1252 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1253 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1254 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val
)
1256 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK
;
1258 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1259 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1260 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val
)
1262 return ((val
) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
;
1264 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1265 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1266 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val
)
1268 return ((val
) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
;
1270 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1271 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1272 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val
)
1274 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
;
1276 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1277 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1278 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val
)
1280 return ((val
) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
;
1283 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
1285 #define REG_A3XX_RB_STENCIL_INFO 0x00002106
1286 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800
1287 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11
1288 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val
)
1290 return ((val
>> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT
) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK
;
1293 #define REG_A3XX_RB_STENCIL_PITCH 0x00002107
1294 #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff
1295 #define A3XX_RB_STENCIL_PITCH__SHIFT 0
1296 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val
)
1298 return ((val
>> 3) << A3XX_RB_STENCIL_PITCH__SHIFT
) & A3XX_RB_STENCIL_PITCH__MASK
;
1301 #define REG_A3XX_RB_STENCILREFMASK 0x00002108
1302 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1303 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1304 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
1306 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK
;
1308 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1309 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1310 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
1312 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
1314 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1315 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1316 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
1318 return ((val
) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
1321 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109
1322 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1323 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1324 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val
)
1326 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK
;
1328 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1329 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1330 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val
)
1332 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK
;
1334 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1335 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1336 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val
)
1338 return ((val
) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT
) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK
;
1341 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c
1342 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002
1344 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e
1345 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff
1346 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0
1347 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val
)
1349 return ((val
) << A3XX_RB_WINDOW_OFFSET_X__SHIFT
) & A3XX_RB_WINDOW_OFFSET_X__MASK
;
1351 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000
1352 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16
1353 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val
)
1355 return ((val
) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT
) & A3XX_RB_WINDOW_OFFSET_Y__MASK
;
1358 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
1359 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001
1360 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1362 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
1364 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114
1366 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
1368 #define REG_A3XX_VGT_BIN_BASE 0x000021e1
1370 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2
1372 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1373 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
1374 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
1375 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val
)
1377 return ((val
) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT
) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK
;
1379 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
1380 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22
1381 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val
)
1383 return ((val
) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT
) & A3XX_PC_VSTREAM_CONTROL_N__MASK
;
1386 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
1388 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec
1389 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
1390 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0
1391 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val
)
1393 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK
;
1395 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0
1396 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5
1397 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val
)
1399 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK
;
1401 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700
1402 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8
1403 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val
)
1405 return ((val
) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT
) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK
;
1407 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
1408 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
1409 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1410 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
1412 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1414 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
1415 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
1416 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1417 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val
)
1419 return ((val
) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
;
1421 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1422 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1423 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1424 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1425 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
1426 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
1427 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val
)
1429 return ((val
) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT
) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK
;
1431 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1432 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1433 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1434 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1436 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1437 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
1438 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1439 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val
)
1441 return ((val
) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT
) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK
;
1443 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1444 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
1445 #define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
1447 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1448 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1449 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1450 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val
)
1452 return ((val
) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT
) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK
;
1455 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1456 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
1457 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
1458 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val
)
1460 return ((val
) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT
) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK
;
1463 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1464 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1465 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1466 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1468 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK
;
1470 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1471 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1472 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1474 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1476 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1477 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1478 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1480 return ((val
) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK
;
1483 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1484 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1485 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1486 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val
)
1488 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK
;
1490 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1491 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1492 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val
)
1494 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK
;
1496 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1497 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1498 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val
)
1500 return ((val
) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT
) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK
;
1503 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1504 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1505 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1506 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1508 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK
;
1510 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1511 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1512 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1514 return ((val
) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK
;
1517 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1518 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1519 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1520 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val
)
1522 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK
;
1524 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1525 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1526 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val
)
1528 return ((val
) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT
) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK
;
1531 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1532 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003
1533 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0
1534 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val
)
1536 return ((val
) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT
) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK
;
1538 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc
1539 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2
1540 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val
)
1542 return ((val
) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT
) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK
;
1544 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000
1545 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12
1546 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val
)
1548 return ((val
) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT
) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK
;
1550 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000
1551 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22
1552 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val
)
1554 return ((val
) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT
) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK
;
1557 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0
) { return 0x0000220b + 0x2*i0
; }
1559 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0
) { return 0x0000220b + 0x2*i0
; }
1561 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0
) { return 0x0000220c + 0x2*i0
; }
1563 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
1565 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212
1567 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
1569 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0
) { return 0x00002215 + 0x1*i0
; }
1571 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0
) { return 0x00002215 + 0x1*i0
; }
1573 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
1575 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
1577 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
1579 #define REG_A3XX_VFD_CONTROL_0 0x00002240
1580 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff
1581 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1582 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val
)
1584 return ((val
) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT
) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK
;
1586 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000
1587 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18
1588 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val
)
1590 return ((val
) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT
) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK
;
1592 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000
1593 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22
1594 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val
)
1596 return ((val
) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK
;
1598 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1599 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1600 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val
)
1602 return ((val
) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT
) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK
;
1605 #define REG_A3XX_VFD_CONTROL_1 0x00002241
1606 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1607 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1608 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val
)
1610 return ((val
) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT
) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK
;
1612 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1613 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1614 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val
)
1616 return ((val
) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK
;
1618 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1619 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1620 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val
)
1622 return ((val
) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT
) & A3XX_VFD_CONTROL_1_REGID4INST__MASK
;
1625 #define REG_A3XX_VFD_INDEX_MIN 0x00002242
1627 #define REG_A3XX_VFD_INDEX_MAX 0x00002243
1629 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244
1631 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1633 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1635 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1637 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0
) { return 0x00002246 + 0x2*i0
; }
1638 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1639 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1640 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val
)
1642 return ((val
) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK
;
1644 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80
1645 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1646 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val
)
1648 return ((val
) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK
;
1650 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000
1651 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000
1652 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000
1653 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18
1654 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val
)
1656 return ((val
) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK
;
1658 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000
1659 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24
1660 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val
)
1662 return ((val
) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT
) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK
;
1665 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0
) { return 0x00002247 + 0x2*i0
; }
1667 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1669 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0
) { return 0x00002266 + 0x1*i0
; }
1670 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1671 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1672 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val
)
1674 return ((val
) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT
) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK
;
1676 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1677 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1678 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1679 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val
)
1681 return ((val
) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT
) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK
;
1683 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1684 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1685 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val
)
1687 return ((val
) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT
) & A3XX_VFD_DECODE_INSTR_REGID__MASK
;
1689 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000
1690 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
1691 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
1692 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val
)
1694 return ((val
) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT
) & A3XX_VFD_DECODE_INSTR_SWAP__MASK
;
1696 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1697 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1698 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val
)
1700 return ((val
) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT
) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK
;
1702 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1703 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1705 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e
1706 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f
1707 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0
1708 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val
)
1710 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK
;
1712 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00
1713 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8
1714 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val
)
1716 return ((val
) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT
) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK
;
1719 #define REG_A3XX_VPC_ATTR 0x00002280
1720 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1721 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
1722 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val
)
1724 return ((val
) << A3XX_VPC_ATTR_TOTALATTR__SHIFT
) & A3XX_VPC_ATTR_TOTALATTR__MASK
;
1726 #define A3XX_VPC_ATTR_PSIZE 0x00000200
1727 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
1728 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1729 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val
)
1731 return ((val
) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT
) & A3XX_VPC_ATTR_THRDASSIGN__MASK
;
1733 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000
1734 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28
1735 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val
)
1737 return ((val
) << A3XX_VPC_ATTR_LMSIZE__SHIFT
) & A3XX_VPC_ATTR_LMSIZE__MASK
;
1740 #define REG_A3XX_VPC_PACK 0x00002281
1741 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1742 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1743 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val
)
1745 return ((val
) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT
) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK
;
1747 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1748 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1749 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val
)
1751 return ((val
) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT
) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK
;
1754 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1756 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0
) { return 0x00002282 + 0x1*i0
; }
1757 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003
1758 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0
1759 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val
)
1761 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK
;
1763 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c
1764 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2
1765 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val
)
1767 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK
;
1769 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030
1770 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4
1771 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val
)
1773 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK
;
1775 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0
1776 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6
1777 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val
)
1779 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK
;
1781 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300
1782 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8
1783 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val
)
1785 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK
;
1787 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00
1788 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10
1789 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val
)
1791 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK
;
1793 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000
1794 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12
1795 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val
)
1797 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK
;
1799 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000
1800 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14
1801 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val
)
1803 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK
;
1805 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000
1806 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16
1807 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val
)
1809 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK
;
1811 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000
1812 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18
1813 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val
)
1815 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK
;
1817 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000
1818 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20
1819 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val
)
1821 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK
;
1823 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000
1824 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22
1825 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val
)
1827 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK
;
1829 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000
1830 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24
1831 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val
)
1833 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK
;
1835 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000
1836 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26
1837 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val
)
1839 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK
;
1841 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000
1842 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28
1843 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val
)
1845 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK
;
1847 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000
1848 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30
1849 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val
)
1851 return ((val
) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT
) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK
;
1854 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1856 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0
) { return 0x00002286 + 0x1*i0
; }
1857 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003
1858 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0
1859 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val
)
1861 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK
;
1863 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c
1864 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2
1865 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val
)
1867 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK
;
1869 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030
1870 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4
1871 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val
)
1873 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK
;
1875 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0
1876 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6
1877 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val
)
1879 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK
;
1881 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300
1882 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8
1883 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val
)
1885 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK
;
1887 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00
1888 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10
1889 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val
)
1891 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK
;
1893 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000
1894 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12
1895 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val
)
1897 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK
;
1899 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000
1900 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14
1901 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val
)
1903 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK
;
1905 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000
1906 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16
1907 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val
)
1909 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK
;
1911 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000
1912 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18
1913 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val
)
1915 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK
;
1917 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000
1918 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20
1919 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val
)
1921 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK
;
1923 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000
1924 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22
1925 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val
)
1927 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK
;
1929 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000
1930 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24
1931 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val
)
1933 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK
;
1935 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000
1936 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26
1937 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val
)
1939 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK
;
1941 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000
1942 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28
1943 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val
)
1945 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK
;
1947 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000
1948 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30
1949 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val
)
1951 return ((val
) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT
) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK
;
1954 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
1956 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b
1958 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
1959 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
1960 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000
1961 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
1962 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val
)
1964 return ((val
) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK
;
1966 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000
1967 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
1968 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
1969 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val
)
1971 return ((val
) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK
;
1973 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000
1974 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22
1975 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val
)
1977 return ((val
) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT
) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK
;
1980 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
1981 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1982 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1983 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
1985 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK
;
1987 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
1988 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
1989 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
1991 return ((val
) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
1993 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1994 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1995 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1996 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
1998 return ((val
) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
2000 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
2001 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2002 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
2004 return ((val
) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
2006 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2007 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2008 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
2010 return ((val
) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
2012 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2013 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2014 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
2016 return ((val
) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
;
2018 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2019 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2020 #define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000
2021 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
2022 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
2023 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val
)
2025 return ((val
) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK
;
2028 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5
2029 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
2030 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2031 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
2033 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK
;
2035 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
2036 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
2037 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
2039 return ((val
) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
2041 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2042 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
2043 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
2045 return ((val
) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
2048 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6
2049 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2050 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
2051 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val
)
2053 return ((val
) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK
;
2055 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2056 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2057 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val
)
2059 return ((val
) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT
) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK
;
2061 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2062 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2063 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val
)
2065 return ((val
) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT
) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK
;
2068 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
2070 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0
) { return 0x000022c7 + 0x1*i0
; }
2071 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2072 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2073 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val
)
2075 return ((val
) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_A_REGID__MASK
;
2077 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2078 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2079 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val
)
2081 return ((val
) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK
;
2083 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2084 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2085 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val
)
2087 return ((val
) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT
) & A3XX_SP_VS_OUT_REG_B_REGID__MASK
;
2089 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2090 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2091 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val
)
2093 return ((val
) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK
;
2096 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
2098 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0
) { return 0x000022d0 + 0x1*i0
; }
2099 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2100 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2101 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val
)
2103 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
;
2105 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2106 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2107 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val
)
2109 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
;
2111 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2112 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2113 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val
)
2115 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
;
2117 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2118 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2119 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val
)
2121 return ((val
) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
;
2124 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
2125 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2126 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2127 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
2129 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
2131 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2132 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2133 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
2135 return ((val
) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
2138 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
2140 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
2142 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
2144 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
2146 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
2147 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
2148 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
2149 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
2151 return ((val
) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK
;
2154 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0
2155 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2156 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
2157 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val
)
2159 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK
;
2161 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2162 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2163 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val
)
2165 return ((val
) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK
;
2167 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2168 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2169 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2170 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
2172 return ((val
) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
2174 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
2175 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2176 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
2178 return ((val
) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
2180 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2181 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2182 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val
)
2184 return ((val
) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT
) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK
;
2186 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2187 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2188 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
2190 return ((val
) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
;
2192 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2193 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2194 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000
2195 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
2196 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
2197 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val
)
2199 return ((val
) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK
;
2202 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1
2203 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
2204 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2205 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val
)
2207 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK
;
2209 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
2210 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
2211 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val
)
2213 return ((val
) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT
) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK
;
2215 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
2216 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
2217 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val
)
2219 return ((val
) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT
) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK
;
2221 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
2222 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
2223 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val
)
2225 return ((val
) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT
) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK
;
2228 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
2229 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2230 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2231 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val
)
2233 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK
;
2235 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2236 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2237 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val
)
2239 return ((val
) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT
) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK
;
2242 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
2244 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
2246 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
2248 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
2250 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
2252 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
2254 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
2255 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003
2256 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
2257 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val
)
2259 return ((val
) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT
) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK
;
2261 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2262 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2263 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
2264 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val
)
2266 return ((val
) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT
) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK
;
2269 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
2271 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0
) { return 0x000022f0 + 0x1*i0
; }
2272 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2273 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
2274 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val
)
2276 return ((val
) << A3XX_SP_FS_MRT_REG_REGID__SHIFT
) & A3XX_SP_FS_MRT_REG_REGID__MASK
;
2278 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2279 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400
2280 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800
2282 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
2284 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0
) { return 0x000022f4 + 0x1*i0
; }
2285 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
2286 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
2287 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val
)
2289 return ((val
) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT
) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK
;
2292 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff
2293 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
2294 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0
2295 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val
)
2297 return ((val
) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT
) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK
;
2300 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301
2302 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340
2303 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
2304 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
2305 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
2307 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
2309 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
2310 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
2311 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
2313 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
2315 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
2316 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
2317 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
2319 return ((val
) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK
;
2322 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341
2324 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342
2325 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
2326 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
2327 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val
)
2329 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK
;
2331 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
2332 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
2333 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val
)
2335 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK
;
2337 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
2338 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
2339 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val
)
2341 return ((val
) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT
) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK
;
2344 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343
2346 #define REG_A3XX_VBIF_CLKON 0x00003001
2348 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c
2350 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d
2352 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e
2354 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c
2356 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d
2358 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2360 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2362 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2364 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2366 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2368 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034
2370 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035
2372 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036
2374 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c
2376 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2378 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058
2380 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e
2382 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
2384 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070
2385 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001
2386 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002
2387 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004
2388 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008
2389 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010
2391 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071
2392 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001
2393 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002
2394 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004
2395 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008
2396 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010
2398 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072
2400 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073
2402 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074
2404 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075
2406 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076
2408 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077
2410 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078
2412 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079
2414 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a
2416 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b
2418 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c
2420 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01
2421 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2422 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2423 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val
)
2425 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT
) & A3XX_VSC_BIN_SIZE_WIDTH__MASK
;
2427 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2428 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
2429 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val
)
2431 return ((val
>> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT
) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK
;
2434 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
2436 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
2438 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0
) { return 0x00000c06 + 0x3*i0
; }
2439 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
2440 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
2441 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val
)
2443 return ((val
) << A3XX_VSC_PIPE_CONFIG_X__SHIFT
) & A3XX_VSC_PIPE_CONFIG_X__MASK
;
2445 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00
2446 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10
2447 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val
)
2449 return ((val
) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT
) & A3XX_VSC_PIPE_CONFIG_Y__MASK
;
2451 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000
2452 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20
2453 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val
)
2455 return ((val
) << A3XX_VSC_PIPE_CONFIG_W__SHIFT
) & A3XX_VSC_PIPE_CONFIG_W__MASK
;
2457 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000
2458 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24
2459 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val
)
2461 return ((val
) << A3XX_VSC_PIPE_CONFIG_H__SHIFT
) & A3XX_VSC_PIPE_CONFIG_H__MASK
;
2464 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0
) { return 0x00000c07 + 0x3*i0
; }
2466 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0
) { return 0x00000c08 + 0x3*i0
; }
2468 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c
2469 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001
2471 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
2473 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
2475 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
2477 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
2479 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
2481 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81
2483 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
2485 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
2487 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
2489 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
2491 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
2493 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0
) { return 0x00000ca0 + 0x4*i0
; }
2495 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0
) { return 0x00000ca1 + 0x4*i0
; }
2497 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0
) { return 0x00000ca2 + 0x4*i0
; }
2499 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0
) { return 0x00000ca3 + 0x4*i0
; }
2501 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
2503 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1
2505 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
2507 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
2509 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
2510 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
2511 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
2512 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val
)
2514 return ((val
) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT
) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK
;
2516 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000
2517 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14
2518 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val
)
2520 return ((val
) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT
) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK
;
2523 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
2525 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
2527 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
2529 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
2531 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
2533 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
2535 #define REG_A3XX_UNKNOWN_0E43 0x00000e43
2537 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
2539 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
2541 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
2543 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
2545 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
2547 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
2549 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
2551 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
2553 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
2555 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
2557 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
2559 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
2561 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
2563 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
2564 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
2565 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
2566 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val
)
2568 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK
;
2571 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1
2572 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff
2573 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0
2574 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val
)
2576 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK
;
2578 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000
2579 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28
2580 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val
)
2582 return ((val
) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT
) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK
;
2584 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
2586 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6
2588 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
2590 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
2592 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6
2594 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7
2596 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8
2598 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9
2600 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca
2602 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb
2604 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0
2606 #define REG_A3XX_UNKNOWN_0F03 0x00000f03
2608 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
2610 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
2612 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
2614 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
2616 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
2618 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
2620 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0
2622 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
2624 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
2625 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
2626 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
2627 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val
)
2629 return ((val
) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK
;
2631 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
2632 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
2633 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val
)
2635 return ((val
) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK
;
2637 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
2638 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
2639 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val
)
2641 return ((val
) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK
;
2643 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
2644 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
2645 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val
)
2647 return ((val
) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK
;
2649 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
2650 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
2651 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
2652 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000
2653 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24
2654 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val
)
2656 return ((val
) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT
) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK
;
2659 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd
2661 #define REG_A3XX_TEX_SAMP_0 0x00000000
2662 #define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001
2663 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
2664 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
2665 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
2666 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val
)
2668 return ((val
) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT
) & A3XX_TEX_SAMP_0_XY_MAG__MASK
;
2670 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030
2671 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4
2672 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val
)
2674 return ((val
) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT
) & A3XX_TEX_SAMP_0_XY_MIN__MASK
;
2676 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0
2677 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6
2678 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val
)
2680 return ((val
) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_S__MASK
;
2682 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00
2683 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9
2684 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val
)
2686 return ((val
) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_T__MASK
;
2688 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000
2689 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12
2690 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val
)
2692 return ((val
) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT
) & A3XX_TEX_SAMP_0_WRAP_R__MASK
;
2694 #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000
2695 #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15
2696 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val
)
2698 return ((val
) << A3XX_TEX_SAMP_0_ANISO__SHIFT
) & A3XX_TEX_SAMP_0_ANISO__MASK
;
2700 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000
2701 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20
2702 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val
)
2704 return ((val
) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT
) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK
;
2706 #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000
2707 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
2709 #define REG_A3XX_TEX_SAMP_1 0x00000001
2710 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff
2711 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0
2712 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val
)
2714 return ((((int32_t)(val
* 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT
) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK
;
2716 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000
2717 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12
2718 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val
)
2720 return ((((uint32_t)(val
* 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT
) & A3XX_TEX_SAMP_1_MAX_LOD__MASK
;
2722 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000
2723 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22
2724 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val
)
2726 return ((((uint32_t)(val
* 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT
) & A3XX_TEX_SAMP_1_MIN_LOD__MASK
;
2729 #define REG_A3XX_TEX_CONST_0 0x00000000
2730 #define A3XX_TEX_CONST_0_TILED 0x00000001
2731 #define A3XX_TEX_CONST_0_SRGB 0x00000004
2732 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2733 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2734 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val
)
2736 return ((val
) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_X__MASK
;
2738 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2739 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2740 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val
)
2742 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Y__MASK
;
2744 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2745 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2746 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val
)
2748 return ((val
) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_Z__MASK
;
2750 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2751 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2752 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val
)
2754 return ((val
) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT
) & A3XX_TEX_CONST_0_SWIZ_W__MASK
;
2756 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2757 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2758 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val
)
2760 return ((val
) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT
) & A3XX_TEX_CONST_0_MIPLVLS__MASK
;
2762 #define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000
2763 #define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20
2764 static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val
)
2766 return ((val
) << A3XX_TEX_CONST_0_MSAATEX__SHIFT
) & A3XX_TEX_CONST_0_MSAATEX__MASK
;
2768 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2769 #define A3XX_TEX_CONST_0_FMT__SHIFT 22
2770 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val
)
2772 return ((val
) << A3XX_TEX_CONST_0_FMT__SHIFT
) & A3XX_TEX_CONST_0_FMT__MASK
;
2774 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000
2775 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
2776 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30
2777 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val
)
2779 return ((val
) << A3XX_TEX_CONST_0_TYPE__SHIFT
) & A3XX_TEX_CONST_0_TYPE__MASK
;
2782 #define REG_A3XX_TEX_CONST_1 0x00000001
2783 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
2784 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0
2785 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val
)
2787 return ((val
) << A3XX_TEX_CONST_1_HEIGHT__SHIFT
) & A3XX_TEX_CONST_1_HEIGHT__MASK
;
2789 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000
2790 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14
2791 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val
)
2793 return ((val
) << A3XX_TEX_CONST_1_WIDTH__SHIFT
) & A3XX_TEX_CONST_1_WIDTH__MASK
;
2795 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000
2796 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28
2797 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val
)
2799 return ((val
) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT
) & A3XX_TEX_CONST_1_FETCHSIZE__MASK
;
2802 #define REG_A3XX_TEX_CONST_2 0x00000002
2803 #define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff
2804 #define A3XX_TEX_CONST_2_INDX__SHIFT 0
2805 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val
)
2807 return ((val
) << A3XX_TEX_CONST_2_INDX__SHIFT
) & A3XX_TEX_CONST_2_INDX__MASK
;
2809 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000
2810 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12
2811 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val
)
2813 return ((val
) << A3XX_TEX_CONST_2_PITCH__SHIFT
) & A3XX_TEX_CONST_2_PITCH__MASK
;
2815 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2816 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30
2817 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val
)
2819 return ((val
) << A3XX_TEX_CONST_2_SWAP__SHIFT
) & A3XX_TEX_CONST_2_SWAP__MASK
;
2822 #define REG_A3XX_TEX_CONST_3 0x00000003
2823 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff
2824 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
2825 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val
)
2827 return ((val
>> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT
) & A3XX_TEX_CONST_3_LAYERSZ1__MASK
;
2829 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000
2830 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17
2831 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val
)
2833 return ((val
) << A3XX_TEX_CONST_3_DEPTH__SHIFT
) & A3XX_TEX_CONST_3_DEPTH__MASK
;
2835 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000
2836 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28
2837 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val
)
2839 return ((val
>> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT
) & A3XX_TEX_CONST_3_LAYERSZ2__MASK
;
2843 #endif /* A3XX_XML */