src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_util.h"
  43 #include "fd3_zsa.h"
  44
  45
  46 static void
  47 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  48                 struct fd3_emit *emit)
  49 {
  50         const struct pipe_draw_info *info = emit->info;
  51
  52         fd3_emit_state(ctx, ring, emit);
  53
  54         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  55                 fd3_emit_vertex_bufs(ring, emit);
  56
  57         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  58         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  59
  60         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  61         OUT_RING(ring, info->min_index);        /* VFD_INDEX_MIN */
  62         OUT_RING(ring, info->max_index);        /* VFD_INDEX_MAX */
  63         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  64         OUT_RING(ring, info->start);            /* VFD_INDEX_OFFSET */
  65
  66         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  67         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  68                         info->restart_index : 0xffffffff);
  69
  70         fd_draw_emit(ctx, ring,
  71                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  72                         info);
  73 }
  74
  75 /* fixup dirty shader state in case some "unrelated" (from the state-
  76  * tracker's perspective) state change causes us to switch to a
  77  * different variant.
  78  */
  79 static void
  80 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  81 {
  82         struct fd3_context *fd3_ctx = fd3_context(ctx);
  83         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
  84
  85         if (!ir3_shader_key_equal(last_key, key)) {
  86                 ctx->dirty |= FD_DIRTY_PROG;
  87
  88                 if (last_key->has_per_samp || key->has_per_samp) {
  89                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  90                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  91                                         (last_key->vsaturate_r != key->vsaturate_r))
  92                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
  93
  94                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
  95                                         (last_key->fsaturate_t != key->fsaturate_t) ||
  96                                         (last_key->fsaturate_r != key->fsaturate_r))
  97                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  98                 }
  99
 100                 if (last_key->color_two_side != key->color_two_side)
 101                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 102
 103                 if (last_key->half_precision != key->half_precision)
 104                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 105
 106                 if (last_key->alpha != key->alpha)
 107                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 108
 109                 fd3_ctx->last_key = *key;
 110         }
 111 }
 112
 113 static void
 114 fd3_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
 115 {
 116         struct fd3_context *fd3_ctx = fd3_context(ctx);
 117         struct fd3_emit emit = {
 118                 .vtx  = &ctx->vtx,
 119                 .prog = &ctx->prog,
 120                 .info = info,
 121                 .key = {
 122                         /* do binning pass first: */
 123                         .binning_pass = true,
 124                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 125                         .alpha = util_format_is_alpha(pipe_surface_format(ctx->framebuffer.cbufs[0])),
 126                         // TODO set .half_precision based on render target format,
 127                         // ie. float16 and smaller use half, float32 use full..
 128                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 129                         .has_per_samp = fd3_ctx->fsaturate || fd3_ctx->vsaturate,
 130                         .vsaturate_s = fd3_ctx->vsaturate_s,
 131                         .vsaturate_t = fd3_ctx->vsaturate_t,
 132                         .vsaturate_r = fd3_ctx->vsaturate_r,
 133                         .fsaturate_s = fd3_ctx->fsaturate_s,
 134                         .fsaturate_t = fd3_ctx->fsaturate_t,
 135                         .fsaturate_r = fd3_ctx->fsaturate_r,
 136                 },
 137                 .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 138         };
 139         uint32_t dirty, vconst;
 140
 141         fixup_shader_state(ctx, &emit.key);
 142
 143         /* save/restore vertex const state too, so that vertex
 144          * shader consts also get emitted for render pass:
 145          */
 146         vconst = ctx->constbuf[PIPE_SHADER_VERTEX].dirty_mask;
 147
 148         dirty = ctx->dirty;
 149         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 150         draw_impl(ctx, ctx->binning_ring, &emit);
 151
 152         ctx->constbuf[PIPE_SHADER_VERTEX].dirty_mask = vconst;
 153
 154         /* and now regular (non-binning) pass: */
 155         emit.key.binning_pass = false;
 156         emit.dirty = dirty;
 157         emit.vp = NULL;   /* we changed key so need to refetch vp */
 158         draw_impl(ctx, ctx->ring, &emit);
 159 }
 160
 161 /* clear operations ignore viewport state, so we need to reset it
 162  * based on framebuffer state:
 163  */
 164 static void
 165 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 166 {
 167         float half_width = pfb->width * 0.5f;
 168         float half_height = pfb->height * 0.5f;
 169
 170         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 171         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 172         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 173         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 174         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 175 }
 176
 177 /* binning pass cmds for a clear:
 178  * NOTE: newer blob drivers don't use binning for clear, which is probably
 179  * preferable since it is low vtx count.  However that doesn't seem to
 180  * actually work for me.  Not sure if it is depending on support for
 181  * clear pass (rather than using solid-fill shader), or something else
 182  * that newer blob is doing differently.  Once that is figured out, we
 183  * can remove fd3_clear_binning().
 184  */
 185 static void
 186 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 187 {
 188         struct fd3_context *fd3_ctx = fd3_context(ctx);
 189         struct fd_ringbuffer *ring = ctx->binning_ring;
 190         struct fd3_emit emit = {
 191                 .vtx  = &fd3_ctx->solid_vbuf_state,
 192                 .prog = &ctx->solid_prog,
 193                 .key = {
 194                         .binning_pass = true,
 195                         .half_precision = true,
 196                 },
 197                 .dirty = dirty,
 198         };
 199
 200         fd3_emit_state(ctx, ring, &emit);
 201         fd3_emit_vertex_bufs(ring, &emit);
 202         reset_viewport(ring, &ctx->framebuffer);
 203
 204         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 205         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 206                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 207                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 208                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 209         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 210         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 211         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 212         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 213         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 214         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 215         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 216
 217         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 218
 219         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 220                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 221 }
 222
 223 static void
 224 fd3_clear(struct fd_context *ctx, unsigned buffers,
 225                 const union pipe_color_union *color, double depth, unsigned stencil)
 226 {
 227         struct fd3_context *fd3_ctx = fd3_context(ctx);
 228         struct fd_ringbuffer *ring = ctx->ring;
 229         unsigned dirty = ctx->dirty;
 230         unsigned ce, i;
 231         struct fd3_emit emit = {
 232                 .vtx  = &fd3_ctx->solid_vbuf_state,
 233                 .prog = &ctx->solid_prog,
 234                 .key = {
 235                         .half_precision = true,
 236                 },
 237         };
 238
 239         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 240         dirty |= FD_DIRTY_PROG;
 241         emit.dirty = dirty;
 242
 243         fd3_clear_binning(ctx, dirty);
 244
 245         /* emit generic state now: */
 246         fd3_emit_state(ctx, ring, &emit);
 247         reset_viewport(ring, &ctx->framebuffer);
 248
 249         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 250         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 251                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 252
 253         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 254         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 255                         &fd3_ctx->rbrc_patches);
 256
 257         if (buffers & PIPE_CLEAR_DEPTH) {
 258                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 259                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 260                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 261                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 262
 263                 fd_wfi(ctx, ring);
 264                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 265                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 266                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 267                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 268         } else {
 269                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 270                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 271         }
 272
 273         if (buffers & PIPE_CLEAR_STENCIL) {
 274                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 275                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 276                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 277                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 278                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 279                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 280                                 0xff000000 | // XXX ???
 281                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 282
 283                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 284                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 285                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 286                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 287                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 288                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 289                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 290                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 291                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 292                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 293         } else {
 294                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 295                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 296                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 297                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 298                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 299                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 300                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 301
 302                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 303                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 304                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 305                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 306                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 307                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 308                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 309                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 310                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 311         }
 312
 313         if (buffers & PIPE_CLEAR_COLOR) {
 314                 ce = 0xf;
 315         } else {
 316                 ce = 0x0;
 317         }
 318
 319         for (i = 0; i < 4; i++) {
 320                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 321                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 322                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 323                                 A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 324
 325                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 326                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 327                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 328                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 329                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 330                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 331                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO) |
 332                                 A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE);
 333         }
 334
 335         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 336         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 337
 338         fd3_emit_vertex_bufs(ring, &emit);
 339
 340         ctx->constbuf[PIPE_SHADER_FRAGMENT].dirty_mask = ~0;
 341         fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 342
 343         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 344         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 345                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 346                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 347                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 348         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 349         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 350         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 351         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 352         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 353         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 354         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 355
 356         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 357
 358         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 359                         DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL);
 360 }
 361
 362 void
 363 fd3_draw_init(struct pipe_context *pctx)
 364 {
 365         struct fd_context *ctx = fd_context(pctx);
 366         ctx->draw = fd3_draw;
 367         ctx->clear = fd3_clear;
 368 }