src/gallium/drivers/freedreno/a3xx/fd3_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33 #include "util/u_format.h"
  34
  35 #include "freedreno_state.h"
  36 #include "freedreno_resource.h"
  37
  38 #include "fd3_draw.h"
  39 #include "fd3_context.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_program.h"
  42 #include "fd3_format.h"
  43 #include "fd3_zsa.h"
  44
  45 static inline uint32_t
  46 add_sat(uint32_t a, int32_t b)
  47 {
  48         int64_t ret = (uint64_t)a + (int64_t)b;
  49         if (ret > ~0U)
  50                 return ~0U;
  51         if (ret < 0)
  52                 return 0;
  53         return (uint32_t)ret;
  54 }
  55
  56 static void
  57 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  58                 struct fd3_emit *emit)
  59 {
  60         const struct pipe_draw_info *info = emit->info;
  61         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  62
  63         fd3_emit_state(ctx, ring, emit);
  64
  65         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  66                 fd3_emit_vertex_bufs(ring, emit);
  67
  68         OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
  69         OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */
  70
  71         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
  72         OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
  73         OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
  74         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
  75         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  76
  77         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
  78         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  79                         info->restart_index : 0xffffffff);
  80
  81         /* points + psize -> spritelist: */
  82         if (ctx->rasterizer->point_size_per_vertex &&
  83                         fd3_emit_get_vp(emit)->writes_psize &&
  84                         (info->mode == PIPE_PRIM_POINTS))
  85                 primtype = DI_PT_POINTLIST_PSIZE;
  86
  87         fd_draw_emit(ctx, ring,
  88                         primtype,
  89                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  90                         info);
  91 }
  92
  93 /* fixup dirty shader state in case some "unrelated" (from the state-
  94  * tracker's perspective) state change causes us to switch to a
  95  * different variant.
  96  */
  97 static void
  98 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  99 {
 100         struct fd3_context *fd3_ctx = fd3_context(ctx);
 101         struct ir3_shader_key *last_key = &fd3_ctx->last_key;
 102
 103         if (!ir3_shader_key_equal(last_key, key)) {
 104                 if (last_key->has_per_samp || key->has_per_samp) {
 105                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
 106                                         (last_key->vsaturate_t != key->vsaturate_t) ||
 107                                         (last_key->vsaturate_r != key->vsaturate_r))
 108                                 ctx->dirty |= FD_SHADER_DIRTY_VP;
 109
 110                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 111                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 112                                         (last_key->fsaturate_r != key->fsaturate_r))
 113                                 ctx->dirty |= FD_SHADER_DIRTY_FP;
 114                 }
 115
 116                 if (last_key->vclamp_color != key->vclamp_color)
 117                         ctx->dirty |= FD_SHADER_DIRTY_VP;
 118
 119                 if (last_key->fclamp_color != key->fclamp_color)
 120                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 121
 122                 if (last_key->color_two_side != key->color_two_side)
 123                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 124
 125                 if (last_key->half_precision != key->half_precision)
 126                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 127
 128                 fd3_ctx->last_key = *key;
 129         }
 130 }
 131
 132 static bool
 133 fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 134 {
 135         struct fd3_context *fd3_ctx = fd3_context(ctx);
 136         struct fd3_emit emit = {
 137                 .debug = &ctx->debug,
 138                 .vtx  = &ctx->vtx,
 139                 .prog = &ctx->prog,
 140                 .info = info,
 141                 .key = {
 142                         .color_two_side = ctx->rasterizer->light_twoside,
 143                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 144                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 145                         // TODO set .half_precision based on render target format,
 146                         // ie. float16 and smaller use half, float32 use full..
 147                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 148                         .has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate),
 149                         .vsaturate_s = fd3_ctx->vsaturate_s,
 150                         .vsaturate_t = fd3_ctx->vsaturate_t,
 151                         .vsaturate_r = fd3_ctx->vsaturate_r,
 152                         .fsaturate_s = fd3_ctx->fsaturate_s,
 153                         .fsaturate_t = fd3_ctx->fsaturate_t,
 154                         .fsaturate_r = fd3_ctx->fsaturate_r,
 155                 },
 156                 .rasterflat = ctx->rasterizer->flatshade,
 157                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 158                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 159         };
 160
 161         fixup_shader_state(ctx, &emit.key);
 162
 163         unsigned dirty = ctx->dirty;
 164
 165         /* do regular pass first, since that is more likely to fail compiling: */
 166
 167         if (!(fd3_emit_get_vp(&emit) && fd3_emit_get_fp(&emit)))
 168                 return false;
 169
 170         emit.key.binning_pass = false;
 171         emit.dirty = dirty;
 172         draw_impl(ctx, ctx->ring, &emit);
 173
 174         /* and now binning pass: */
 175         emit.key.binning_pass = true;
 176         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 177         emit.vp = NULL;   /* we changed key so need to refetch vp */
 178         emit.fp = NULL;
 179         draw_impl(ctx, ctx->binning_ring, &emit);
 180
 181         return true;
 182 }
 183
 184 /* clear operations ignore viewport state, so we need to reset it
 185  * based on framebuffer state:
 186  */
 187 static void
 188 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 189 {
 190         float half_width = pfb->width * 0.5f;
 191         float half_height = pfb->height * 0.5f;
 192
 193         OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
 194         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
 195         OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
 196         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
 197         OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
 198 }
 199
 200 /* binning pass cmds for a clear:
 201  * NOTE: newer blob drivers don't use binning for clear, which is probably
 202  * preferable since it is low vtx count.  However that doesn't seem to
 203  * actually work for me.  Not sure if it is depending on support for
 204  * clear pass (rather than using solid-fill shader), or something else
 205  * that newer blob is doing differently.  Once that is figured out, we
 206  * can remove fd3_clear_binning().
 207  */
 208 static void
 209 fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
 210 {
 211         struct fd3_context *fd3_ctx = fd3_context(ctx);
 212         struct fd_ringbuffer *ring = ctx->binning_ring;
 213         struct fd3_emit emit = {
 214                 .debug = &ctx->debug,
 215                 .vtx  = &fd3_ctx->solid_vbuf_state,
 216                 .prog = &ctx->solid_prog,
 217                 .key = {
 218                         .binning_pass = true,
 219                         .half_precision = true,
 220                 },
 221                 .dirty = dirty,
 222         };
 223
 224         fd3_emit_state(ctx, ring, &emit);
 225         fd3_emit_vertex_bufs(ring, &emit);
 226         reset_viewport(ring, &ctx->framebuffer);
 227
 228         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 229         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 230                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 231                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 232                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 233         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 234         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 235         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 236         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 237         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 238         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 239         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 240
 241         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 242
 243         fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 244                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 245 }
 246
 247 static void
 248 fd3_clear(struct fd_context *ctx, unsigned buffers,
 249                 const union pipe_color_union *color, double depth, unsigned stencil)
 250 {
 251         struct fd3_context *fd3_ctx = fd3_context(ctx);
 252         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 253         struct fd_ringbuffer *ring = ctx->ring;
 254         unsigned dirty = ctx->dirty;
 255         unsigned i;
 256         struct fd3_emit emit = {
 257                 .debug = &ctx->debug,
 258                 .vtx  = &fd3_ctx->solid_vbuf_state,
 259                 .prog = &ctx->solid_prog,
 260                 .key = {
 261                         .half_precision = fd_half_precision(pfb),
 262                 },
 263         };
 264
 265         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 266         dirty |= FD_DIRTY_PROG;
 267         emit.dirty = dirty;
 268
 269         fd3_clear_binning(ctx, dirty);
 270
 271         /* emit generic state now: */
 272         fd3_emit_state(ctx, ring, &emit);
 273         reset_viewport(ring, &ctx->framebuffer);
 274
 275         OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
 276         OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
 277                         A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
 278
 279         OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
 280         OUT_RINGP(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER),
 281                         &fd3_ctx->rbrc_patches);
 282
 283         if (buffers & PIPE_CLEAR_DEPTH) {
 284                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 285                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 286                                 A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
 287                                 A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 288
 289                 fd_wfi(ctx, ring);
 290                 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2);
 291                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
 292                 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth));
 293                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 294         } else {
 295                 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
 296                 OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 297         }
 298
 299         if (buffers & PIPE_CLEAR_STENCIL) {
 300                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 301                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 302                                 A3XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 303                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 304                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 305                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 306                                 0xff000000 | // XXX ???
 307                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 308
 309                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 310                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 311                                 A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 312                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 313                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 314                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 315                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 316                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 317                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 318                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 319         } else {
 320                 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
 321                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_STENCILREF(0) |
 322                                 A3XX_RB_STENCILREFMASK_STENCILMASK(0) |
 323                                 A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 324                 OUT_RING(ring, A3XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 325                                 A3XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 326                                 A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 327
 328                 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
 329                 OUT_RING(ring, A3XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 330                                 A3XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 331                                 A3XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 332                                 A3XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 333                                 A3XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 334                                 A3XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 335                                 A3XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 336                                 A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 337         }
 338
 339         for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
 340                 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
 341                 OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 342                                 A3XX_RB_MRT_CONTROL_DITHER_MODE(DITHER_ALWAYS) |
 343                                 COND(buffers & (PIPE_CLEAR_COLOR0 << i),
 344                                          A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)));
 345
 346                 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
 347                 OUT_RING(ring, A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 348                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 349                                 A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 350                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 351                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 352                                 A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 353         }
 354
 355         OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
 356         OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 357
 358         fd3_emit_vertex_bufs(ring, &emit);
 359
 360         fd3_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 361
 362         OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
 363         OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
 364                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 365                         A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES) |
 366                         A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 367         OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
 368         OUT_RING(ring, 0);            /* VFD_INDEX_MIN */
 369         OUT_RING(ring, 2);            /* VFD_INDEX_MAX */
 370         OUT_RING(ring, 0);            /* VFD_INSTANCEID_OFFSET */
 371         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 372         OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
 373         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 374
 375         fd_event_write(ctx, ring, PERFCOUNTER_STOP);
 376
 377         fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 378                         DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL);
 379 }
 380
 381 void
 382 fd3_draw_init(struct pipe_context *pctx)
 383 {
 384         struct fd_context *ctx = fd_context(pctx);
 385         ctx->draw_vbo = fd3_draw_vbo;
 386         ctx->clear = fd3_clear;
 387 }